JP3810352B2

JP3810352B2 - Package for housing input/output terminals and semiconductor elements

Info

Publication number: JP3810352B2
Application number: JP2002214398A
Authority: JP
Inventors: 義明植田
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2002-07-23
Filing date: 2002-07-23
Publication date: 2006-08-16
Anticipated expiration: 2022-07-23
Also published as: JP2004056013A

Description

【０００１】
【発明の属する技術分野】
本発明は、ＩＣ，ＬＳＩ等の半導体素子を収納するための半導体素子収納用パッケージに用いられる入出力端子および半導体素子収納用パッケージに関する。
【０００２】
【従来の技術】
近時の無線通信に使用される通信機器の発達に伴って、高周波帯域で高出力で作動するＩＣ，ＬＳＩ等の半導体素子の需要が大幅に伸びている。特に携帯電話の基地局に用いられる情報機器等では、限られた電力で高出力が得られ長時間の信号変換ができるように高効率で動作する高出力用の半導体素子と、これを収納する半導体素子収納用パッケージ（以下、半導体パッケージともいう）が重要となってきている。即ち、半導体素子内部での電力損失が小さく、印加する直流電力を効率よく高周波電力に変換する半導体素子と、この半導体素子を収納して、その性能を最大限引き出せる半導体パッケージが望まれている。
【０００３】
このようなことから、ガリウム砒素（ＧａＡｓ）化合物半導体を用いたＭＥＳＦＥＴ（Metal Semiconductor Field Effect Transistor:金属半導体電界効果トランジスタ）の開発が進められてきたが、低電圧時の特性および変換効率が悪く、また大電流を流せないという点で問題があった。しかしながら、近年、ＧａＡｓ化合物半導体系ＨＢＴ（Heterojunction Bipolar Transistor：ヘテロ接合バイポーラトランジスタ）などの半導体素子が、ＭＥＳＦＥＴに比し優れた低電圧時の特性を有し、また大きな直流電力を効率よく高周波電力に変換できる半導体素子として注目されてきている。また、このような半導体素子は作動時に大量の熱を発生するため、熱放散性の良好な半導体パッケージが強く望まれている。
【０００４】
このような半導体素子を収納する半導体パッケージを図３の斜視図に示す。図３は入出力端子Ｂを用いた半導体パッケージＡを示し、この入出力端子Ｂは、図４の斜視図に示すように、セラミックグリーンシート積層法によって作製される縦断面形状が凸型のものであり、セラミックスからなる平板部１および平板部１上面に線路導体３の一部（中央部）を間に挟んで取着されたセラミックスからなる立壁部２とで構成されている。この入出力端子Ｂは、図３に示すように、基体７の上面の外周部に載置部７ａを囲むようにして接合された枠体８の取付部８ａに嵌着され、例えば半導体パッケージＡに収納される半導体素子Ｃに対して高周波電力の出力用として機能する。
【０００５】
基体７は高い熱放散性が要求されることから銅（Ｃｕ）−タングステン（Ｗ）やＣｕからなる場合が多く、また、枠体８としては入出力端子Ｂと熱膨張係数が近い鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金が多く用いられている。とりわけ大量の熱を外部に放散させる必要がある場合、Ｆｅ−Ｎｉ−Ｃｏ合金に対して200〜300℃での熱膨張係数が近似するＣｕ−Ｗ合金が賞用されている。これは、この温度域における熱膨張係数が５×10^-6〜８×10^-6／℃程度の範囲となるように材料設計をすることが可能であり、よってこれらの合金の熱膨張係数を近似させることができ、これにより基体７に大きな反りが発生しないからである。
【０００６】
また、入出力端子Ｂの平板部１の下面の略全面には下部接地導体層４が形成され、平板部１および立壁部２の線路方向に略平行な両側面には側部接地導体層５が形成され、また立壁部２の上面の略全面には上部接地導体層６が形成され、これらの下部接地導体層４、側部接地導体層５および上部接地導体層６が線路導体３を囲むようにして配置されて、導波管構造を成している。
【０００７】
この立壁部２の線路方向に略直交する方向の幅は枠体８の幅と略同じであり、例えば銀（Ａｇ）ロウを介して入出力端子Ｂを枠体８の取付部８ａに嵌着した場合、立壁部２の線路方向に略直交する側面２ｂと取付部９ａの内面との間に大きなメニスカスが生じないようにされている。これにより、半導体パッケージＡの温度が上昇した場合にＡｇロウが立壁部２の表面を引張る応力を小さくすることができ、立壁部２の上面と線路方向に略直交する側面２ｂとの間の稜部２ａに応力が集中するのを回避している。
【０００８】
また、上記のように立壁部２の幅を枠体８の厚さと略同じにするのは、立壁部２の幅は高周波信号の挿入損失を小さくするために狭いほうが良く、一方枠体８の厚さは接合の信頼性を得るためにできるだけ広いほうが良く、相反する二つの条件を実質的に満たすためである。現状ではそれぞれの幅を略同じとし、0.25〜1.0ｍｍの間に設定されていることが多い。
【０００９】
【発明が解決しようとする課題】
しかしながら、図４に示すような従来の入出力端子Ｂを用いる半導体パッケージＡでは、Ａｇロウを用いて入出力端子Ｂを取付部８ａに接合するに際して例えば850℃程度の温度で加熱する必要があり、このときＣｕ−Ｗからなる基体７に比べてＦｅ−Ｎｉ−Ｃｏ合金からなる枠体８が外側方向に広がった状態で溶融したＡｇロウが固化していき、温度が下がるに伴って枠体８が元に戻ろうとする際に立壁部２の上面の枠体８外側に向いた稜部２ａを起点としてマイクロクラックが発生する。このとき、上部接地導体層６に対してこれを剥がそうとする力が作用し、その結果、半導体パッケージの気密性が損なわれるという不具合を招来していた。
【００１０】
これは、Ｆｅ−Ｎｉ−Ｃｏ合金が420℃付近で熱膨張係数の変曲点を有しているためであり、室温からこの温度までは約5.5×10^-6／℃の熱膨張係数を有しているが、この温度を超えると約11.3×10^-6／℃の熱膨張係数を有することに起因している。即ち、850℃ではＣｕ−Ｗ合金よりも大きい熱膨張率で膨張するために、この温度よりも若干下がった共晶点でＡｇロウが固化し、このとき枠体８の上部が拡がった状態で入出力端子Ｂが固定され、その後温度が下がるにつれて枠体８が元に戻ろうとする。このとき発生する応力が、上部接地導体層６の縁端部、特に立壁部２の枠体８外側に向いた稜部２ａに集中するため、稜部２ａに小さなクラックが発生する。このクラックを起点として、上部接地導体層６に入出力端子Ｂの表面とともに剥そうとする力が作用してクラックが成長していき、遂には立壁部２の上面における対向する稜部２ａに発生するクラックに繋がってしまう場合があり、このとき半導体パッケージＡの気密性が損なわれてしまう。
【００１１】
そこで、稜部２ａに大きな応力が集中しないようにするために、枠体８ａの厚さを入出力端子Ｂの取付部８ａ付近に限って局部的に薄くし、それに対応して立壁部２の線路方向の厚さを薄くすることが行われていたが、この場合立壁部２の接合部の接合強度が小さくなることによって、小さな力でＡｇロウにクラックが発生する場合があり、これによって半導体パッケージＡの気密性が損なわれる場合があった。
【００１２】
また、入出力端子Ｂの線路方向に平行な方向の長さをそのままにして立壁部２の線路方向に平行な方向の厚さを大きくすることにより稜部２ａを枠体８から遠ざけ、これにより稜部２ａへの応力集中を緩和することも考えられるが、この場合平板部１上面における線路導体３のワイヤボンディング領域やリード端子（図示せず）の接合領域が狭くなり、これを回避するために入出力端子Ｂのサイズを大きくせざるを得なくなる。その結果、半導体パッケージＡ全体のサイズが大きくなってしまうという不具合が発生していた。
【００１３】
従って、本発明は上記問題点に鑑み完成されたものであり、その目的は、入出力端子の立壁部の上面における稜部を起点としてクラックが発生するのを防いで、立壁部上面の上部接地導体層を剥す力が作用しても容易にクラックが成長することがない入出力端子および半導体パッケージを提供することにある。
【００１４】
【課題を解決するための手段】
本発明の入出力端子は、上面に一辺から対向する他辺にかけて線路導体が形成されたセラミックスから成る略四角形の平板部および該平板部の上面に前記線路導体の一部を間に挟んで接合されたセラミックスから成る立壁部から構成されており、前記立壁部の上面の略全面に上部接地導体層が形成されているとともに前記平板部の下面の略全面に下部接地導体層が形成され、さらに前記線路導体の線路方向に略平行な両側面に側部接地導体層がそれぞれ形成されている入出力端子において、前記上部接地導体層は、前記立壁部の上面から前記立壁部の前記線路導体に略直交する両側面にかけて、前記線路導体の直上に位置する部位に上下方向の幅が0.05乃至0.1ｍｍの第一の延出部が形成され、その他の部位に上下方向の幅が0.05乃至0.3ｍｍの第二の延出部が形成されていることを特徴とする。
【００１５】
本発明の入出力端子は、立壁部の上面から線路導体に略直交する両側面にかけて、線路導体の直上に位置する部位に上下方向の幅が0.05〜0.1ｍｍの第一の延出部が形成され、その他の部位に上下方向の幅が0.05〜0.3ｍｍの第二の延出部が形成されていることから、立壁部の平板部の上面に略直交する両側面上端の稜部付近が、上部接地導体層によって押え込まれた状態となってクラックの発生が抑えられ、上部接地導体層の外周部が延出部によって容易に剥れなくなるようにすることができる。また、このとき、上部接地導体層と線路導体との間に発生する浮遊容量を小さくすることができる。
【００１６】
本発明の半導体素子収納用パッケージは、上面に半導体素子を載置する載置部が設けられた基体と、該基体の上面に前記載置部を囲繞するように接合され、側部に貫通孔または切欠きからなる入出力端子の取付部が形成された枠体と、前記取付部に嵌着された上記本発明の入出力端子とを具備したことを特徴とする。
【００１７】
本発明の半導体素子収納用パッケージは、上記の構成により、入出力端子を枠体の取付部にロウ材を介して嵌着させる際に立壁部に発生するクラックに起因して上部接地導体層が剥れるのを防止することができるとともに、上部接地導体層と線路導体との間で新たに発生する浮遊容量を最小限にすることにより、半導体素子収納用パッケージ内における高周波信号の共振点の低下を防止することができる。
【００１８】
【発明の実施の形態】
本発明の入出力端子および半導体素子収納用パッケージを以下に詳細に説明する。図１は、本発明の入出力端子を用いた半導体パッケージについて実施の形態の一例を示す部分拡大断面図であり、また図２（ａ）は本発明の入出力端子の正面図を、同図（ｂ）は入出力端子の斜視図をそれぞれ示す。なお、図１、図２において従来例を示す図３、図４と同じ部位には同じ符号を付した。
【００１９】
図１、図２において、１は平板部、２は平板部１上に接合された立壁部、２ａは立壁部２の線路導体３に略直交する側面の上端の稜部、２ｂは立壁部２の線路導体３に略直交する側面、２ｃは立壁部２を構成する最上層の絶縁層（セラミック層）、２ｄは立壁部２を構成する上から２番目の絶縁層、３は平板部１の上面に形成された線路導体である。また、４は平板部１の下面の略全面に形成された下部接地導体層、５は平板部１および立壁部２の線路方向に略平行な両側面に形成された側部接地導体層、６は立壁部２の上面の略全面に形成された上部接地導体層、６ａは上部接地導体層６の延出部、６ａ−１は第一の延出部、６ａ−２は第二の延出部、７は基体、７ａは半導体素子Ｃの載置部、８は枠体、８ａは取付部である。
【００２０】
本発明の入出力端子Ｂは、上面に一辺から対向する他辺にかけて線路導体３が形成されたセラミックスから成る略四角形の平板部１および平板部１の上面に線路導体３の一部を間に挟んで接合されたセラミックスから成る立壁部２から構成されており、立壁部２の上面の略全面に上部接地導体層６が形成されているとともに平板部１の下面の略全面に下部接地導体層４が形成され、さらに線路導体３の線路方向に略平行な両側面に側部接地導体層５がそれぞれ形成されており、上部接地導体層６は、立壁部２の上面から立壁部２の線路導体３に略直交する両側面にかけて、線路導体３の直上に位置する部位に上下方向の幅が0.05〜0.1ｍｍの第一の延出部６ａ−１が形成され、その他の部位に上下方向の幅が0.05〜0.3ｍｍの第二の延出部６ａ−２が形成されている。
【００２１】
本発明の入出力端子Ｂは、図１、図２（ａ），（ｂ）に示すように、下部接地導体層４、側部接地導体層５、上部接地導体層６が枠体８の取付部８ａに嵌着されロウ付けされる。これにより、取付部８ａにおいて半導体パッケージＡの気密性が保持されるとともに、外部電気回路装置に対して半導体パッケージＡの内部に収容されている半導体素子Ｃからボンディングワイヤ（図示せず）を介して高周波信号を伝達する機能を有するものとなる。
【００２２】
また、入出力端子Ｂの平板部１および立壁部２は電気的な絶縁体としてのセラミックスから成り、例えばセラミック母基板を多数個に分割する多数個取りによる作製法によって作製され、平板部１および立壁部２はアルミナ（Ａｌ₂Ｏ₃）質焼結体（セラミックス）、窒化アルミニウム（ＡｌＮ）質焼結体、ムライト（３Ａｌ₂Ｏ₃・２ＳｉＯ₂）質焼結体等のセラミックスから成る。そして、立壁部２によって線路導体３が露出した一方側と他方側とに区分されている。
【００２３】
入出力端子Ｂが例えばＡｌ₂Ｏ₃セラミックスから成る場合、以下のようにして作製される。まずＡｌ₂Ｏ₃の粉末と、焼結助材としての酸化カルシウム（ＳｉＯ₂）、酸化カルシウム（ＣａＯ）、酸化マグネシウム（ＭｇＯ）などの粉末と、適当なバインダーおよび溶剤とを混合してこれをスラリーとなす。次に、このスラリーを用いて、従来周知のドクターブレード法などのテープ成形法によって所定厚さのセラミックグリーンシートに成形する。
【００２４】
次に、立壁部２のセラミック層となる厚さの異なる複数枚のセラミックグリーンシートと、同様に平板部１となるセラミックグリーンシートとを準備し、平板部１となるセラミックグリーンシートの上面に線路導体３となるパターンを、Ｗを主成分とする金属ペーストを周知のスクリーン印刷法で塗布形成するとともに、下面に下部接地導体層４となるパターンを同様にして形成する。
【００２５】
そして、同様に立壁部２となるセラミックグリーンシートに所定の穴あけ加工および貫通孔の側面への金属ペーストの被着を行い、次いで、これらのセラミックグリーンシートを積層することにより、上下方向の幅が0.05〜0.1ｍｍの第一の延出部６ａ−１と、その他の部位に上下方向の幅が0.05〜0.3ｍｍの第二の延出部６ａ−２とを立壁部となる積層部の側面に有するセラミックグリーンシート積層体が得られる。
【００２６】
このようにして得られたセラミックグリーンシート積層体を所定長さに切断し、次いで非酸化雰囲気下で1500〜1600℃の温度で焼成することによって入出力端子Ｂとなるセラミック焼結体を得る。次に、このセラミック焼結体の側面にＭｏ−Ｍｎ合金を主成分とする導体ペーストを周知のスクリーン印刷法により印刷して導体パターンを形成し、これを還元性雰囲気中で約1350℃の温度で焼成することにより、立壁部２の上面のＷから成る上部接地導体層６、延出部６ａ、Ｍｏ−Ｍｎ合金からなる側部接地導体層５、平板部１下面のＷから成る下部接地導体層４が形成された入出力端子を得る。
【００２７】
このようにして得られた入出力端子Ｂは、図２に示すように、半導体パッケージＡの枠体８に形成された貫通孔または切欠き部から成る取付部８ａに嵌着され、例えば半導体パッケージＡに収納される半導体素子Ｃに対する高周波電力の出力用として機能する。
【００２８】
本発明の入出力端子Ｂは、立壁部２の上面に形成された上部接地導体層６が、立壁部２の線路導体３に略直交する側面に延出した延出部６ａを有していることから、入出力端子Ｂを枠体８の取付部８ａにＡｇロウを介して嵌着接合させる際に、枠体８の変形に起因する応力が立壁部２の稜部２ａに集中したとしても、また半導体素子Ｃの熱により枠体８が変形し立壁部２の稜部２ａに応力が集中したとしても、稜部２ａが延出部６ａで覆われて補強されているため、立壁部２にクラックが発生することがなく、上部接地導体層６の剥れを解消できる。従って、本発明の入出力端子Ｂによれば、枠体８が変形して入出力端子Ｂの立壁部２に応力が集中したとしても、立壁部２の稜部２ａを起点とするクラックが発生することがなく、半導体パッケージＡの内部の気密性が損なわれることがなくなる。
【００２９】
本発明の入出力端子Ｂにおいて、上部接地導体層６は、立壁部２の上面から立壁部２の線路導体３に略直交する両側面にかけて、線路導体３の直上に位置する部位に上下方向の幅が0.05〜0.1ｍｍの第一の延出部６ａ−１が形成され、その他の部位に上下方向の幅が0.05〜0.3ｍｍの第二の延出部６ａ−２が形成されている。これにより、入出力端子Ｂを枠体２の取付部２ａに嵌着する際に立壁部２の稜部２ａにおけるクラックの発生を抑えることができ、半導体パッケージＡの気密性の劣化を防止することができる。
【００３０】
第二の延出部６ａ−２の幅が0.05ｍｍ未満では、クラックの発生を抑えることが困難となる。0.3ｍｍを超えると、Ａｇロウが第二の延出部６ａ−２の表面に大量に流れ出す場合があり、その結果、接合に寄与するＡｇロウが不足して枠体２の接合強度が劣化してしまう。
【００３１】
また、第一の延出部６ａ−１を形成することにより、線路導体３と第一の延出部６ａ−１との間で発生する浮遊容量を抑えることができる。この幅が0.05ｍｍ未満の場合、稜部２ａを起点として発生するクラックを防止することができず、また0.1ｍｍを超えると、浮遊容量が大きくなってしまい、共振点の低下が発生する。
【００３２】
また本発明の半導体パッケージＡは、上面に半導体素子Ｃを載置する載置部７ａが設けられた基体８と、基体８の上面の外周部に載置部７を囲繞するように接合され、側部に貫通孔または切欠きからなる入出力端子Ｂの取付部８ａが形成された枠体８と、取付部８ａに嵌着された入出力端子Ｂとを具備したことにより、気密性が良好であり、また共振点の低下が抑えられたものとなる。
【００３３】
そして、本発明の半導体パッケージＡは、入出力端子Ｂを枠体８の取付部８ａにＡｇロウなどのロウ材で嵌着して接合し、半導体素子Ｃを載置部７ａに載置して、半導体素子Ｃ上の電極と入出力端子Ｂの線路導体３とをボンディングワイヤを介して電気的に接続し、枠体８の上面にＦｅ−Ｎｉ−Ｃｏ合金等から成る蓋体（図示せず）を接合することにより、半導体装置となる。
【００３４】
かくして、本発明の入出力端子Ｂを有する半導体パッケージＡは、例えば高周波電力を出力する半導体素子Ｃを高い信頼性でもって収納することができるものとなる。
【００３５】
【実施例】
本発明の入出力端子および半導体パッケージの実施例を以下に説明する。
【００３６】
図２の入出力端子Ｂを以下のように構成した。すなわち、線路方向に直交する方向の長さが３ｍｍ、線路方向に平行な方向の長さが２ｍｍ、厚さが１ｍｍである平板部１上に、線路方向の長さが0.5ｍｍ、線路方向に直交する方向の長さが３ｍｍ、高さが1.5ｍｍの立壁部２を設けた入出力端子を用意した。このとき、第二の延出部６ａ−２の幅を0.025，0.05，0.075，0.15，0.25，0.275，0.3，0.325，0.35（ｍｍ）とした種々の入出力端子を各10個ずつの計90個、さらに延出部６ａがない従来の入出力端子10個と併せて合計100個を作製した。このとき、下部接地導体層４、側部接地導体層５、上部接地導体層６のそれぞれの厚さを15μｍにし、また延出部６ａの厚さを20μｍとした。
【００３７】
なお、第二の延出部６ａ−２を形成した90個のサンプルにおいて、第一の延出部６ａ−１の幅はすべて0.05ｍｍとした。
【００３８】
また、Ｃｕ−Ｗ合金からなる10ｍｍ角の基体７の上面に、半導体素子Ｃの載置部７ａを囲むように、厚さが0.5ｍｍ、高さが２ｍｍであり、側部に入出力端子Ｂを嵌着する取付部８ａが形成された枠体８をＡｇロウ（ＢＡｇ−８：ＪＩＳＺ３２６１）で接合したものを100個用意し、それらの表面にニッケルメッキ層および金メッキ層をいずれも２μｍの厚さで形成した。
【００３９】
そして、取付部８ａに、上記Ａｇロウを介して850℃の温度で入出力端子Ｂを嵌着接合して各種評価用サンプルを作製した。これらの評価用サンプルについて、加速寿命試験として半導体素子Ｃの作動時の温度よりも２倍以上高い温度（200℃）とする温度サイクル試験を1000サイクル行った。その後、これらの半導体パッケージＡについてクラック発生の有無を調査した。クラックの発生は浸透探傷用浸透液（「スーパーチェック」マークテック株式会社製）に漬浸した場合にこの液の浸透によりクラック部が赤く着色することによって判定した。表１にその結果を示す。
【００４０】
【表１】

【００４１】
表１より、第二の延出部６ａ−２の幅が0.05〜0.3ｍｍである本発明の入出力端子Ｂではクラックの発生が見られなかった。
【００４２】
次に、第二の延出部６ａ−２の幅が0.05，0.075，0.15，0.25，0.275，0.3，0.325（ｍｍ）のそれぞれの場合において第一の延出部６ａ−１の幅を0.05ｍｍとしたサンプルを各10個ずつ計70個作製し、また第二の延出部６ａ−２の幅が上記のそれぞれの場合において第一の延出部６ａ−１の幅を小さくしていないサンプルを各10個ずつ計70個作製し、これらについて浮遊容量の大きさを測定した。
【００４３】
このとき、浮遊容量および共振周波数の測定に際しては、半導体素子Ｃは１ＧＨｚの高周波信号を発信している状態とし、ネットワークアナライザーを用いて測定した。評価結果を表２に示す。
【００４４】
【表２】

【００４５】
表２より、第一の延出部６ａ−１の幅が0.05ｍｍで第二の延出部６ａ−２の幅が0.075〜0.3ｍｍである本発明の入出力端子Ｂを用いた半導体パッケージＡでは、浮遊容量を小さくすることができ、共振点の低下を小さくすることができることが判明した。
【００４６】
次に、第二の延出部６ａ−２の幅を0.2ｍｍとし、第一の延出部６ａ−１の幅を0.03，0.04，0.05，0.075，0.09，0.1，0.15，0.2（ｍｍ）とした種々のサンプルを各10個ずつ計80個作製し、上記と同様に浮遊容量および共振周波数を測定した結果を表３に示す。
【００４７】
【表３】

【００４８】
表３より、第一の延出部６ａ−１の幅が0.05〜0.1ｍｍのときに、クラックの発生がなく、かつ浮遊容量を小さくすることができ、共振点の低下を小さくすることができることが判明した。
【００４９】
なお、本発明は上記実施の形態および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上記実施の形態では、本発明の入出力端子Ｂを半導体パッケージＡに適用した場合について説明したが、混成集積回路基板の入出力端子として本発明の入出力端子Ｂを適用してもよい。
【００５０】
【発明の効果】
本発明の入出力端子は、上面に一辺から対向する他辺にかけて線路導体が形成されたセラミックスから成る略四角形の平板部および平板部の上面に線路導体の一部を間に挟んで接合されたセラミックスから成る立壁部から構成されており、立壁部の上面の略全面に上部接地導体層が形成されているとともに平板部の下面の略全面に下部接地導体層が形成され、さらに線路導体の線路方向に略平行な両側面に側部接地導体層がそれぞれ形成されており、上部接地導体層は、立壁部の上面から立壁部の線路導体に略直交する両側面にかけて、線路導体の直上に位置する部位に上下方向の幅が0.05〜0.1ｍｍの第一の延出部が形成され、その他の部位に上下方向の幅が0.05〜0.3ｍｍの第二の延出部が形成されていることにより、立壁部の線路導体に略直交する両側面上端の稜部付近が、上部接地導体層によって押え込まれた状態となってクラックの発生が抑えられ、上部接地導体層の外周部が延出部によって容易に剥れなくなるようにすることができる。また、上部接地導体層と線路導体との間に発生する浮遊容量を小さくすることができる。
【００５１】
本発明の半導体素子収納用パッケージは、上面に半導体素子を載置する載置部が設けられた基体と、基体の上面に載置部を囲繞するように接合され、側部に貫通孔または切欠きからなる入出力端子の取付部が形成された枠体と、取付部に嵌着された上記本発明の入出力端子とを具備したことにより、入出力端子を枠体の取付部にロウ材を介して嵌着させる際に立壁部に発生するクラックに起因して上部接地導体層が剥れるのを防止することができるとともに、上部接地導体層と線路導体との間に発生する浮遊容量を小さくすることができ、これにより、半導体素子収納用パッケージ内において、上部接地導体層と線路導体との間で発生する新たな浮遊容量により高周波信号の共振点が低下することを防止することができる。
【図面の簡単な説明】
【図１】本発明の入出力端子が設けられた半導体素子収納用パッケージについて実施の形態の一例を示し、入出力端子部の部分拡大断面図である。
【図２】本発明の入出力端子について実施の形態の一例を示し、（ａ）は入出力端子の正面図、（ｂ）は入出力端子の斜視図である。
【図３】従来の入出力端子を枠体の側部に有する半導体素子収納用パッケージの斜視図である。
【図４】従来の入出力端子の斜視図である。
【符号の説明】
１：平板部
２：立壁部
２ａ：稜部
２ｂ：側面
３：線路導体
４：下部接地導体層
５：側部接地導体層
６：上部接地導体層
６ａ：延出部
６ａ−１：第一の延出部
６ａ−２：第二の延出部
７：基体
７ａ：載置部
８：枠体
８ａ：取付部
Ａ：半導体素子収納用パッケージ
Ｂ：入出力端子
Ｃ：半導体素子[0001]
[Technical field to which the invention pertains]
The present invention relates to an input/output terminal used in a package for housing a semiconductor element for housing a semiconductor element such as an IC or an LSI, and to a package for housing a semiconductor element.
[0002]
2. Description of the Related Art
With the recent development of communication devices used in wireless communication, the demand for semiconductor elements such as ICs and LSIs that operate at high power in the high frequency band has increased significantly. In particular, in information devices used in mobile phone base stations, high-power semiconductor elements that operate with high efficiency to obtain high power output with limited power and perform long-term signal conversion, and packages for housing these semiconductor elements (hereinafter also referred to as semiconductor packages) are becoming important. That is, there is a demand for semiconductor elements that have small power loss inside the semiconductor elements and efficiently convert applied DC power into high frequency power, and for semiconductor packages that can house these semiconductor elements and maximize their performance.
[0003]
For this reason, the development of MESFETs (Metal Semiconductor Field Effect Transistors) using gallium arsenide (GaAs) compound semiconductors has been promoted, but there are problems in that the characteristics and conversion efficiency at low voltages are poor and large currents cannot be passed. However, in recent years, semiconductor elements such as GaAs compound semiconductor HBTs (Heterojunction Bipolar Transistors) have been attracting attention as semiconductor elements that have superior characteristics at low voltages compared to MESFETs and can efficiently convert large DC power into high frequency power. In addition, since such semiconductor elements generate a large amount of heat during operation, a semiconductor package with good heat dissipation properties is strongly desired.
[0004]
A semiconductor package that houses such a semiconductor element is shown in the perspective view of Fig. 3. Fig. 3 shows a semiconductor package A using an input/output terminal B, which, as shown in the perspective view of Fig. 4, has a convex vertical cross-sectional shape produced by a ceramic green sheet lamination method, and is composed of a flat plate portion 1 made of ceramics and a vertical wall portion 2 made of ceramics attached to the upper surface of the flat plate portion 1 with a part (center portion) of a line conductor 3 sandwiched therebetween. As shown in Fig. 3, the input/output terminal B is fitted into a mounting portion 8a of a frame body 8 that is joined to the outer periphery of the upper surface of a base body 7 so as to surround a mounting portion 7a, and functions, for example, to output high-frequency power to a semiconductor element C housed in the semiconductor package A.
[0005]
Since the base 7 is required to have high heat dissipation properties, it is often made of copper (Cu)-tungsten (W) or Cu, and the frame 8 is often made of an iron (Fe)-nickel (Ni)-cobalt (Co) alloy, which has a thermal expansion coefficient close to that of the input/output terminals B. When a large amount of heat needs to be dissipated to the outside, a Cu-W alloy is preferred, which has a thermal expansion coefficient close to that of the Fe-Ni-Co alloy at 200 to 300°C. This is because it is possible to design the material so that the thermal expansion coefficient in this temperature range is in the range of about 5 x ^10-6 to 8 x ^10-6 /°C, and therefore the thermal expansion coefficients of these alloys can be made similar, which prevents the base 7 from warping significantly.
[0006]
In addition, a lower ground conductor layer 4 is formed on almost the entire lower surface of the flat plate portion 1 of the input/output terminal B, side ground conductor layers 5 are formed on both side surfaces of the flat plate portion 1 and the vertical wall portion 2 which are approximately parallel to the line direction, and an upper ground conductor layer 6 is formed on almost the entire upper surface of the vertical wall portion 2, and these lower ground conductor layer 4, side ground conductor layer 5 and upper ground conductor layer 6 are arranged so as to surround the line conductor 3, thereby forming a waveguide structure.
[0007]
The width of the standing wall 2 in the direction substantially perpendicular to the line direction is substantially the same as the width of the frame 8, so that when the input/output terminal B is fitted to the mounting portion 8a of the frame 8 via silver (Ag) solder, for example, a large meniscus is not generated between the side surface 2b of the standing wall 2 substantially perpendicular to the line direction and the inner surface of the mounting portion 9a. This makes it possible to reduce the stress with which the Ag solder tensiles the surface of the standing wall 2 when the temperature of the semiconductor package A rises, and prevents stress from concentrating on the ridge portion 2a between the upper surface of the standing wall 2 and the side surface 2b substantially perpendicular to the line direction.
[0008]
The reason why the width of the vertical wall 2 is made approximately the same as the thickness of the frame 8 as described above is to substantially satisfy two conflicting conditions: the narrower the width of the vertical wall 2 is, in order to reduce the insertion loss of high frequency signals, while the wider the thickness of the frame 8 is, in order to obtain reliable bonding. Currently, the widths of the two are generally made approximately the same, and are often set between 0.25 and 1.0 mm.
[0009]
[Problem to be solved by the invention]
However, in the semiconductor package A using the conventional input/output terminals B as shown in Fig. 4, when the input/output terminals B are joined to the mounting portion 8a using Ag solder, it is necessary to heat the terminals to a temperature of, for example, about 850°C, and at this time, the molten Ag solder solidifies in a state in which the frame body 8 made of an Fe-Ni-Co alloy spreads outward compared to the base body 7 made of Cu-W, and as the temperature drops and the frame body 8 tries to return to its original state, microcracks are generated starting from the ridges 2a facing outward of the frame body 8 on the upper surface of the vertical wall portion 2. At this time, a force acts on the upper ground conductor layer 6 to peel it off, resulting in a problem in which the airtightness of the semiconductor package is impaired.
[0010]
This is because the Fe-Ni-Co alloy has an inflection point of the thermal expansion coefficient at about 420°C, and has a thermal expansion coefficient of about 5.5× ^10-6 /°C from room temperature to this temperature, but has a thermal expansion coefficient of about 11.3× ^10-6 /°C above this temperature. That is, since it expands at a thermal expansion coefficient greater than that of the Cu-W alloy at 850°C, the Ag braze solidifies at the eutectic point slightly lower than this temperature, and at this time the input/output terminals B are fixed in a state in which the upper part of the frame 8 is expanded, and then as the temperature decreases, the frame 8 tries to return to its original state. The stress generated at this time is concentrated on the edge of the upper ground conductor layer 6, especially on the ridge 2a of the vertical wall 2 facing the outside of the frame 8, and small cracks are generated at the ridge 2a. Starting from this crack, a force acts on the upper ground conductor layer 6 to peel it off together with the surface of the input/output terminal B, causing the crack to grow, and eventually it may connect to a crack that occurs in the opposing ridge 2a on the upper surface of the vertical wall portion 2, thereby compromising the airtightness of the semiconductor package A.
[0011]
Therefore, in order to prevent a large stress from concentrating on the ridge portion 2a, the thickness of the frame body 8a is locally thinned only in the vicinity of the mounting portion 8a of the input/output terminal B, and the thickness of the vertical wall portion 2 in the line direction is correspondingly thinned. However, in this case, the bonding strength of the joint of the vertical wall portion 2 is reduced, and cracks may occur in the Ag solder even with a small force, which may impair the airtightness of the semiconductor package A.
[0012]
It is also conceivable to increase the thickness of the vertical wall portion 2 in the direction parallel to the line direction while leaving the length of the input/output terminal B in the direction parallel to the line direction unchanged, thereby moving the ridge portion 2a away from the frame body 8 and alleviating the stress concentration on the ridge portion 2a, but in this case the wire bonding area of the line conductor 3 on the upper surface of the flat plate portion 1 and the bonding area of the lead terminal (not shown) would become narrower, and in order to avoid this, it would be necessary to increase the size of the input/output terminal B. As a result, a problem occurred in which the overall size of the semiconductor package A became larger.
[0013]
Therefore, the present invention has been completed in consideration of the above-mentioned problems, and its object is to provide an input/output terminal and a semiconductor package that prevent cracks from occurring starting from the ridges on the upper surface of the vertical wall portion of the input/output terminal, and in which cracks do not easily grow even when a force is applied to peel off the upper ground conductor layer on the upper surface of the vertical wall portion.
[0014]
[Means for solving the problem]
The input/output terminal of the present invention is composed of a substantially rectangular flat plate portion made of ceramics having a line conductor formed on its upper surface from one side to the opposing other side, and a vertical wall portion made of ceramics joined to the upper surface of the flat plate portion with a part of the line conductor sandwiched therebetween, wherein an upper ground conductor layer is formed on substantially the entire surface of the upper surface of the vertical wall portion and a lower ground conductor layer is formed on substantially the entire surface of the lower surface of the flat plate portion, and further, side ground conductor layers are formed on both side surfaces of the line conductor substantially parallel to the line direction, wherein the upper ground conductor layer has a first extension portion having a vertical width of 0.05 to 0.1 mm formed from the upper surface of the vertical wall portion to both side surfaces of the vertical wall portion substantially perpendicular to the line conductor at a portion located directly above the line conductor, and a second extension portion having a vertical width of 0.05 to 0.3 mm formed in other portions.
[0015]
In the input/output terminal of the present invention, a first extending portion having a vertical width of 0.05 to 0.1 mm is formed at a portion located directly above the line conductor from the upper surface of the vertical wall portion to both side surfaces substantially perpendicular to the line conductor, and a second extending portion having a vertical width of 0.05 to 0.3 mm is formed at other portions, so that the ridges near the upper ends of both side surfaces substantially perpendicular to the upper surface of the flat portion of the vertical wall portion are pressed down by the upper ground conductor layer, suppressing the occurrence of cracks and making it possible for the outer periphery of the upper ground conductor layer to be prevented from peeling off easily by the extending portions. Also, at this time, the stray capacitance generated between the upper ground conductor layer and the line conductor can be reduced.
[0016]
The package for storing a semiconductor element of the present invention is characterized by comprising a base having a mounting portion on its upper surface for mounting a semiconductor element thereon, a frame body joined to the upper surface of the base so as to surround the mounting portion and having an attachment portion for an input/output terminal formed on its side in the form of a through hole or a notch, and the input/output terminal of the present invention fitted into the attachment portion.
[0017]
The semiconductor element storage package of the present invention, with its above-mentioned configuration, can prevent peeling of the upper ground conductor layer due to cracks that occur in the vertical wall portion when the input/output terminals are fitted to the mounting portion of the frame body via solder material, and can prevent a decrease in the resonance point of high-frequency signals within the semiconductor element storage package by minimizing the new stray capacitance that occurs between the upper ground conductor layer and the line conductor.
[0018]
[0023]
The input/output terminal and the package for housing a semiconductor element of the present invention will be described in detail below. Fig. 1 is a partially enlarged cross-sectional view showing an embodiment of a semiconductor package using the input/output terminal of the present invention, and Fig. 2(a) shows a front view of the input/output terminal of the present invention, and Fig. 2(b) shows a perspective view of the input/output terminal. In Figs. 1 and 2, the same reference numerals are used to designate the same parts as in Figs. 3 and 4 showing the conventional example.
[0019]
1 and 2, 1 denotes a flat plate portion, 2 denotes a standing wall portion joined onto the flat plate portion 1, 2a denotes a ridge portion at the upper end of a side surface of the standing wall portion 2 substantially perpendicular to the

line conductor

3, 2b denotes a side surface of the standing wall portion 2 substantially perpendicular to the line conductor 3, 2c denotes an uppermost insulating layer (ceramic layer) constituting the

standing wall portion

2, 2d denotes a second insulating layer from the top constituting the standing

wall portion

2, and 3 denotes a line conductor formed on the upper surface of the flat plate portion 1. In addition, 4 denotes a lower ground conductor layer formed on substantially the entire lower surface of the flat plate portion 1, 5 denotes side ground conductor layers formed on both side surfaces of the flat plate portion 1 and the standing wall portion 2 substantially parallel to the line direction, 6 denotes an upper ground conductor layer formed on substantially the entire upper surface of the standing

wall portion

2, 6a denotes an extension of the upper ground conductor layer 6, 6a-1 denotes a first extension, 6a-2 denotes a second extension, 7 denotes a base, 7a denotes a mounting portion for a semiconductor element C, 8 denotes a frame, and 8a denotes an attachment portion.
[0020]
The input/output terminal B of the present invention is composed of a substantially rectangular flat plate portion 1 made of ceramics having a line conductor 3 formed on its upper surface from one side to the opposing other side, and a vertical wall portion 2 made of ceramics joined to the upper surface of the flat plate portion 1 with a part of the line conductor 3 sandwiched therebetween, with an upper ground conductor layer 6 formed on substantially the entire upper surface of the vertical wall portion 2 and a lower ground conductor layer 4 formed on substantially the entire lower surface of the flat plate portion 1, and further with side ground conductor layers 5 formed on both side surfaces of the line conductor 3 substantially parallel to the line direction, and the upper ground conductor layer 6 is formed from the upper surface of the vertical wall portion 2 to both side surfaces of the vertical wall portion 2 substantially perpendicular to the line conductor 3, with a first extension portion 6a-1 having a vertical width of 0.05 to 0.1 mm at a portion located directly above the line conductor 3 and a second extension portion 6a-2 having a vertical width of 0.05 to 0.3 mm at other portions.
[0021]
1, 2(a) and 2(b), the input/output terminal B of the present invention is configured such that the lower ground conductor layer 4, the side ground conductor layer 5 and the upper ground conductor layer 6 are fitted and brazed to the mounting portion 8a of the frame body 8. This maintains the airtightness of the semiconductor package A at the mounting portion 8a, and also provides the function of transmitting high frequency signals from the semiconductor element C accommodated inside the semiconductor package A to an external electric circuit device via bonding wires (not shown).
[0022]
The flat plate 1 and the vertical wall 2 of the input/output terminal B are made of ceramics as an electrical insulator, and are fabricated, for example, by a multi _- piece fabrication method in which a ceramic mother board is divided into many pieces, and the flat plate 1 and the vertical wall 2 are made of ceramics such as alumina ( _Al2O3 ) sintered body (ceramics), _aluminum nitride ( _AlN ) sintered body, mullite ( _3Al2O3.2SiO2 ) sintered body, etc. The vertical wall 2 divides the terminal B into one side where the line conductor 3 is exposed and the other side.
[0023]
For example, when the input/output terminal B is made of _Al2O3 _ceramics , it is manufactured as follows. _First , _Al2O3 powder, powders of calcium oxide ( _SiO2 ), calcium oxide (CaO), magnesium oxide (MgO) or the like as sintering aids, a suitable binder and a solvent are mixed to form a slurry. Next, this slurry is formed into a ceramic green sheet of a predetermined thickness by a tape casting method such as the well-known doctor blade method.
[0024]
Next, multiple ceramic green sheets of different thicknesses that will become the ceramic layers of the vertical wall portion 2, and a ceramic green sheet that will similarly become the flat portion 1 are prepared, and a pattern that will become the line conductor 3 is formed on the upper surface of the ceramic green sheet that will become the flat portion 1 by applying a metal paste containing W as its main component using a well-known screen printing method, and a pattern that will become the lower ground conductor layer 4 is similarly formed on the lower surface.
[0025]
Similarly, the ceramic green sheets that will become the vertical wall portion 2 are subjected to the prescribed hole drilling process and metal paste is applied to the side surfaces of the through holes. These ceramic green sheets are then stacked to obtain a ceramic green sheet laminate having a first extension portion 6a-1 having a vertical width of 0.05 to 0.1 mm and a second extension portion 6a-2 having a vertical width of 0.05 to 0.3 mm in the other location on the side surfaces of the laminate portion that will become the vertical wall portion.
[0026]
The ceramic green sheet laminate thus obtained is cut to a predetermined length and then fired in a non-oxidizing atmosphere at a temperature of 1500 to 1600°C to obtain a ceramic sintered compact which becomes the input/output terminal B. Next, a conductor paste mainly composed of a Mo-Mn alloy is printed on the side surfaces of this ceramic sintered compact by a well-known screen printing method to form a conductor pattern, which is then fired in a reducing atmosphere at a temperature of about 1350°C to obtain an input/output terminal having an upper ground conductor layer 6 made of W on the upper surface of the standing wall portion 2, an extension portion 6a, a side ground conductor layer 5 made of a Mo-Mn alloy, and a lower ground conductor layer 4 made of W on the underside of the flat plate portion 1.
[0027]
The input/output terminal B thus obtained is fitted into a mounting portion 8a consisting of a through hole or a notch formed in a frame body 8 of the semiconductor package A, as shown in FIG. 2, and functions, for example, for outputting high-frequency power to a semiconductor element C housed in the semiconductor package A.
[0028]
In the input/output terminal B of the present invention, the upper ground conductor layer 6 formed on the upper surface of the vertical wall portion 2 has an extension portion 6a extending to a side surface substantially perpendicular to the line conductor 3 of the vertical wall portion 2, so that even if stress caused by deformation of the frame body 8 is concentrated on the ridge portion 2a of the vertical wall portion 2 when the input/output terminal B is fitted and joined to the mounting portion 8a of the frame body 8 via Ag solder, or even if the frame body 8 is deformed by the heat of the semiconductor element C and stress is concentrated on the ridge portion 2a of the vertical wall portion 2, cracks will not occur in the vertical wall portion 2 because the ridge portion 2a is covered and reinforced by the extension portion 6a, and peeling of the upper ground conductor layer 6 can be eliminated. Therefore, according to the input/output terminal B of the present invention, even if the frame body 8 is deformed and stress is concentrated on the vertical wall portion 2 of the input/output terminal B, cracks will not occur originating from the ridge portion 2a of the vertical wall portion 2, and the airtightness inside the semiconductor package A will not be impaired.
[0029]
In the input/output terminal B of the present invention, the upper ground conductor layer 6 is formed with a first extending portion 6a-1 having a vertical width of 0.05 to 0.1 mm at a portion located directly above the line conductor 3 from the upper surface of the standing wall portion 2 to both side surfaces of the standing wall portion 2 substantially perpendicular to the line conductor 3, and with a second extending portion 6a-2 having a vertical width of 0.05 to 0.3 mm at other portions. This makes it possible to suppress the occurrence of cracks at the ridge portion 2a of the standing wall portion 2 when the input/output terminal B is fitted into the mounting portion 2a of the frame body 2, and prevents deterioration of the airtightness of the semiconductor package A.
[0030]
If the width of the second extension 6a-2 is less than 0.05 mm, it is difficult to prevent cracks from occurring. If the width exceeds 0.3 mm, a large amount of Ag solder may flow out onto the surface of the second extension 6a-2, resulting in a shortage of Ag solder contributing to bonding and a deterioration in the bonding strength of the frame 2.
[0031]
Furthermore, by forming the first extending portion 6a-1, it is possible to suppress the stray capacitance occurring between the line conductor 3 and the first extending portion 6a-1. If the width is less than 0.05 mm, it is not possible to prevent cracks from occurring starting from the ridge portion 2a, and if it exceeds 0.1 mm, the stray capacitance becomes large, causing a decrease in the resonance point.
[0032]
In addition, the semiconductor package A of the present invention comprises a base 8 having a mounting portion 7a on its upper surface for mounting a semiconductor element C thereon, a frame body 8 which is joined to the outer periphery of the upper surface of the base 8 so as to surround the mounting portion 7 and has mounting portions 8a for input/output terminals B formed on the sides thereof, each of which comprises a through hole or a notch, and the input/output terminals B fitted into the mounting portions 8a, thereby achieving good airtightness and suppressing a decrease in the resonance point.
[0033]
The semiconductor package A of the present invention becomes a semiconductor device by fitting and joining the input/output terminals B to the mounting portions 8a of the frame body 8 with a solder material such as Ag solder, placing the semiconductor element C on the mounting portion 7a, electrically connecting the electrodes on the semiconductor element C to the line conductors 3 of the input/output terminals B via bonding wires, and joining a lid body (not shown) made of an Fe-Ni-Co alloy or the like to the upper surface of the frame body 8.
[0034]
Thus, the semiconductor package A having the input/output terminals B of the present invention can house, with high reliability, a semiconductor element C that outputs, for example, high frequency power.
[0035]
EXAMPLES
An embodiment of the input/output terminal and the semiconductor package of the present invention will be described below.
[0036]
The input/output terminal B in Fig. 2 was constructed as follows. That is, an input/output terminal was prepared in which a vertical wall portion 2 having a length of 0.5 mm in the line direction, a length of 3 mm in the direction perpendicular to the line direction, and a height of 1.5 mm was provided on a flat plate portion 1 having a length of 3 mm in the direction perpendicular to the line direction, a length of 2 mm in the direction parallel to the line direction, and a thickness of 1 mm. At this time, various input/output terminals having widths of the second extension portion 6a-2 of 0.025, 0.05, 0.075, 0.15, 0.25, 0.275, 0.3, 0.325, and 0.35 (mm) were fabricated, totaling 90 pieces, including 10 pieces of each type of input/output terminal, and 10 conventional input/output terminals without the extension portion 6a. At this time, the thicknesses of the lower ground conductor layer 4, the side ground conductor layer 5, and the upper ground conductor layer 6 were each set to 15 μm, and the thickness of the extension portion 6a was set to 20 μm.
[0037]
In the 90 samples in which the second extending portion 6a-2 was formed, the width of the first extending portion 6a-1 was set to 0.05 mm.
[0038]
In addition, 100 pieces of frames 8 each having a thickness of 0.5 mm and a height of 2 mm and each having a mounting portion 8a for fitting an input/output terminal B on one side were prepared by bonding the frames 8 with Ag solder (BAg-8: JIS Z 3261) to the top surface of a 10 mm square base 7 made of a Cu-W alloy so as to surround the mounting portion 7a for the semiconductor element C. Nickel plating and gold plating layers each having a thickness of 2 μm were formed on the surfaces of these frames.
[0039]
Then, input/output terminals B were fitted and joined to mounting portion 8a via the Ag solder at a temperature of 850°C to prepare various evaluation samples. These evaluation samples were subjected to a temperature cycle test of 1000 cycles at a temperature (200°C) that was more than twice as high as the operating temperature of semiconductor element C as an accelerated life test. After that, the semiconductor packages A were examined for the occurrence of cracks. The occurrence of cracks was judged by the fact that the cracks were colored red by the penetration of a penetrant for penetrant inspection ("Super Check" manufactured by Marktec Co., Ltd.) when the samples were immersed in the penetrant for penetrant inspection. The results are shown in Table 1.
[0040]
Table 1

[0041]
From Table 1, no cracks were observed in the input/output terminal B of the present invention in which the width of the second extending portion 6a-2 is 0.05 to 0.3 mm.
[0042]
Next, 70 samples in total were fabricated in which the width of the first extension portion 6a-1 was 0.05 mm for each of the cases in which the width of the second extension portion 6a-2 was 0.05, 0.075, 0.15, 0.25, 0.275, 0.3, and 0.325 (mm). In addition, 70 samples in total were fabricated in which the width of the first extension portion 6a-1 was not reduced for each of the above cases in which the width of the second extension portion 6a-2 was 0.05, 0.075, 0.15, 0.25, 0.275, 0.3, and 0.325 (mm). The magnitude of stray capacitance of these samples was measured.
[0043]
At this time, the floating capacitance and the resonant frequency were measured using a network analyzer while the semiconductor element C was transmitting a high frequency signal of 1 GHz. The evaluation results are shown in Table 2.
[0044]
Table 2

[0045]
From Table 2, it was found that in the semiconductor package A using the input/output terminal B of the present invention in which the width of the first extension portion 6a-1 is 0.05 mm and the width of the second extension portion 6a-2 is 0.075 to 0.3 mm, the stray capacitance can be reduced and the decrease in the resonance point can be minimized.
[0046]
Next, various samples were fabricated, each with 10 samples of each type, in which the width of the second extension portion 6a-2 was 0.2 mm and the width of the first extension portion 6a-1 was 0.03, 0.04, 0.05, 0.075, 0.09, 0.1, 0.15, and 0.2 mm, for a total of 80 samples. The stray capacitance and resonant frequency were measured in the same manner as above, and the results are shown in Table 3.
[0047]
Table 3

[0048]
It is clear from Table 3 that when the width of the first extension portion 6a-1 is 0.05 to 0.1 mm, no cracks are generated, the stray capacitance can be reduced, and the decrease in the resonance point can be reduced.
[0049]
The present invention is not limited to the above-described embodiment and examples, and various modifications are possible without departing from the scope of the present invention. For example, in the above-described embodiment, the input/output terminal B of the present invention is applied to the semiconductor package A, but the input/output terminal B of the present invention may be applied as an input/output terminal of a hybrid integrated circuit board.
[0050]
Effect of the Invention
The input/output terminal of the present invention is composed of a substantially rectangular flat plate portion made of ceramics having a line conductor formed on its upper surface from one side to the opposing other side, and a vertical wall portion made of ceramics joined to the upper surface of the flat plate portion with a part of the line conductor sandwiched between them, an upper ground conductor layer is formed on substantially the entire surface of the upper surface of the vertical wall portion and a lower ground conductor layer is formed on substantially the entire surface of the lower surface of the flat plate portion, and further, side ground conductor layers are formed on both side surfaces of the line conductor that are substantially parallel to the line direction, and the upper ground conductor layer has a first extension portion having a vertical width of 0.05 to 0.1 mm formed from the upper surface of the vertical wall portion to both side surfaces of the vertical wall portion substantially perpendicular to the line conductor, at a portion located directly above the line conductor, and a second extension portion having a vertical width of 0.05 to 0.3 mm formed in other portions, so that the vicinity of the ridge portions at the upper ends of both side surfaces of the vertical wall portion substantially perpendicular to the line conductor are pressed down by the upper ground conductor layer, thereby suppressing the occurrence of cracks and making it possible to prevent the outer periphery of the upper ground conductor layer from easily peeling off due to the extension portions. In addition, the stray capacitance occurring between the upper ground conductor layer and the line conductor can be reduced.
[0051]
The package for storing semiconductor elements of the present invention comprises a base having a mounting portion on its upper surface for mounting a semiconductor element thereon, a frame body joined to the upper surface of the base so as to surround the mounting portion and having mounting portions for input/output terminals consisting of through holes or notches formed on the sides, and the input/output terminals of the present invention fitted into the mounting portions.By doing so, it is possible to prevent peeling of the upper ground conductor layer due to cracks that occur in the vertical wall portion when the input/output terminals are fitted into the mounting portions of the frame body via solder, and it is possible to reduce the stray capacitance generated between the upper ground conductor layer and the line conductor, thereby preventing a lowering of the resonance point of high-frequency signals due to new stray capacitance generated between the upper ground conductor layer and the line conductor within the package for storing semiconductor elements.
[Brief description of the drawings]
FIG. 1 is a partially enlarged cross-sectional view of an input/output terminal portion, showing an example of an embodiment of a semiconductor element housing package provided with input/output terminals according to the present invention.
2A and 2B show an example of an input/output terminal according to an embodiment of the present invention, in which FIG. 2A is a front view of the input/output terminal, and FIG. 2B is a perspective view of the input/output terminal.
FIG. 3 is a perspective view of a conventional package for housing a semiconductor element having input/output terminals on the side of a frame body.
FIG. 4 is a perspective view of a conventional input/output terminal.
[Explanation of symbols]
1: Flat plate portion 2: Standing wall portion 2a: Ridge portion 2b: Side surface 3: Line conductor 4: Lower ground conductor layer 5: Side ground conductor layer 6: Upper ground conductor layer 6a: Extension portion 6a-1: First extension portion 6a-2: Second extension portion 7: Base body 7a: Mounting portion 8: Frame body 8a: Mounting portion A: Package for housing semiconductor element B: Input/output terminal C: Semiconductor element

Claims

an input/output terminal comprising: a substantially rectangular flat plate portion made of ceramics having a line conductor formed on its upper surface from one side to the opposing other side; and a vertical wall portion made of ceramics joined to the upper surface of the flat plate portion with a part of the line conductor sandwiched therebetween, wherein an upper ground conductor layer is formed over substantially the entire surface of the upper surface of the vertical wall portion and a lower ground conductor layer is formed over substantially the entire surface of the lower surface of the flat plate portion, and further wherein side ground conductor layers are formed on both side surfaces of the line conductor substantially parallel to the line direction, the upper ground conductor layer having a first extension portion having a vertical width of 0.05 to 0.1 mm formed from the upper surface of the vertical wall portion to both side surfaces of the vertical wall portion substantially perpendicular to the line conductor, at a portion located directly above the line conductor, and a second extension portion having a vertical width of 0.05 to 0.3 mm formed in other portions.

13. A package for storing semiconductor elements, comprising: a base having a mounting portion on its upper surface for mounting a semiconductor element thereon; a frame body joined to the upper surface of the base so as to surround the mounting portion and having an input/output terminal mounting portion formed on the side thereof, the mounting portion being a through hole or a notch; and the input/output terminal according to claim 1 fitted into the mounting portion.