JP3830871B2 - Electrostatic discharge protection element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrostatic discharge protection element that protects an internal circuit from a surge.
[0002]
[Prior art]
An electrostatic discharge (ESD) protective element is an element that protects an internal circuit from abnormal current or voltage, a so-called surge, and is used by being connected to an input part or an output part of an LSI chip or LSI circuit. .
[0003]
Here, a conventional ESD protection element will be described by taking a MOSFET type as an example and referring to a schematic structural diagram of FIG.
[0004]
On the p-type semiconductor substrate 1601, the first to third n⁺ Diffusion layers 1602a to 1602c are provided. The first diffusion layer 1602a forms a source region, and the second and third diffusion layers 1602b and 1602c form drain regions. Silicide layers 1603a to 1603c for reducing resistance are formed on the surfaces of the first to third diffusion layers 1602a to 1602c. A silicide block region 1604 where no silicide is formed is provided between the second diffusion layer 1602b and the third diffusion layer 1602c. A gate electrode 1605 is provided between the first diffusion layer 1602a and the second diffusion layer 1602b. Sidewall insulating films 1606 are formed on both sides of the gate electrode 1605, and a gate insulating film 1607 is formed below the gate electrode 1605. In the vicinity of the surface of the semiconductor substrate 1601, for example, the impurity region of the silicide block region 1604 is an extension region 1608, and its end portions 1608a and 1608b extend from the first diffusion layer 1602a to the lower portion of the gate insulating film 1607, and the second diffusion layer 1602b. To the lower part of the gate insulating film 1607.
[0005]
In the extension region 1608, the junction depth of impurities is shallower than that of first to third diffusion layers 1602a to 1602c, which are called high-concentration diffusion layers, and the maximum impurity concentration is also low.
[0006]
The silicide layer 1603a and the gate electrode 1605 are grounded through the source wiring S and the gate wiring G, respectively, and the semiconductor substrate 1601 is also grounded. The silicide layer 1603c is connected to the drain wiring D, and the drain wiring D is connected to, for example, an input signal line 1611 that connects the input pad 1609 to which a signal is input and the internal circuit 1610.
[0007]
In the above-described configuration, for example, when a surge occurs in the signal line 1611, the parasitic bipolar transistor formed inside the ESD protection element is turned on, triggered by collision ionization generated between the drain diffusion layer and the semiconductor substrate 1601. The ESD protection element becomes conductive. At this time, a current path through which a current flows is formed in the surface portion of the semiconductor substrate 1601, for example, the silicide block region 1604 and the channel region below the gate electrode 1605, the signal line 1611 is grounded, and the internal circuit 1610 is protected from the surge.
[0008]
In the ESD protection element, when a surge occurs in the signal line 1611, the lattice temperature of the semiconductor substrate 1601 may increase due to a high electric field generated between the drain diffusion layer and the semiconductor substrate 1601, and may be thermally destroyed.
[0009]
However, in the conventional ESD protection element, thermal breakdown is suppressed by the silicide block region 1604. Since the silicide block region 1604 is not formed with low-resistance silicide, the resistance is higher than that of the drain diffusion layer in which the silicide layer is formed, the high electric field generated between the drain diffusion layer and the semiconductor substrate is relaxed, and thermal breakdown is prevented. Is prevented.
[0010]
[Problems to be solved by the invention]
In the case of a conventional ESD protection element, for example, a MOSFET type, a silicide block region is provided in a part of the drain diffusion layer to suppress a temperature rise when a surge occurs and prevent thermal destruction.
[0011]
This method may not sufficiently prevent thermal destruction when the surge increases. Therefore, there is a method of lengthening the silicide block region to alleviate electric field concentration and prevent thermal destruction. However, if the silicide block region becomes longer, the resistance of the ESD protection element increases, loss due to current increases, and the lattice temperature may increase as a whole. Further, when the silicide block region is lengthened, there is a problem that the chip area increases. On the other hand, if the length of the silicide block region is short, the electric field concentrates on the silicide block region, which easily causes thermal destruction.
[0012]
In order to avoid such electric field concentration on the silicide block region, there is a method of providing the silicide block region 1604 in the high-concentration diffusion layer 1701 having a low resistance as shown in FIG. This method has a problem that since the resistance value of the high concentration diffusion layer is low, the silicide block region 1604 becomes long to sufficiently relax the electric field. In FIG. 17, the same reference numerals are given to the portions corresponding to FIG.
[0013]
An object of the present invention is to provide an electrostatic discharge protection element that solves the above-described drawbacks and has improved resistance to thermal destruction of the ESD protection element.
[0014]
[Means for Solving the Problems]
  The present inventionElectrostatic discharge protection elementA semiconductor substrate;
    A drain diffusion layer forming a drain region in which a first silicide layer and a second silicide layer are formed apart from the surface of the semiconductor substrate;
  A source diffusion layer forming a source region in which a third silicide layer is formed;
A gate electrode located on the semiconductor substrate between the drain diffusion layer and the source diffusion layer via an insulating film;
  Thermal conductivity that changes from a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate, formed in at least part of the first silicide layer and the second silicide layer. Transition region, and
  The drain diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the source diffusion layer and the gate electrode are groundedAnd
The transition region of the thermal conductivity is characterized in that the thermal conductivity continuously increases from the surface of the semiconductor substrate to the semiconductor substrate side below and toward a deeper direction.The
  The electrostatic discharge protection element of the present invention includes a semiconductor substrate,
A first conductivity type well formed on the surface of the semiconductor substrate;
First and second diffusion layers having the same conductivity type as the first conductivity type formed in the first conductivity type well at intervals,
A material having a low thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate formed in at least a part of the first conductivity type well sandwiched between the first and second diffusion layers. A transition region of thermal conductivity that changes to a high material,
The first diffusion layer is connected to an input pad provided on the semiconductor substrate, and the second diffusion layer is connected to an internal circuit provided on the semiconductor substrate;
The transition region of the thermal conductivity is characterized in that the thermal conductivity increases continuously from the surface of the semiconductor substrate toward the semiconductor substrate side in the deep direction..
  The electrostatic discharge protection element of the present invention includes a semiconductor substrate,
A first conductivity type well formed on the surface of the semiconductor substrate;
A first diffusion layer of the same conductivity type as the first conductivity type formed in the first conductivity type well with an interval, and a second diffusion layer of a second conductivity type different from the first conductivity type;
From a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate, formed in at least a part of the well sandwiched between the first and second diffusion layers. A transition region of varying thermal conductivity,
The first diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the second diffusion layer is grounded;
The transition region of the thermal conductivity is characterized in that the thermal conductivity increases continuously from the surface of the semiconductor substrate toward the deeper direction toward the semiconductor substrate below.
  The electrostatic discharge protection element of the present invention includes a first conductivity type semiconductor substrate,
First and second diffusion layers of a second conductivity type different from the first conductivity type formed on the semiconductor substrate at intervals,
From a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate formed in at least a part of the semiconductor substrate between the first diffusion layer and the second diffusion layer. A transition region of varying thermal conductivity,
The first diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the second diffusion layer is grounded;
The transition region of the thermal conductivity is characterized in that the thermal conductivity increases continuously from the surface of the semiconductor substrate toward the deeper direction toward the semiconductor substrate below.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. 1 by taking a MOSFET type as an example.
[0016]
On the p-type semiconductor substrate 11 such as silicon, the first to third high-concentration n⁺ Diffusion layers 12a-12c are provided. The first diffusion layer 12a forms the source region, and the second and third diffusion layers 12b and 12c form the drain region. Silicide layers 13a to 13c for reducing the resistance are formed on the surfaces of the first to third diffusion layers 12a to 12c.
[0017]
A silicide block region 14 in which no silicide layer is formed is provided between the second diffusion layer 12b and the third diffusion layer 12c. Transition of the thermal conductivity changing from a material having a low thermal conductivity to a material having a high thermal conductivity in at least a part of the silicide block region 14 from the deep region of the semiconductor substrate 11 positioned below the figure, for example, the silicide block region 14. A region, for example, a mixed crystal semiconductor region 15 such as SiGe is formed. A gate electrode 16 is provided on the semiconductor substrate 11 between the first diffusion layer 12a and the second diffusion layer 12b. Sidewall insulating films 17 are formed on both sides of the gate electrode 16, and a gate insulating film 18 is formed below the gate electrode 16.
[0018]
An extension region is provided on the surface of the semiconductor substrate 11 to alleviate the concentration difference between the first to third diffusion layers 12a to 12c and the adjacent layers, and end portions 19a and 19b are formed from the first diffusion layer 12a. The region extends below the gate insulating film 18 and from the second diffusion layer 12 b to the region below the gate insulating film 18.
[0019]
In the extension region, the junction depth of impurities is shallower than that of the first to third diffusion layers 12a to 12c, which are called high-concentration diffusion layers, and the maximum impurity concentration is low. In this case, the impurity region of the silicide block region 14 is, for example, an extension region.
[0020]
The silicide layer 13a and the gate electrode 16 are grounded through the source wiring S and the gate wiring G, respectively, and the semiconductor substrate 11 is also grounded. The silicide layer 13c is connected to a drain wiring D, and the drain wiring D is connected to a signal input terminal, for example, an input signal line 22 connecting an input pad 20 and an internal circuit 21 such as a memory. In FIG. 1, the drain wiring D is connected to the input signal line 22, but may be connected to an output signal line from which a signal is output from the internal circuit 21. The input pad 20 or the internal circuit 21 is formed on the semiconductor substrate 11.
[0021]
In the above-described configuration, for example, when a surge occurs in the input signal line 22, the collision bipolarization generated between the drain diffusion layer and the semiconductor substrate 11 is triggered to turn on the parasitic bipolar transistor formed inside the ESD protection element. Thus, the ESD protection element becomes conductive. At this time, a current path through which current flows on the surface of the semiconductor substrate 11, for example, the silicide block region 14 between the second diffusion layer 12b and the third diffusion layer 12c, and the channel region between the first diffusion layer 12a and the second diffusion layer 12b Is formed, the signal line 22 is grounded, and the internal circuit 21 is protected from the surge.
[0022]
Here, the composition distribution of the SiGe mixed crystal semiconductor region 15 formed in the silicide block region 14 will be described with reference to FIG.
[0023]
The left vertical axis in FIG. 2 indicates the thermal conductivity (WK^-1cm^-1), The right vertical axis represents the Ge composition ratio (%), the horizontal axis represents the depth (nm) from the surface of the semiconductor substrate 11, the symbol L is the thermal conductivity, and the symbol R is the composition ratio.
[0024]
As the depth from the surface of the semiconductor substrate increases, the Ge composition ratio decreases as indicated by the symbol R, and the thermal conductivity increases as indicated by the symbol L. Conversely, when the depth from the surface of the semiconductor substrate becomes shallower, the Ge composition ratio increases and the thermal conductivity becomes lower. Therefore, the mixed crystal semiconductor region 15 forms a transition region in which the thermal conductivity increases from the high temperature region where the temperature rises due to current from the high temperature region where the temperature rises due to the current from the current path to the semiconductor substrate 11 region located below the figure. Yes.
[0025]
In this case, heat has a property of easily moving from a low thermal conductivity region to a high region. Even if the temperature of the surface of the semiconductor substrate 11 such as the silicide block region is increased by the current flowing in the current path, the heat is The semiconductor substrate 11 having high thermal conductivity moves to the deeper side. For example, it moves from the current path to the semiconductor substrate 11 and is radiated through the semiconductor substrate 11. As a result, heat concentration on the silicide block region 14 is avoided and thermal destruction is prevented.
[0026]
Here, the time change of the maximum temperature when a surge is input through the drain wiring D will be described with reference to FIG.
[0027]
In FIG. 3, the horizontal axis indicates time (ns), and the vertical axis indicates the maximum lattice temperature (K). The maximum lattice temperature is the surface temperature of the central portion of the silicide block region 14, where P is the prior art and Q is the invention. As can be seen from FIG. 3, the increase in the lattice temperature is suppressed in the present invention (reference numeral Q) than in the conventional ESD protection element (reference numeral P).
[0028]
Next, a method for manufacturing the above-described ESD protection element will be described with reference to FIG. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description is partially omitted.
[0029]
First, the gate insulating film 18 and the gate electrode 16 are formed on the p-type semiconductor substrate 11 (FIG. 4A). Next, impurities are introduced by ion implantation to form extension regions 19 (FIG. 4B). Next, an insulating film 41 is deposited (FIG. 4C). Next, the deposited insulating film 41 is removed by etching, and the sidewall insulating film 17 is formed on the sidewall of the gate electrode 16 (FIG. 4D). Next, a Ge film 42 is deposited (FIG. 4E). Next, a Ge region 421 for solid phase diffusion is formed by anisotropic etching (FIG. 4F). Next, an impurity for the high-concentration diffusion layer to be the source region and the drain region is introduced by ion implantation, and the first to third n⁺ Diffusion layers 12a to 12c are formed (FIG. 4G). Next, a Co film 43 is deposited (FIG. 4H). Next, the extension region 19 and the first to third n are annealed.⁺ The diffusion layers 12a to 12c are activated. At this time, the first to third n⁺ CoSi2 silicide layers 13a-13c are formed in the diffusion layers 12a-12c, and the second and third n layers are formed.⁺ A SiGe mixed crystal semiconductor region 15 is formed in the silicide block region 14 located between the silicide layers 13b and 13c on the diffusion layers 12b and 12c so that the depth thereof substantially overlaps the silicide block region 14, for example. Then, the unreacted Co film 43 is removed by etching, and the Ge region 421 for solid phase diffusion is removed (FIG. 4I).
[0030]
In the case of the above-described embodiment, the silicide block region 14 is provided in the extension region 19, and the resistance is high. Therefore, even if the silicide block region 14 is not lengthened, the high electric field generated between the drain diffusion layer and the semiconductor substrate 11 is relaxed and thermal destruction is prevented.
[0031]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 5, parts corresponding to those in FIG.
[0032]
In this embodiment, the SiGe mixed crystal semiconductor region 15 is formed in the silicide block region 14 of the high-concentration n + diffusion layer 51 serving as the drain region. In this case, since the resistance of the silicide block region 14 is small, an increase in the resistance of the entire ESD protection element can be suppressed. Therefore, heat generation due to the current flowing through the silicide block region 14 is reduced, and an increase in the lattice temperature is suppressed.
[0033]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 6, parts corresponding to those in FIGS. 1 and 5 are given the same reference numerals, and duplicate explanations are omitted.
[0034]
In the case of this embodiment, the silicide layer 61 is formed almost entirely on the high concentration diffusion layer 51. A SiGe mixed crystal semiconductor region 15 is formed in a current path, for example, a channel region immediately below the gate insulating film 18. In this case, the heat generated by the current flowing in the channel region is efficiently dissipated from the channel region to the deep side of the semiconductor substrate 11, and thermal destruction is prevented.
[0035]
In the configuration of FIG. 6, if a silicide block region is provided in a part of the high-concentration diffusion layer 51, higher resistance to surge is realized by the action of the silicide block region. Further, as described with reference to FIG. 2, if the SiGe mixed crystal semiconductor region is provided in the silicide block region, an increase in the lattice temperature in the silicide block region can be reduced.
[0036]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 7, parts corresponding to those in FIG.
[0037]
In this embodiment, the SiGe mixed crystal semiconductor region 15 is provided in both the channel region and the silicide block region 14. In this case, the silicide block region 14 may be an extension region or a high-concentration diffusion layer, and these are determined according to the size of the surge and the restriction on the chip area.
[0038]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 8, parts corresponding to those in FIG.
[0039]
In this embodiment, for example, a base layer 81 made of a mixed crystal semiconductor of SiC is formed first, except for a partial region close to the surface of the semiconductor substrate 11, and then the thermal conductivity of the silicide block region 14 in the extension region is increased. A transition region, for example, a mixed crystal semiconductor region 82 is formed. In this case, the mixed crystal semiconductor region 82 is formed of SiC, and, for example, the composition ratio of C of SiC gradually decreases toward the surface of the semiconductor substrate 11. In this case, the mixed crystal semiconductor region 82 has a thermal conductivity distribution similar to that in FIG. 3 from the surface of the semiconductor substrate 11 in the depth direction, that is, the thermal conductivity from the surface of the semiconductor substrate 11 toward the deep direction. A higher distribution is formed, and the same effect as in the case of SiGe is obtained.
[0040]
Next, another embodiment of the present invention will be described with reference to FIG. 9, parts corresponding to those in FIGS. 1, 6, and 8 are denoted by the same reference numerals, and a part of overlapping description is omitted.
[0041]
In this embodiment, the SiC mixed crystal semiconductor region 82 is formed in the silicide block region 14 of the high concentration diffusion layer 51. In this case, since the silicide block region 14 has a low resistance, the resistance of the entire ESD protection element does not increase, and an increase in lattice temperature due to resistance loss can be suppressed.
[0042]
Next, another embodiment of the present invention will be described with reference to FIG. 10, parts corresponding to those in FIGS. 1 and 6 are denoted by the same reference numerals, and a duplicate description is omitted.
[0043]
In this embodiment, the SiC mixed crystal semiconductor region 82 is formed in the channel region immediately below the gate insulating film 18. In this case, heat generated in the channel region can be efficiently dissipated to the semiconductor substrate 11 side, and thermal destruction is prevented.
[0044]
In FIG. 10, if a silicide block region is provided in a part of the high-concentration diffusion layer 51, higher resistance to surge is realized. Further, as described with reference to FIG. 8, if a SiC mixed crystal semiconductor region is provided in the silicide block region, an increase in the lattice temperature of the silicide block region can be suppressed.
[0045]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 11, parts corresponding to those in FIGS. 1 and 8 are denoted by the same reference numerals, and a part of overlapping description is omitted.
[0046]
In this embodiment, a SiC mixed crystal semiconductor region 82 is formed in both the channel region and the silicide block region 14. In this case, the silicide block region 14 may be an extension region or a high-concentration diffusion layer, and these are determined according to the amount of surge and the restriction of the chip area.
[0047]
Each of the above embodiments is applied to a so-called GGMOSFET (Gate-Grounded Metal-Oxide-Semiconductor Field-Effect-Transistor) type ESD protection element that clamps the potentials of the gate and source diffusion layers. However, the present invention can also be applied to an ESD protection element such as a resistance type other than the GGMOSFET type, a diode type, a bipolar transistor type, or a thyristor type.
[0048]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 12, parts corresponding to those in FIG.
[0049]
In the case of this embodiment, an n-well 1201 made of a donor impurity that becomes a high resistance region is formed in the upper layer region of the semiconductor substrate 11, and a high-concentration diffusion layer such as a donor impurity is formed in the n-well 1201 near the surface of the semiconductor substrate 11. Two n⁺ Diffusion layers 1202 and 1203 are formed at predetermined intervals. Two n⁺ In the n-well 1201 between the diffusion layers 1202 and 1203, a mixed crystal semiconductor region 15 such as SiGe whose thermal conductivity increases from the surface of the semiconductor substrate 11 in the depth direction is formed. The diffusion layer 1202 is connected to the input pad 20, and the diffusion layer 1203 is connected to the internal circuit 21. In this case, two n⁺ Heat generated in the current path between the diffusion layers 1202 and 1203 is dissipated in the deep direction of the semiconductor substrate 11.
[0050]
In the case of FIG. 12, the same effect can be obtained even if the semiconductor substrate 11, the well 1201, and the diffusion layers 1202 and 1203 are made of different conductivity types.
[0051]
Next, another embodiment of the present invention will be described with reference to FIG. 13 by taking a diode type as an example. In FIG. 13, parts corresponding to those in FIG.
[0052]
In this embodiment, the n-well 1201 on the semiconductor substrate 11 has two high-concentration diffusion layer regions, that is, p + diffusion layer 1301 and n⁺ Diffusion layers 1302 are formed at predetermined intervals, and a diode structure is formed inside the device. Then, a mixed crystal semiconductor region 15 such as SiGe whose thermal conductivity increases in the depth direction from the surface of the semiconductor substrate 11 is formed in a high resistance n-well 1201 between so-called pn junctions between the two diffusion layers 1301 and 1302. Has been. Also in this case, heat generated in the current path between the two diffusion layers 1301 and 1302 when a surge occurs is dissipated in the deep direction of the semiconductor substrate 11. Note that the diffusion layers 1301, 1302 and the like can be formed of different conductivity types.
[0053]
Next, another embodiment of the present invention will be described with reference to FIG. 14, taking a bipolar transistor type as an example. In FIG. 14, parts corresponding to those in FIG.
[0054]
In the case of this embodiment, two n are formed on the p-type semiconductor substrate 11.⁺ Diffusion layers 1401 and 1402 are formed at predetermined intervals, and a bipolar transistor structure is formed inside the device. A mixed crystal semiconductor region 15 such as SiGe whose thermal conductivity increases in the depth direction is formed between the two diffusion layers 1401 and 1402 on the surface of the semiconductor substrate 11. Also in this case, the heat generated in the current path between the two diffusion layers 1401 and 1402 when a surge occurs is dissipated in the deep direction of the semiconductor substrate 11.
[0055]
Note that the semiconductor substrate 11, the diffusion layers 1401, 1402, and the like can be formed of different conductivity types.
[0056]
Next, another embodiment of the present invention will be described with reference to FIG. 15, taking a thyristor type as an example. In FIG. 15, parts corresponding to those in FIG.
[0057]
In this embodiment, a p-type epitaxial growth layer 1501 is formed on the p-type semiconductor substrate 11, and an n-well 1502 is formed in a partial region of the epitaxial growth layer 1501. High concentration of n over both epitaxial growth layer 1501 and n-well 1502⁺ A diffusion layer 1503 is provided. Further, a high concentration of p is formed on the epitaxial growth layer 1501.⁺ Diffusion layers 1504 and n⁺ Diffusion layers 1505 are formed at predetermined intervals, and a high-concentration p is formed on the n-well 1502.⁺ Diffusion layer 1506 and n⁺ Diffusion layers 1507 are formed at a predetermined interval. A gate electrode 1508 is provided on the semiconductor substrate 11 between the diffusion layer 1503 and the diffusion layer 1505, and a gate insulating film 1509 is formed below the gate electrode 1508. The gate electrode 16 and the diffusion layers 1504 and 1505 and the semiconductor substrate 11 are grounded, and the diffusion layers 1506 and 1507 are connected to the signal line 22 to form a thyristor structure inside the element. A SiGe mixed crystal semiconductor region 15 is formed between a region including the boundary between the epitaxial growth layer 1501 and the n-well 1502, for example, between the diffusion layer 1505 and the diffusion layer 1506 on the semiconductor substrate 11.
[0058]
Also in this case, even when a current flows in the current path between the two diffusion layers 1505 and 1506 and heat is generated when a surge occurs, the heat is dissipated toward the deeper side of the semiconductor substrate 11.
[0059]
The semiconductor substrate 11, the well 1502, the epitaxial growth layer 1501, the diffusion layers 1503 to 1507, etc. can be configured with different conductivity types.
[0060]
In each of the embodiments described above, the mixed crystal semiconductor region whose thermal conductivity increases from the surface of the semiconductor substrate in the depth direction is provided, for example, in the whole or a part of the current path formed between the high-concentration diffusion layers. ing. However, if the cost can be reduced by simplifying the process, a mixed crystal semiconductor region can be formed on the entire surface of the semiconductor substrate.
[0061]
Further, the concentration of Ge or C in the mixed crystal semiconductor region may be continuously changed in the depth direction of the current path or may be changed stepwise. Further, when the thermal conductivity of the current path is smaller than the thermal conductivity of the semiconductor substrate, there is an effect that heat is dissipated from the current path toward the semiconductor substrate side below the current path. Therefore, the concentration of Ge or C in the mixed crystal semiconductor in the current path may be constant within a range where the thermal conductivity of the current path is smaller than the thermal conductivity of the semiconductor substrate adjacent below the current path. However, when the concentration of the mixed crystal semiconductor is continuously changed and the thermal conductivity is gradually changed, the heat transfer effect in the current path and from the current path to the semiconductor substrate side below the current path becomes larger.
[0062]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the electrostatic discharge protection element which improved the tolerance with respect to the thermal destruction of an ESD protection element is realizable.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining an embodiment of the present invention.
FIG. 2 is a characteristic diagram illustrating characteristics of a mixed crystal semiconductor region constituting the present invention.
FIG. 3 is a characteristic diagram illustrating a heat dissipation effect according to the present invention.
FIG. 4 is a process diagram for explaining a method of manufacturing an ESD protection element of the present invention.
FIG. 5 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 12 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 13 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 14 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 15 is a schematic cross-sectional view for explaining another embodiment of the present invention.
FIG. 16 is a schematic cross-sectional view for explaining a conventional example.
FIG. 17 is a schematic cross-sectional view for explaining a conventional example.
[Explanation of symbols]
11 ... Semiconductor substrate
12a-12c ... diffusion layer
13a-13c ... Silicide
14 ... Silicide block region
15 ... Mixed crystal semiconductor region
16 ... Gate electrode
17 ... Side wall insulating film
18 ... Gate insulating film
19a, 19b ... extension area
20 ... Input pad
21 ... Internal circuit
22 ... Signal line

Claims (5)

A semiconductor substrate;
A drain diffusion layer forming a drain region in which a first silicide layer and a second silicide layer are formed apart from the surface of the semiconductor substrate;
A source diffusion layer forming a source region in which a third silicide layer is formed;
A gate electrode located on the semiconductor substrate between the drain diffusion layer and the source diffusion layer via an insulating film;
Thermal conductivity that changes from a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate, formed in at least part of the first silicide layer and the second silicide layer. Transition region, and
The drain diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the source diffusion layer and the gate electrode are grounded ,
The transition region of the thermal conductivity is characterized in that the thermal conductivity is continuously increased from the surface of the semiconductor substrate toward a semiconductor substrate below the semiconductor substrate in a deep direction. element. A semiconductor substrate;
A first conductivity type well formed on the surface of the semiconductor substrate;
First and second diffusion layers having the same conductivity type as the first conductivity type formed in the first conductivity type well at intervals,
A material having a low thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate formed in at least a part of the first conductivity type well sandwiched between the first and second diffusion layers. A transition region of thermal conductivity that changes to a high material,
Coupled to an input pad of the first diffusion layer is provided on the semiconductor substrate, said second diffusion layer is connected to an internal circuit provided on said semiconductor substrate,
In the electrostatic discharge protection element , the thermal conductivity transition region continuously increases from the surface of the semiconductor substrate toward a deeper direction toward the semiconductor substrate below . A semiconductor substrate;
A first conductivity type well formed on the surface of the semiconductor substrate;
A first diffusion layer of the same conductivity type as the first conductivity type formed in the first conductivity type well with an interval, and a second diffusion layer of a second conductivity type different from the first conductivity type;
From a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate, formed in at least a part of the well sandwiched between the first and second diffusion layers. A transition region of varying thermal conductivity,
The first diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the second diffusion layer is grounded ;
In the electrostatic discharge protection element , the thermal conductivity transition region continuously increases from the surface of the semiconductor substrate toward a deeper direction toward the semiconductor substrate below . A first conductivity type semiconductor substrate;
First and second diffusion layers of a second conductivity type different from the first conductivity type formed on the semiconductor substrate at intervals,
From a material having a low thermal conductivity to a material having a high thermal conductivity in a direction away from the surface in the thickness direction of the semiconductor substrate formed in at least a part of the semiconductor substrate between the first diffusion layer and the second diffusion layer. A transition region of varying thermal conductivity,
The first diffusion layer is connected to an input signal line or an output signal line provided on the semiconductor substrate, and the second diffusion layer is grounded ;
Transition region of the thermal conductivity, the semiconductor from the substrate surface toward a deep direction toward semiconductors substrate thereunder, electrostatic discharge protection device, characterized in that thermal conductivity increases continuously. The transition region of thermal conductivity is formed of SiGe in which the composition ratio of Ge decreases toward the direction away from the surface of the semiconductor substrate, or SiC in which the composition ratio of C decreases toward the surface of the semiconductor substrate . The electrostatic discharge protection element according to claim 1 .

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