JP3842869B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having an element isolation structure by a trench element isolation method among methods for defining an element formation region on a semiconductor substrate.
[0002]
[Prior art]
A trench element isolation structure is known as a structure for electrically isolating elements on a semiconductor substrate. In this element isolation structure, for example, an element formation region is defined by embedding an insulating film layer made of an oxide film, a nitride film or the like in a groove formed in a semiconductor substrate made of silicon, for example. At present, a trench element isolation structure consisting of a groove having a width of about 1 μm and a depth of several μm is possible.
[0003]
As described above, the trench isolation structure can reduce the width of the element isolation region that defines the element and can sufficiently secure the depth direction, so that the element isolation area is larger than that of the LOCOS (Local Oxidation Of Silicon) method. It has the greatest advantage that it can be greatly reduced.
[0004]
Such a trench element isolation structure is formed as follows, for example. 4 to 5 show a trench element isolation structure according to a conventional manufacturing method in the order of the manufacturing process.
[0005]
First, as shown in FIG. 4A, after a thermal oxide film 32 is formed on a p-type silicon semiconductor substrate 31, for example, a p-type impurity 33 is ion-implanted. Thereafter, as shown in FIG. 4B, a p-type well diffusion layer 34 is formed by performing heat treatment to diffuse and stabilize the impurities.
[0006]
Next, as shown in FIG. 4C, after an oxide film layer 35 is deposited on the thermal oxide film 32, a portion of the oxide film for forming the trench element isolation region is formed by photolithography and subsequent dry etching. The layer 35 is removed, and the remaining photoresist on the oxide film layer 35 is removed.
[0007]
Thereafter, using the oxide film layer 35 as a mask, the thermal oxide film 32 is removed by anisotropic etching, and at the same time, the p-type silicon semiconductor substrate 31 is removed to form a groove 36. During this anisotropic etching, a crystal surface damage layer 37 such as a SiC layer or a polymer layer is simultaneously formed on the surface layer from the bottom surface to the side surface of the groove 36.
[0008]
Next, as shown in FIG. 4D, a sacrificial oxide film 38 is formed on the inner wall of the trench 36 by dry oxidation, and the crystal surface damage layer 37 is taken into the inside. Thereafter, the thermal oxide film 32, the oxide film layer 35, and the sacrificial oxide film 38 are removed by wet etching, and at the same time, the crystal surface damage layer 37 taken into the sacrificial oxide film 38 is removed.
[0009]
Next, as shown in FIG. 5A, a surface oxide film 39 is formed from the upper surface of the p-type well diffusion layer 34 and the bottom surface to the side surface of the groove 36. Then, as shown in FIG. 5B, the oxide film layer 40 is formed by filling the groove 36 by a low pressure CVD method.
[0010]
Then, the oxide film layer 40 is removed until the p-type silicon semiconductor substrate 1 in which the p-type well diffusion layer 34 is formed is exposed, and the trench element isolation region 41 is completed as shown in FIG.
[0011]
[Problems to be solved by the invention]
When the trench element isolation region 41 is formed by the method described above, the following problems have occurred.
[0012]
As shown in FIG. 5C, after the trench element isolation region 41 is completed by a conventional method, an element is formed in the element formation region. Is required.
[0013]
Due to the heat treatment in the subsequent process, the p-type silicon semiconductor substrate 31 and the surface oxide film 39 and the oxide film layer 40 have different thermal expansion coefficients, so that internal stress is generated. Defects such as slips and transitions are formed in the crystal lattice at the interface of the layers. And the leak current flows through this defect, and the problem that element isolation performance fell occurred.
[0014]
In addition, in the step of forming the trench element isolation region 41, when the groove 36 is formed by anisotropic etching, a crystal surface damage layer such as a SiC layer or a polymer layer is simultaneously formed. After the sacrificial oxide film 38 was formed and taken in, the sacrificial oxide film 38 had to be removed, requiring many extra steps.
[0015]
The present invention has been made to solve such problems, and minimizes degradation of element isolation performance due to heat treatment at the time of element formation in a subsequent process after the element isolation structure is formed. It is an object of the present invention to provide a method for manufacturing a trench element isolation structure in which the number of steps when forming the element isolation structure is reduced.
[0016]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device of the present invention includes a first step of forming a first insulating film on a semiconductor substrate, a second step of forming a heat resistant insulating film on the first insulating film,
A third step of selectively removing a part of the heat-resistant insulating film, the first insulating film, and the semiconductor substrate to form a groove in the semiconductor substrate; and a step of forming the semiconductor substrate including the inside of the groove A fourth step of introducing impurities to the entire surface, and a fifth step of forming a second insulating film on the entire surface of the semiconductor substrate including the inside of the trench in an atmosphere of excess oxygen and / or excess nitrogen. Then, heat treatment is applied to diffuse the impurities into the semiconductor substrate, and excess oxygen and / or excess nitrogen in the second insulating film is diffused into the semiconductor substrate. A sixth step of filling the trench, and a seventh step of removing the second insulating film and the heat-resistant insulating film until the first insulating film is exposed.
[0017]
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the oxidation is performed in an atmosphere containing oxygen and / or ozone between the third step and the fourth step, and the trench exposed. The method further includes the step of forming a silicon oxide film on the surface region of the semiconductor substrate, and the step of removing the silicon oxide film between the fourth step and the fifth step.
[0018]
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the thickness of the second insulating film is 30 to 45% of the minimum width of the groove.
[0019]
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the first insulating film is a silicon thermal oxide film.
[0020]
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the heat-resistant insulating film is a silicon nitride film.
[0021]
[Action]
In the method of manufacturing a semiconductor device of the present invention, the groove formed on the semiconductor substrate is filled with the second insulating film containing excess oxygen and / or excess nitrogen, and the longest time is reached at the highest temperature in all the steps. By heat treatment for diffusing the well diffusion layer, excess oxygen and / or excess nitrogen in the second insulating film is diffused into the semiconductor substrate to form a thermally stable insulating film. This makes it possible to form an interface that minimizes the generation of internal stress due to the difference in thermal expansion coefficient between the semiconductor substrate and the second insulating film during the heat treatment at a temperature lower than that in the subsequent process. .
[0022]
Further, as a series of etching steps, anisotropic etching for forming the groove is performed, followed by isotropic etching in an atmosphere of oxygen or / and ozone, so that the surface region of the semiconductor substrate exposed to the groove is oxidized with silicon. A film can be formed. Then, by removing this silicon oxide film, the crystal surface damage layer formed in the groove can be removed without complicating the process.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and manufacturing method of an nMOS transistor according to an embodiment of the present invention will be described with reference to FIGS.
[0024]
As shown in FIG. 1A, a thermal oxide film 2 is formed on a p-type silicon semiconductor substrate 1 by dry oxidation at a temperature of 900 ° C., and a nitride film 3 is formed on the thermal oxide film 2 by a low pressure CVD method. . Next, a resist pattern 4 having an opening 5 having a width of about 1 μm is formed on the nitride film 3 by a photolithography process. This state is shown in FIG.
[0025]
Next, using this resist pattern 4 as a mask, the nitride film 3, the thermal oxide film 2 and the p-type silicon semiconductor substrate 1 are removed by anisotropic etching, and a groove 6 having a depth of about 3 μm is formed in the p-type silicon semiconductor substrate 1. Form. On the inner wall surface of the groove 6, an SiC layer, a polymer layer, and the like are simultaneously formed as the crystal surface damage layer 7 by anisotropic etching. This state is shown in FIG.
[0026]
Next, isotropic etching is performed in an atmosphere of oxygen or ozone to remove the crystal surface damage layer 7 and simultaneously react the oxygen or ozone with the p-type silicon semiconductor substrate 1 exposed in the groove 6. An oxide film 8 is formed in a region from the bottom surface to the side surface of the groove 6. This state is shown in FIG.
[0027]
In this way, by switching from anisotropic etching to isotropic etching in an oxygen or ozone atmosphere within the etching process for forming the groove 6 and continuously performing the etching, the number of special processes can be increased. The surface damage layer 7 can be removed.
[0028]
Next, as shown in FIG. 2A, after the resist pattern 4 is removed by etching, phosphorus (P) 9 which is an impurity for forming the n-type well diffusion layer 12 is dosed at an acceleration energy of about 120 to 180 kev. Ion implantation is performed under the condition of an amount of about 1 × 10 ^{13 to} 3 × 10 ¹³ / cm ² .
[0029]
In this embodiment, since an nMOS transistor is formed, phosphorus (P) 9 is ion-implanted. However, when a pMOS transistor is formed, boron (B) is accelerated at an energy of about 40 to 80 kev and a dose amount is 5 × 10 ¹² to Ion implantation may be performed under conditions of about 2 × 10 ¹³ / cm ² .
[0030]
Next, the entire surface is washed with a fluorine solution or the like, and the oxide film 8 formed in the groove 6 is removed.
[0031]
Thereafter, the oxide film 10 is formed on the entire surface by a low pressure CVD method in an excess oxygen atmosphere, for example, under the condition of silane: O ₂ = 1: 100 to 200 (unit is cc). The thickness of the oxide film 10 is suitably 30 to 45% of the minimum width of the groove 6. In this embodiment, the width of the groove 6 is 1 μm, so that the thickness is about 3000 mm.
[0032]
Since the oxide film 10 is formed in an excessive oxygen atmosphere, it contains a large amount of unreacted oxygen molecules inside. As shown in FIG. 2B, the oxide film 10 is formed in the groove 6 along the side surface from the bottom surface, and the gap 11 is formed on the top surface by setting the film thickness as described above.
[0033]
Note that the film formed at this time is an insulating film, and it is sufficient that it contains excessively unreacted molecules that react with the p-type silicon semiconductor substrate 1 by heat treatment in a later step. For example, an oxynitride film may be formed instead of the oxide film. When forming an oxynitride film, it is formed by a low pressure CVD method in an excess oxygen and nitrogen atmosphere, for example, under the conditions of silane: O ₂ : NH ₄ = 5: 250: 1 to 2 (unit is cc).
[0034]
Next, heat treatment is performed in a nitrogen atmosphere at a temperature of 1150 ° C. for a time of about 360 minutes to diffuse phosphorus (P) 9 which is an ion-implanted impurity, thereby forming an n-type well diffusion layer 12.
[0035]
By this heat treatment, excessive oxygen molecules in the oxide film 10 are simultaneously diffused into the crystal of the p-type silicon semiconductor substrate 1 and react with the silicon in the p-type silicon semiconductor substrate 1 to form the oxide film layer 13. The oxide film layer 13 fills the groove 6 and fills the gap 11. This state is shown in FIG.
[0036]
Thus, oxygen is diffused at the interface between the p-type silicon semiconductor substrate 1 and the oxide film 10 in order to diffuse oxygen by performing the heat treatment that is the highest temperature in all the steps. It is possible to form an interface in which the generation of defects due to the difference in thermal expansion coefficient between the silicon semiconductor substrate 1 and the oxide film layer 13 is suppressed as much as possible.
[0037]
Thereafter, the formed oxide film layer 13 is polished and removed by a CMP (chemical mechanical polishing) method using a fluorine-based solution until the nitride film 3 is exposed. Alternatively, the oxide film layer 13 may be removed by plasma etching.
[0038]
Thereafter, the nitride film 3 is removed using phosphoric acid warmed to about 190 ° C., and the thermal oxide film 2 is removed using hydrofluoric acid, whereby the trench element isolation region 14 as shown in FIG. Finalize.
[0039]
Next, as shown in FIG. 3A, after the p-type silicon semiconductor substrate 1 is thermally oxidized to form a gate oxide film 24, an impurity such as phosphorus (P) is added to the entire surface by low-pressure CVD. Then, the polycrystalline silicon film 15 is formed, and as shown in FIG. 3B, the polycrystalline silicon film 15 and the gate oxide film 24 are removed by etching while leaving the gate portion 16 by photolithography and subsequent dry etching. .
[0040]
Next, using the trench element isolation region 14 and the gate portion 16 as a mask, phosphorus (P) or arsenic (As), which are n-type impurities, for example, an acceleration energy of about 60 to 100 kev and a dose of 5 × 10 ^{15 to} 5 After ion implantation on the p-type silicon semiconductor substrate 1 under the condition of about × 10 ¹⁶ / cm ² , heat treatment is performed under a temperature condition of about 900 ° C. to diffuse, thereby forming the source layer 17 and the drain layer 18 of the nMOS transistor. To do.
[0041]
By the high-temperature heat treatment for diffusion of phosphorus (P) 9 described above, oxygen is diffused from the oxide film layer 13 into the p-type silicon semiconductor substrate 1 to stabilize this interface. Thermal stress due to the difference in thermal expansion coefficient between the p-type silicon semiconductor substrate 1 and the oxide film layer 13 in the heat treatment for forming the drain layer 18 can be reduced.
[0042]
Next, as shown in FIG. 3C, a BPSG film 19 as an interlayer insulating film is deposited over the entire surface by a CVD method, and then a reflow process is performed. Then, contact holes 20, 21, and 22 that expose the polycrystalline silicon film 15 that is the gate electrode, the source layer 17, and the drain layer 18 are opened. Thereafter, aluminum wiring 23 is deposited by sputtering to fill the contact holes 20, 21, 22 and patterning is performed to complete an nMOS transistor as shown in FIG.
[0043]
As described above, in this embodiment, the heat treatment for forming the n-type well diffusion layer 12 is performed for a long time under the high temperature condition of 1150 ° C., which is the highest temperature in all the steps, and phosphorus (P) 9 At the same time, oxygen molecules in the oxide film 10 are diffused into the p-type silicon semiconductor substrate 1 and reacted with silicon in the p-type silicon semiconductor substrate 1 to form a thermally stable oxide film layer 13. To do. Oxide film layer 13 can suppress the occurrence of internal stress due to the difference in thermal expansion coefficient between p-type silicon semiconductor substrate 1 and oxide film 13 during subsequent heat treatment at a low temperature.
[0044]
Therefore, even in the heat treatment when forming the source layer 17 and the drain layer 18 of the nMOS transistor in the subsequent process, defects such as slips and transitions in the crystal lattice at the interface between the p-type silicon semiconductor substrate 1 and the oxide film layer 13 are also obtained. Occurrence can be prevented. As a result, it is possible to configure an nMOS transistor in which loss due to leakage current from defects is minimized.
[0045]
Further, the anisotropic etching for forming the groove portion is performed by using the crystal surface damage layer 7 such as the SiC layer or the polymer layer generated in the anisotropic etching step for forming the groove 6 of the trench element isolation region 14 as a series of etching steps. Subsequently, isotropic etching can be performed in an oxygen or / and ozone atmosphere. As a result, the crystal surface damage layer 7 can be removed without forming a sacrificial oxide film or the like as in the prior art, so that the number of steps can be reduced.
【The invention's effect】
According to the present invention, it is possible to minimize defects in the crystal lattice at the interface between the trench element isolation structure and the semiconductor substrate, which are generated by heat treatment during element formation. Furthermore, the damage layer generated when forming the trench having the trench isolation structure can be removed in the same process. Therefore, it is possible to provide a method for manufacturing a trench element isolation structure with improved element isolation performance without complicating the process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
FIG. 4 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in order of steps.
FIG. 5 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.
[Explanation of symbols]
1 p-type silicon semiconductor substrate 2 thermal oxide film 3 nitride film 6 groove 8 phosphorus (P)
10 oxide film 12 n-type well diffusion layer 13 oxide film layer

Claims (5)

A first step of forming a first insulating film on a semiconductor substrate;
A second step of forming a heat-resistant insulating film on the first insulating film;
A third step of selectively removing a part of the heat-resistant insulating film, the first insulating film and the semiconductor substrate to form a groove in the semiconductor substrate;
A fourth step of introducing impurities into the entire surface of the semiconductor substrate including the inside of the groove;
A fifth step of forming a second insulating film on the entire surface of the semiconductor substrate including the inside of the trench in an atmosphere of excess oxygen and / or excess nitrogen;
Heat treatment is applied to diffuse the impurities into the semiconductor substrate, and excess oxygen and / or excess nitrogen in the second insulating film is diffused into the semiconductor substrate. A sixth step of filling the groove;
A seventh step of removing the second insulating film and the heat-resistant insulating film until the first insulating film is exposed;
A method for manufacturing a semiconductor device, comprising: Between the third step and the fourth step,
Performing oxidation in an atmosphere containing oxygen and / or ozone to form a silicon oxide film on the surface region of the semiconductor substrate exposed in the groove;
Between the fourth step and the fifth step,
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the second insulating film is 30 to 45% of the minimum width of the groove. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon thermal oxide film. The method for manufacturing a semiconductor device according to claim 1, wherein the heat-resistant insulating film is a silicon nitride film.

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