JP3850585B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit using an inductance parasitic to a lead terminal of a package and an inductance parasitic to a bonding wire as elements constituting the circuit.
[0002]
[Prior art]
In integrated circuits that handle high-frequency signals in the UHF band or higher, the parasitic inductance of lead terminals and the parasitic inductance of bonding wires may be actively used as components of circuits such as resonant circuits.
[0003]
As described above, when using the parasitic inductance of the lead terminal and the bonding wire, one or a plurality of lead terminals and bonding wires arranged on one side of the package are used. In this case, the parasitic inductance value varies due to the assembly of the package. In the assembly process of the semiconductor integrated circuit, when the pellet is mounted on the frame, there is a case where the mounting deviation occurs in the X direction, the Y direction, or the rotation direction with respect to a desired mounting point due to mechanical accuracy. Further, when bonding wires are connected between the pellet and the frame, there is a case where the bonding point is displaced. As a result, the length of the bonding wire serving as the parasitic inductance and the length serving as the parasitic inductance component of the lead terminal are shifted, thereby varying the value of the parasitic inductance. The increase or decrease in the variation of the parasitic inductance is one direction of increasing or decreasing because the lead terminals and bonding wires used as the parasitic inductance are arranged on one side of the package.
[0004]
For example, in two lead terminals and bonding wires, the parasitic inductance of one lead terminal is uniformly L1, the parasitic inductance of one bonding wire is uniformly L2, and the coefficient of increase or decrease of the parasitic inductance L2 of the bonding wire is α ( When 0 <α ≦ 1), the combined inductance L obtained by combining the parasitic inductances of the two lead terminals and the bonding wire is expressed by the following equation.
[0005]
[Expression 1]
L = ((L1 + L2) + (± α * L2)) * ((L1 + L2) + (± α * L2)) / (2 * ((L1 + L2) + (± α * L2)))
= ((L1 + L2) + (± α * L2)) / 2
= (L1 + L2) / 2 ± (α * L2) / 2 ...... Equation (1)
From the above equation, a deviation of ± (α * L2) / 2 occurs in the combined inductance L.
[0006]
This deviation of the inductance component increases the fluctuation range of the resonance frequency, and if the signal frequency becomes higher, there is a possibility that the yield of the product is drastically reduced due to the deviation of the resonance frequency.
[0007]
[Problems to be solved by the invention]
As described above, in the conventional semiconductor integrated circuit using the parasitic inductance of the lead terminal and the bonding wire as a circuit component, the lead terminal and the bonding wire used as the parasitic inductance are used for the package of the semiconductor integrated circuit. Lead terminals and bonding wires arranged on one side were used. For this reason, there has been a problem that the parasitic inductance value varies due to assembly of the package.
[0008]
Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor integrated circuit capable of suppressing variations in parasitic inductance of lead terminals and bonding wires used as circuit constituent elements. There is.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a first means for solving the problem is a semiconductor integrated circuit in which the parasitic inductance of the bonding wire is used as a circuit component of a semiconductor integrated circuit that handles a high-frequency signal. It is characterized by comprising a plurality of bonding wires arranged in parallel on opposite sides and connected in parallel.
[0010]
The second means is a semiconductor integrated circuit in which the parasitic inductance of the bonding wire and the parasitic inductance of the lead terminal of the package connected to the bonding wire are used as a circuit component of a semiconductor integrated circuit that handles high frequency signals. And the lead terminal connected to the bonding wire comprises a plurality of bonding wires and lead terminals arranged on opposite sides of the package and connected in parallel.
[0011]
A third means is characterized in that, in the first or second means, the bonding wires or the bonding wires and the lead terminals connected to the bonding wires are an even number.
[0012]
According to a fourth means, in the first, second, or third means, the parasitic inductance of the bonding wire, or the parasitic inductance of the bonding wire and the lead terminal connected to the bonding wire constitutes a resonance circuit. It is characterized by becoming.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0014]
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
[0015]
In FIG. 1, the semiconductor integrated circuit of this embodiment is one in which the present invention is applied to a leadless semiconductor integrated circuit and the parasitic inductance of the bonding wire is used as an inductance of a circuit, for example, a series resonant circuit. In the pellet 2 mounted on the leadless package 1, an FET (field effect transistor) 3 and a capacitor (Cx) 4 connected to the FET 3 are formed as circuit components inside the pellet 2, and the capacitor 4 is One end of a corresponding bonding wire 6 is connected to each of the pair of electrode pads 5 arranged and formed on opposite sides of the pellet 2, and the other end of each bonding wire 6 is connected to the package. Are connected to the corresponding electrodes 7. In such a configuration, the parasitic inductance of the pair of bonding wires 6 is connected in parallel to the FET 3 and the capacitor 4 which are circuit components in the pellet, and a series resonance circuit is configured. It is expressed as shown in FIG.
[0016]
In such an embodiment, since the pair of bonding wires 6 serving as the parasitic inductance constituting the resonance circuit are arranged separately on the opposite sides of the pellet 2, the pellets in the assembly process for mounting the pellet are arranged. The increase / decrease direction of the length of the bonding wire 6, that is, the parasitic inductance value of the bonding wire, is opposite to the positional deviation in the X direction, the Y direction, and the rotation direction. Therefore, the deviation of the combined inductance obtained by synthesizing the parasitic inductances of the pair of bonding wires 6 is suppressed as compared with the conventional case, and variations in the parasitic inductance can be suppressed. As a result, the fluctuation range of the resonance frequency of the resonance circuit can also be reduced as compared with the conventional case.
[0017]
FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.
[0018]
In FIG. 3, this embodiment is characterized in that the present invention is applied to a semiconductor integrated circuit with a lead terminal, and the parasitic inductance of the bonding wire and the parasitic inductance of the lead terminal are used as the inductance of a circuit, for example, a series resonance circuit. Compared with the configuration shown in FIG. 1, the other end of each bonding wire 6 is connected to the corresponding lead terminal 8 of the package 1 to form a resonance circuit as shown in the equivalent circuit of FIG. 4. It is to have done.
[0019]
In such an embodiment, when the combined inductance is obtained in the same manner as described in the section of the prior art, it is expressed by the following equation.
[0020]
[Expression 2]
L = ((L1 + L2) + αL2) * ((L1 + L2) -α * L2) / (((L1 + L2) + α * L2) + ((L1 + L2) -α * L2))
= ((L1 + L2) ^2- (α * L2) ² ) / (2 * (L1 + L2))
= ((L1 + L2) / 2- (α * L2) ² ) / (2 * (L1 + L2)) ...... Equation (2)
From the above equation, the deviation of the combined inductance can be suppressed to-(α * L2) ² ) / (2 * (L1 + L2)), which can be reduced compared to the deviation of equation (1) described above. It becomes.
[0021]
For example, the fluctuation width of the resonance frequency (fo = 1 / (2π√ (LC)) due to the assembly variation of the resonance circuit using the parasitic inductance of the two pairs of lead terminals, the parasitic inductance of the bonding wire, and the MIM capacitor is expressed by the above formula. The composite inductance L represented by (1) is compared with the composite inductance L represented by formula (2) in the above embodiment, where the capacitance of the MIM capacitor is 0.5 (pF) and the lead terminal The parasitic inductance and the parasitic inductance of the bonding wire are 0.6 (nH) and .8 (nH) (this value is generally used in the SSOP-8 package), and the coefficient α is 0.3. In this case, using the combined inductance L represented by the conventional equation (1), the minimum (fomin) and maximum (fomax) resonance frequencies are calculated as shown below, and the deviation from the desired resonance frequency is as follows. As shown in the order of 8.8%.
[0022]
[Equation 3]
fo (desired frequency) = 1 / (2 * π * √ (((L1 + L2) / 2) * C)) = 8.51GHz
fomax (maximum frequency) = 1 / (2 * π * √ ((((L1 + L2) -α * L2) / 2) * C)) = 9.35GHz
fomin (minimum frequency) = 1 / (2 * π * √ ((((L1 + L2) + α * L2) / 2) * C)) = 7.86GHz
Frequency error = (fomax-fomin) /2/fo*100=8.8%
On the other hand, in the above embodiment, when the combined inductance L represented by the expression (2) is used, the minimum (fomin) and maximum (fomax) resonance frequencies are calculated as follows, and the desired resonance is obtained. The deviation from the frequency is about 1.5% as shown below.
[0023]
[Expression 4]
fo (desired frequency) = 1 / (2 * π * √ (((L1 + L2) / 2) * C)) = 8.51GHz
fomax (maximum frequency) = 1 / (2 * π * √ (((L1 + L2) / 2- (α * L2) ² /(2*(L1+L2)))*C))=8.64
GHzfomin (minimum frequency) = 1 / (2 * π * √ (((L1 + L2) / 2) * C)) = 8.51GHz
Frequency error = (fomax-fomin) /fo*100=1.5%
As described above, in the above-described embodiment, it is possible to suppress the variation of the combined inductance that combines the parasitic inductances of the lead terminal and the bonding wire, and to greatly suppress the fluctuation range of the resonance frequency compared to the conventional case.
[0024]
FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.
[0025]
In FIG. 5, this embodiment is characterized in that the parasitic inductance of another pair of bonding wires 9 is used as compared with the embodiment shown in FIG. 1, and one end of each bonding wire 9 is a pellet. 2, the other end of each bonding wire 9 is connected to the corresponding electrode 11 of the package 1, the resonance circuit is configured as shown in the equivalent circuit of FIG. Same as 1.
[0026]
In such an embodiment, the same effect as that of the above embodiment can be obtained.
[0027]
The present invention is not limited to the above embodiment, and does not limit the bonding wires used as parasitic inductance, the number of lead terminals, the circuit configuration using parasitic inductance, and the pellet mounting form.
[0028]
【The invention's effect】
As described above, according to the present invention, a plurality of bonding wires arranged on opposite sides of a package and connected in parallel or a parasitic inductance of a plurality of bonding wires and a lead terminal are used. Variations in parasitic inductance due to the assembly of the integrated circuit can be suppressed. As a result, it is possible to suppress the fluctuation range of the resonance frequency, and it is possible to suppress a decrease in product yield.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing an equivalent circuit of the resonance circuit of FIG. 1;
FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.
4 is a diagram showing an equivalent circuit of the resonance circuit of FIG. 3. FIG.
FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.
6 is a diagram showing an equivalent circuit of the resonance circuit of FIG. 5. FIG.
[Explanation of symbols]
1 Package 2 Pellet 3 FET
4 Capacity 5, 10 Electrode pad 6, 9 Bonding wire 7, 11 Package electrode 8 Lead terminal

Claims (4)

In a semiconductor integrated circuit that uses the parasitic inductance of a bonding wire as a circuit component of a semiconductor integrated circuit that handles high-frequency signals,
2. The semiconductor integrated circuit according to claim 1, wherein the bonding wire includes a plurality of bonding wires arranged on opposite sides of the package and connected in parallel. In a semiconductor integrated circuit in which a parasitic inductance of a bonding wire and a parasitic inductance of a lead terminal of a package connected to the bonding wire are used as a circuit component of a semiconductor integrated circuit that handles high-frequency signals.
The semiconductor integrated circuit according to claim 1, wherein the bonding wire and the lead terminal connected to the bonding wire include a plurality of bonding wires and lead terminals arranged in parallel on opposite sides of the package. 3. The semiconductor integrated circuit according to claim 1, wherein the bonding wire, or the bonding wire and the lead terminal connected to the bonding wire are an even number. 4. The semiconductor integrated circuit according to claim 1, wherein the parasitic inductance of the bonding wire or the parasitic inductance of the bonding wire and the lead terminal connected to the bonding wire constitutes a resonance circuit. circuit.

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