JP3851073B2 - Wireless communication device and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wireless communication device such as a mobile phone and a semiconductor device incorporated in the wireless communication device, and more particularly, a single-stage configuration using a single high-power amplifier in which a plurality of transistors are connected in parallel, or a plurality of high-power amplifiers sequentially dependent. The present invention relates to a wireless communication apparatus having a multi-stage high frequency power amplification module connected to a transmitter output stage and an antenna connected to the high frequency power amplification module, and is applied to thermal runaway prevention, efficiency improvement, and oscillation prevention techniques. It relates to effective technology.
[0002]
[Prior art]
In mobile communication devices (wireless communication devices) such as automobile phones and mobile phones, a high-frequency power amplification module (high-frequency power amplification circuit) is incorporated in the output side of the transmission side. The output (transmission power) of the high-frequency power amplification module is automatically controlled by a bias control circuit (APC: Automatic Power Control circuit).
[0003]
In general, in a mobile phone, a system that does not cause interference with other mobile phones by changing the output so as to be applied to the surrounding environment by a power level instruction signal transmitted from a base station according to the usage environment. Has been built. The cellular phone receives the power level instruction signal and outputs a predetermined signal (control signal) from the bias control circuit to the amplifier of the high frequency power amplification module, thereby adjusting the output of the wireless communication device.
[0004]
The high-frequency power amplification module has a single-stage configuration using one semiconductor amplification element (transistor) or a multi-stage configuration in which a plurality of transistors are connected in series. As the transistors, bipolar transistors, MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors), GaAs-MES (Metal-Semiconductor) FETs, HEMTs (High Electron Mobility Transistors), HBTs (Heterojunction Bipolar transistors), and the like are used.
[0005]
US Pat. No. 5,629,648 discloses a heterojunction bipolar transistor high-power amplifier circuit. In this document, in a plurality of transistors connected in parallel, a resistor for supplying a DC bias to each base and a capacitor for supplying an AC signal are provided for each transistor, and thermal runaway is suppressed by a voltage drop of the resistor supplying DC. A high power bipolar transistor circuit is described which is characterized by:
[0006]
On the other hand, Japanese Patent Laid-Open No. 7-7014 (US Pat. No. 5,321,279) discloses an emitter finger (emitter terminal), a base finger (base terminal), a collector finger (collector) in order to operate the apparatus with reliability. In an Si bipolar transistor having a multi-finger structure having a terminal, a power HBT is disclosed in which a ballast impedance is connected to a base finger to suppress thermal runaway (current hopping: hot spot). That is, by providing a ballast impedance (resistor) on each base finger, hot spots due to current concentration are suppressed.
[0007]
In this document, a capacitor (bypass capacitor) is connected in parallel with the ballast impedance (resistor) in order to ensure the minimum gain loss of the transistor. Further, it is described that the power HBT can be a high power amplifier and can be used for a cellular telephone.
[0008]
On the other hand, Japanese Patent Application Laid-Open No. 7-94975 discloses a high-frequency HIC module (high-frequency power amplification module) having a three-stage configuration in which MOSFETs are cascade-connected to a first stage, a middle stage, and a final stage. This high-frequency HIC module is configured such that the first bias circuit is configured to bias the gate of a predetermined MOSFET of a plurality of stages of MOSFETs based on an output control voltage, and the gates of the remaining MOSFETs other than the predetermined MOSFET A second bias circuit for biasing based on a fixed power supply, and switch means for switching a path between the fixed power supply and the second bias circuit according to the output control voltage. Thereby, the controllability of the output is improved and the efficiency is improved. Each bias circuit is composed of three resistors and one capacitor.
[0009]
[Problems to be solved by the invention]
Since the HBT has excellent characteristics such as high speed and low power consumption, it is being used as a semiconductor amplification element of a high frequency power amplification module incorporated in a wireless communication device such as a mobile phone.
[0010]
During the development of a mobile phone power amplifier module (high frequency power amplifier module) using an HBT, the present inventor studied means for improving efficiency while suppressing both thermal runaway and oscillation phenomenon of the HBT element. It has been confirmed that the following problems occur in a wireless communication apparatus employing a conventionally known circuit.
[0011]
FIG. 18 is a schematic circuit diagram of a part of a wireless communication apparatus incorporating a single-stage amplifier (high frequency power amplification module) using one multi-fingered HBT. The circuit configuration of the above-mentioned US Pat. No. 5,629,648 ( This is a circuit employing Conventional Example 1). Here, for the convenience of the following description, a portion composed of one emitter terminal (emitter finger), base terminal (base finger), and collector terminal (collector finger) is referred to as a transistor (unit cell). A transistor group in which the plurality of transistors are connected in parallel is referred to as a multi-finger transistor or a multi-finger transistor. Therefore, the HBT becomes one multi-finger transistor.
[0012]
The high frequency power amplifying module 1 includes, as external terminals, an input terminal (RFin), an output terminal (RFout), a first voltage terminal (Vcc) also serving as a collector terminal, a second voltage terminal (ground: GND) serving also as an emitter terminal, a base It has a bias terminal (control terminal: Vapc) that also serves as a terminal. The antenna 2 is connected to the output terminal (RFout) through a filter (not shown).
[0013]
The HBT is a multi-finger transistor and has a structure in which N transistors are connected in parallel. The transistors Q1A to Q1N are composed of an emitter terminal 5, a base terminal 6, and a collector terminal 7, respectively.
[0014]
This circuit has a structure in which an input terminal and a control terminal are separated. Junction capacitors C2A to C2N are inserted and connected between the base terminals 6 and the input terminals of the transistors Q1A to Q1N, and the bases of the transistors Q1A to Q1N are connected. Ballast resistors R2A to R2N are inserted and connected between the terminal 6 and the control terminal.
[0015]
The first voltage terminal (Vcc) and each collector terminal 7 are connected to a single inductor Lc, and each emitter terminal 5 is connected to the ground (GND). The high frequency power amplification module 1 is provided with a matching circuit 9 on the output side in order to achieve impedance matching with the antenna 2.
[0016]
In this wireless communication apparatus, since the AC signal is supplied only through the capacity, the efficiency of the wireless communication apparatus is increased to about 60% (equivalent to about 70% in the efficiency of the high-frequency power amplification module). In this case, since there is no loss in the signal path, the stability of the element is deteriorated and an oscillation phenomenon is likely to occur, and there is a possibility that stable communication cannot be performed. In other words, the impedance for expecting an external circuit at a high frequency is small, the stabilization coefficient K is remarkably small, and the transistor becomes unstable.
[0017]
FIG. 6 is a graph showing the correlation between the stabilization coefficient K and the collector current. In the graph, Conventional Example 1 is a curve showing a stabilization coefficient value. The stabilization coefficient K is about 0.15 when the collector current is 0.01 A, and further increases as the collector current value increases. Becomes smaller.
[0018]
FIG. 7 is a graph showing the relationship between input power (dBm) and power added efficiency (%). In the graph, Conventional Example 1 is a curve showing added efficiency, and the maximum value reaches a maximum value of about 68.5% at a point where the input power is large, that is, about 25 dBm.
[0019]
19 and 20 are schematic circuit diagrams of a part of a wireless communication apparatus incorporating a single-stage amplifier (high-frequency power amplification module) using one multi-fingered HBT. Each of the circuits adopting the circuit configuration described in the above. In the circuit configuration of FIG. 19, the ballast resistors R1A to R1N are simply inserted between the base terminal 6 and the control terminal (Vapc) of each of the transistors Q1A to Q1N. However, the ballast resistor is sufficient to prevent thermal runaway. When the value is used, the high frequency signal is attenuated, and the amplification characteristic may be significantly impaired.
[0020]
The circuit of FIG. 20 is a circuit (conventional example 2) in which bypass capacitors C1A to C1N are inserted in parallel with resistors R1A to R1N in order to prevent attenuation of high-frequency signals. It is necessary to increase the value of the semiconductor chip (for example, about 50 pF), and there is a dislike of increasing the area of the semiconductor chip into which the HBT is incorporated, and the number of semiconductor chips acquired from one semiconductor substrate (wafer) decreases. The manufacturing cost of a semiconductor element (ie, a semiconductor device) increases. Further, it has been found that since the impedance for expecting an external circuit at a high frequency becomes small, the stabilization coefficient K decreases and the circuit easily oscillates. As shown in the graph of FIG. 6, the stabilization coefficient K is better than that of the conventional example 1, but is far from the stabilization coefficient 1 at which oscillation does not easily occur, and is stabilized when the collector current is between 0.01 and 1A. The coefficient K is about 0.5 to about 0.75.
The capacitors C1A to C1N connected in parallel to the resistors R1A to R1N are for increasing the high-frequency gain. However, if the capacitance value is increased in order to increase the gain, oscillation tends to occur. On the other hand, if the capacitance value is reduced, the effect of high frequency gain is reduced, and optimal design becomes difficult.
[0021]
An object of the present invention is to provide a wireless communication device in which an oscillation phenomenon hardly occurs even in a high efficiency region of the wireless communication device, and a semiconductor device (semiconductor element) incorporated in the wireless communication device.
[0022]
Another object of the present invention is to provide a wireless communication device that suppresses thermal runaway, has high efficiency, and does not easily cause an oscillation phenomenon, and a semiconductor device (semiconductor element) incorporated in the wireless communication device.
[0023]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0024]
[Problems to be solved by the invention]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0025]
(1) A single-stage amplifier using a single multi-finger heterojunction bipolar transistor (HBT) or a high-frequency power amplifying module including a multi-stage amplifier in which a plurality of HBTs are sequentially connected in cascade is provided in the transmission-side output stage, In a wireless communication device having an antenna connected to an amplification module,
A first capacitor and a first resistor inserted and arranged in series between the input terminal of the high-frequency power amplification module and each control terminal of the HBT;
And a second resistor connected to a node between the first resistor and the first capacitor. The second resistor is inserted between the control terminal of the high-frequency power amplifier module and each control terminal of the HBT.
A semiconductor device (semiconductor element) incorporated in a radio communication device controls an input terminal, an output terminal, a bias terminal, a first terminal and a second terminal, and a current flowing between the first terminal and the second terminal. And a first capacitor connected between the input terminal and the control terminal of each of the transistors, and a first capacitor connected to the input terminal. C2A to C2N and first resistors R1A to R1N connected in series to the first capacitors C2A to C2N and connected to the control terminal, and arranged between the bias terminal and the control terminal of each of the transistors, First resistors R1A to R1N and second resistors R2A to R2N connected to a node between the first capacitors C2A to C2N are provided, and the output terminal is connected to each first terminal of the transistor. It has become adult.
[0026]
(2) The configuration of the means (1) includes a second capacitor connected in parallel to the first resistor. The semiconductor device incorporated in such a wireless communication device has a configuration having the second capacitors C1A to C1N connected in parallel to the first resistors R1A to R1N in the configuration of (1).
[0027]
(3) In the means (1) or (2), an inductor is inserted and connected to the base terminal and / or the emitter terminal.
[0028]
(4) A high-frequency power amplification module including a single-stage amplifier using a single heterojunction bipolar transistor (HBT) having a multi-finger structure or a multi-stage amplifier in which a plurality of HBTs are sequentially connected in cascade is provided in the transmission-side output stage, and the high-frequency power In a wireless communication device having an antenna connected to an amplification module,
The thermal design is such that the difference in thermal resistance between the plurality of terminals (fingers) of the HBT constituting one stage of the amplifier is sufficiently small compared to the average thermal resistance of the fingers,
A first resistor inserted and arranged in series between the input terminal of the high-frequency power amplification module and each control terminal of the HBT;
A first capacitor connected between an input terminal of the high-frequency power amplifier module and a node connecting the plurality of first resistors;
A control terminal of the high-frequency power amplifier module; and a second resistor connected to a node between the first resistor and the first capacitor.
[0029]
According to the means of (1), (a) the second resistor causes a base voltage drop with an increase in base current due to a temperature rise of the HBT chip, so that an increase in current of each transistor is suppressed and thermal runaway is suppressed. The Accordingly, the same effect can be obtained in the semiconductor device (semiconductor element).
[0030]
(B) Further, the first resistor becomes a high frequency loss to prevent excessive increase in gain, thereby stabilizing each transistor and preventing oscillation. Therefore, the same effect is also achieved in the semiconductor device.
[0031]
(C) By inserting and connecting the first resistor, the second resistor, and the first capacitor, a highly efficient wireless communication device can be provided. For example, in a high-frequency power amplification module, if an HBT is used, the number of transistors is about 100, and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time, assuming that the current amplification factor is about 80, the first capacitance is about 0.15 pF, the first resistance is about 100 ohms, and the second resistance is about 1 kiloohm, and an efficiency of about 70% can be achieved (see FIGS. 7 and 8). ). During this high efficiency operation, the direct current flowing through the first resistor is about 0.2 to 0.5 mA, the voltage drop across the first resistor is 20 to 50 mV, and the loss is small. From FIG. 9, the change in efficiency is small up to 2.5 times the value of the first resistor, that is, about 250Ω (2.5Ω when 100 lines are paralleled), and the voltage drop at the first resistor at this time is 50 to 50 It is sufficiently small as 25 mV. This is about 60% in the efficiency of the wireless communication device, and a highly efficient wireless communication device can be achieved.
[0032]
(D) It becomes difficult for the amplifier to run away or oscillate due to temperature fluctuations or power fluctuations, and stable communication can be performed without hindering transmission of radio signals.
[0033]
(E) The high frequency gain can be increased by connecting a capacitor in parallel with the first resistor, but oscillation occurs when the capacitance value is increased. In the present invention, since the capacitor is not connected to the first resistor, the oscillation of the base ballast resistor can be suppressed. Therefore, the same effect is also achieved in the semiconductor device.
[0034]
According to the means (2), (a) a first resistor and a second resistor are connected in series and connected to a base terminal, and a second capacitor is connected in parallel to the first resistor. The resistance value of the first resistor can be lowered. As a result, the bypass capacitance (second capacitance) connected in parallel to the first resistor can also be reduced. Conventionally, for example, the capacity of about 50 pF can be reduced to about 1/10 of about 5 pF, and the chip area can be reduced by the capacity. Therefore, the cost reduction of the semiconductor amplifying element (semiconductor element: semiconductor chip) can be achieved.
[0035]
(B) Since the circuit configuration is a combination of the first resistor, the second resistor, the first capacitor, and the second capacitor, the degree of freedom in circuit design in the semiconductor chip is increased. On the other hand, since it is necessary to arrange the first resistor, the second resistor, the first capacitor, and the second capacitor, the element arrangement on the chip is limited.
[0036]
Further, the attenuation of the high-frequency signal by the first resistor is reduced by bypassing through the second capacitor, thereby increasing the efficiency of the amplifier. For example, in FIG. 7, the same efficiency as that of Conventional Example 1 can be obtained.
[0037]
Even in the case of the means (2), the efficiency in comparison with the condition where the gain of the amplifier is saturated, that is, the point where the input power is large as shown in FIG. 7, for example, 25 dBm, is not provided. There is almost no difference. This is because the gain increase caused by the second capacitor bypassing the loss of the high frequency signal in the first resistor and the accompanying increase in efficiency are canceled out by the gain saturation effect of the amplifier.
[0038]
Therefore, when saturation occurs in the gain of the amplifier during use, it is not based on the means of (2) in consideration of the difficulty in chip design due to the complicated element arrangement and the increase in chip area due to the increase in the number of elements. That is, the configuration shown in FIG. 1 is desirable, and when the gain of the amplifier does not saturate, high efficiency can be obtained by means (2).
[0039]
According to the means (3), the negative feedback can be applied by the insertion connection of the inductor, and the circuit is stabilized.
[0040]
According to the means of (4), (a) the second resistor causes a base voltage drop accompanying an increase in the base current due to a temperature rise in the entire multi-finger HBT. Runaway is suppressed.
[0041]
(B) Further, the first resistor becomes a high frequency loss to prevent excessive increase in gain, thereby stabilizing each transistor and preventing oscillation.
[0042]
(C) Also, since the first resistor causes a different base voltage drop for each finger due to a difference in base current increase due to a temperature rise difference of each HBT finger (unit transistor), the difference in collector current is reduced, It suppresses that current concentrates on one finger and operates each finger uniformly.
[0043]
(D) A highly efficient and small wireless communication device can be provided by inserting and connecting the first resistor, the second resistor, and the first capacitor. For example, in a high-frequency power amplification module, if an HBT is used, the number of transistors is about 100, and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time, assuming that the current amplification factor is about 80, the first capacitance is about 0.15 pF, the first resistance is about 100 ohms, and the second resistance is about 1 kiloohm, and an efficiency of about 70% can be achieved (see FIGS. 7 and 8). ). During this high efficiency operation, the direct current flowing through the first resistor is about 0.2 to 0.5 mA, the voltage drop across the first resistor is 20 to 50 mV, and the loss is small. From FIG. 9, the change in efficiency is small up to 2.5 times the value of the first resistor, that is, about 250Ω (2.5Ω when 100 lines are paralleled), and the voltage drop at the first resistor at this time is 50 to 50 It is sufficiently small as 25 mV. This is about 60% in the efficiency of the wireless communication device, and a highly efficient wireless communication device can be achieved.
[0044]
(E) In the arrangement of elements, only the first resistor needs to be arranged for each HBT, and the second resistor and the first capacitor are formed from a plurality of HBTs arranged so that the difference in thermal resistance is small. Since it is sufficient to provide for each block, the degree of freedom of element arrangement increases. Moreover, the area of the isolation region between elements is reduced by reducing the total number of resistance / capacitance elements. This makes it easy to design a low-cost chip (semiconductor device) with a reduced area.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
[0046]
(Embodiment 1)
1 to 9 show a wireless communication apparatus according to an embodiment (Embodiment 1) of the present invention. as well as It is a figure concerning a semiconductor device (semiconductor element). In the first embodiment, an example of a semiconductor element (semiconductor chip) using a heterojunction bipolar transistor (HBT) as a semiconductor amplifying element will be described.
[0047]
FIG. 1 shows a radio communication apparatus having a single-stage amplifier (high-frequency power amplification module 1) incorporating one HBT in a transmission-side output stage, and an antenna 2 connected to the high-frequency power amplification module 1 via a filter or the like (not shown). FIG. 3 is a schematic circuit diagram of a part of FIG. FIG. 2 is a schematic diagram showing a state in which the high-frequency power amplification module 1 packaged on the wiring board 10 of the wireless communication device such as a cellular phone is mounted. External terminals (electrodes) are respectively provided on the lower surface of the high-frequency power amplification module 1, and these electrodes are mechanically and electrically connected to predetermined wirings 11 provided on the wiring board 10 via a bonding material. The antenna 2 is connected to the wiring 11 that is electrically connected to the output terminal of the high-frequency power amplification module 1 through the conductor 12.
[0048]
The high-frequency power amplification module 1 has an external terminal as an input terminal (RFin), an output terminal (RFout), a first voltage terminal (Vcc: collector terminal), a second voltage terminal (GND: emitter terminal), and a control as a bias terminal. It has a terminal (Vapc: base terminal). Although not shown, the antenna 2 is connected to the output terminal via a filter or the like.
[0049]
The amplifier of the high-frequency power amplification module 1 is composed of a heterojunction bipolar transistor (HBT) incorporated in a semiconductor chip (semiconductor element). This HBT is a multi-finger transistor, which has a structure in which N transistors are connected in parallel, and constitutes a high-power amplifier. The transistors Q1A to Q1N are composed of an emitter terminal 5, a base terminal 6, and a collector terminal 7, respectively. Each terminal (finger) is bundled into one and becomes a base terminal, an emitter terminal, and a collector terminal, respectively. The collector terminal is connected to the output terminal (RFout) via the matching circuit 9. The collector electrode is connected to a first voltage terminal (Vcc: collector terminal) via an inductor Lc. The inductor Lb suppresses leakage of a high frequency (RF) signal, and the power supply potential is stabilized.
[0050]
The circuit of the first embodiment has a structure in which an input terminal and a bias terminal (control terminal) are separated, and first capacitors C2A to C2N as junction capacitors between the base terminals 6 and the input terminals of the transistors Q1A to Q1N. The first resistors R1A to R1N are inserted and connected in series as ballast resistors. Further, second resistors R2A to R2N that cause a voltage drop are inserted and connected between a node between the first resistors R1A to R1N and the first capacitors C2A to C2N and a bias terminal (control terminal). .
[0051]
The resistance values of the second resistors R2A to R2N are larger than those of the first resistors R1A to R1N. This is to suppress thermal runaway of the HBT by causing a voltage drop when the temperature of the semiconductor chip rises and the current flowing through the HBT increases. In order to suppress this thermal runaway, for example, the resistance values of the second resistors R2A to R2N are about 10 times larger than the first resistors R1A to R1N. The first resistors R1A to R1N can be reduced by inserting and connecting the second resistors R2A to R2N.
[0052]
An HBT having a multi-finger structure is, for example, an HBT having InGaP as an emitter and GaAs as a base and a collector.
[0053]
FIG. 3 is a schematic plan view showing a part of a semiconductor element (semiconductor chip) constituting an amplifier including an HBT, and corresponds to the circuit of FIG. 4 is a cross-sectional view taken along the line AA 'in FIG. 3, and FIG. 5 is a cross-sectional view taken along the line BB' in FIG.
[0054]
As shown in FIG. 3, a plurality of first capacitors C2A to C2N (also simply referred to as a capacitor C2) are arranged side by side in the center of the drawing. One electrode (capacitor lower layer wiring metal 16) of the first capacitors C2A to C2N is connected to an input terminal (RFin). The other capacitor electrode (wiring metal 15) is connected to one end of first resistors R1A to R1N (also simply referred to as resistor R1) of the transistor. A capacitor C2 (see FIG. 5) is formed by interposing a capacitor insulating film 14 in an intersecting region between the capacitor lower layer interconnect metal 16 and the interconnect metal 15. The other end of the resistor R1 is connected to another independent wiring metal 15, and this wiring metal 15 is connected to the base terminal 6 (portion 41 in FIG. 5) of the transistors Q1A to Q1N.
[0055]
Each collector terminal 7 (portion indicated by 40 in FIG. 5) of the transistors Q1A to Q1N is connected to another independent wiring metal 15. The wiring metal 15 is connected to an output terminal (RFout). Further, the emitter terminal 5 (portion indicated by 42 in FIG. 5) is connected to another independent wiring metal 15 (ground line). The ground line is connected to a back surface electrode 22 (on the back surface (lower surface) of the semiconductor chip (semiconductor element: semiconductor amplifying element) via a conductor 19 filled in the via hole and an etching stopper 21 made of a conductor provided thereunder. GND) (see FIG. 4).
[0056]
On the other hand, the other electrode (wiring metal 15) of the capacitor C2 is connected to one end of second resistors R2A to R2N (also simply referred to as a resistor R2). Another independent wiring metal 15 is connected to the other end of the resistor R2. The wiring metal 15 is connected to a bias terminal (control terminal: base terminal). With such a structure, the amplifier circuit of FIG. 1 is configured.
[0057]
Next, the cross-sectional structure relationship between the HBT, the capacitor C2, the resistor R1, and the resistor R2 will be described with reference to FIGS. The semiconductor amplifying element incorporating these capacitor C2, resistor R1 and resistor R2 is monolithically formed on the semi-insulating GaAs substrate 30. In addition, about the dimension etc. of each part, what is not especially required in this invention is abbreviate | omitted.
[0058]
On the semi-insulating GaAs substrate 30, n ⁺ A type GaAs subcollector layer 31 is provided, and this n ⁺ An n-type GaAs collector layer 32 is provided on the type GaAs subcollector layer 31. The n-type GaAs collector layer 32 has a mesa portion that is selectively etched to a halfway depth and protrudes partially. In the region where the thin n-type GaAs collector layer 32 is formed away from the mesa, the n-type GaAs collector layer 32 is partially removed by etching, and a collector electrode 40 is provided in the removed portion.
[0059]
P on the mesa ⁺ Type GaAs base layer 33, n type InGaP emitter layer 34, n ⁺ The type GaAs cap layers 35 are provided so as to sequentially overlap. p ⁺ The n-type GaAs base layer 33 and the n-type InGaP emitter layer 34 have substantially the same size and overlap each other. ⁺ The type GaAs cap layer 35 is formed in an elongated rectangular shape in the center of the mesa portion.
[0060]
N ⁺ The n-type InGaP emitter layer 34 and the n-type InGaP emitter layer 34 and n ⁺ The type GaAs cap layer 35 is etched away to provide a contact hole, and a base electrode 41 is provided in the contact hole portion.
[0061]
The upper surface of the semi-insulating GaAs substrate 30 is covered with an insulating film 45 that protects the surface. The middle layer of the insulating film 45 has a resistor R1, a resistor R2, a capacitor as shown in FIG. C2 is formed. SiO as the capacitor insulating film 14 ₂ When a laminated film of SiN and SiN is used, a capacity with a small leakage current can be formed. Other materials include high dielectric materials such as strontium titanate (STO) and barium strontium titanate (BST), or tantalum oxide (Ta ₂ O _Five ) Etc., the area of the capacitor C2 can be reduced, and the chip area can be reduced. When a refractory metal nitride such as WN, WSiN, TiN, or TaN is used as the resistor material, a highly reliable resistor can be formed. NiCr alloy or the like can also be applied to the resistor.
[0062]
The insulating film 45 is partially etched away to form contact holes, and the wiring metal 15 formed by patterning the electrodes of the HBT, the electrodes of the resistors R1 and R2, and the electrode of the capacitor C2 is electrically connected. To touch. Before the uppermost insulating film is formed, the n ⁺ An emitter electrode 42 (having two layers in the figure) is formed on the type GaAs cap layer 35. Then, by forming the wiring metal 15 after the contact hole is formed, each wiring metal 15 is connected to the emitter electrode 42, the base electrode 41, and the collector electrode 40, and is connected to each electrode of each capacitor and resistor. The circuit shown in FIG.
[0063]
In the HBT of the first embodiment, the number of transistors Q1A to Q1N is, for example, 100 (N = 100). For example, the emitter size is about 2 μm × 20 μm, the current amplification factor is about 80, the first capacitors C2A to C2N are about 0.15 pF, the first resistors R1A to R1N are about 100 ohms, and the second resistors R2A to R2N Is about 1 kilohm. In this configuration, the output of the high frequency power amplification module 1 is about 4 W. In this case, the efficiency of the high-frequency power amplification module 1 is about 70%, and as a result, the efficiency of the wireless communication apparatus is as high as about 60%.
[0064]
That is, FIG. 6 is a graph showing the transition of the stabilization coefficient with respect to the collector current by the circuit of the first embodiment (the present invention) and the conventional examples 1 and 2, and FIG. 7 is the circuit of the present invention and the conventional example 1. FIG. 8 is a graph showing the correlation between input power and collector added current (PAE), and FIG. 8 shows the relationship between input power (Pin), collector current, and added efficiency in the circuits of Conventional Example 1 and Conventional Example 2. FIG. 9 is a graph showing the correlation. FIG. 9 shows the correlation between the first resistance R1 and the stabilization coefficient K and the added efficiency in the difference in the total resistance (Rtotal) of the first resistance and the second resistance according to the circuit of the first embodiment. It is a graph which shows. These data are comparisons in a circuit in which the efficiency of the high-frequency power amplification module is as high as about 70% and that in the wireless communication apparatus is about 60%.
[0065]
As shown in the graph of FIG. 6, the stabilization coefficient K of Conventional Example 1 is less than 0.5, and an oscillation phenomenon is likely to occur. Further, even in the conventional example 2 in which the capacitors C1A to C1N are connected in parallel to the resistors R1A to R1N, when the collector current is about 0.01A to 0.04A, the stabilization coefficient K is about 0.5, and the collector current is 1.5A. At most, the stabilization coefficient K is less than 0.9, and there is a risk of oscillation.
[0066]
In the circuit configuration of the conventional example 2, the capacitors C1A to C1N connected in parallel to the resistors R1A to R1N are as large as about 50 pF, and the area for forming the capacitors C1A to C1N is increased. The incorporated semiconductor chip (semiconductor device) becomes large.
[0067]
The graph of FIG. 8 is a comparison of the added efficiency in the case of the circuit of the conventional example 1, the case of the circuit in which the capacitors C1A to C1N are set to 25 pF and the case of 50 pF in the conventional example 2. It can be seen that when the capacitances C1A to C1N are set to 25 pF, the added efficiency becomes low and the product cannot be used.
[0068]
FIG. 7 is a curve showing the added efficiency in the case of the circuit of the first embodiment (the present invention) and the circuit of the first conventional example. In the state where the input power is 23 dBm or less, the circuit of the conventional example 1 has somewhat better added efficiency (PAE) than the circuit of the present invention, but in the case of the circuit of the present invention when the input power is about 25 dBm. However, as in the case of the circuit of Conventional Example 1, it can be seen that the added efficiency is as high as about 70% and there is no inferiority. If the input power is 25 dBm, the output power can be 35 dBm.
[0069]
FIG. 9 is a circuit diagram according to the first embodiment, where R1 is a resistance value in which 100 first resistors are connected in parallel, and Rtotal is a resistance value in which 100 series of first and second resistors are connected. It is a graph which shows additional efficiency (PAE) at the time of changing resistance R1 into 0.5 (ohm) -3ohm, when said Rtotal is 7 (ohm), 10 (ohm), 13 (ohm), 16 (ohm), and 20 (ohm).
[0070]
In order not to cause an oscillation phenomenon, the stabilization coefficient K needs to be 1 or more. When the stabilization coefficient K is 1, the additional efficiency can be increased to about 64% even when Rtotal is 7Ω, 10Ω, 13Ω, 16Ω, and 20Ω. Even when the stabilization coefficient K is 2, when the Rtotal is made smaller than 16Ω, the additional efficiency can be kept as high as about 63%.
[0071]
The wireless communication apparatus according to the first embodiment has the following effects by incorporating the semiconductor device (semiconductor element) according to the first embodiment.
[0072]
(1) Since the second resistor causes a base voltage drop with an increase in base current due to a temperature rise of the HBT chip (semiconductor device), an increase in current of each transistor is suppressed and thermal runaway is suppressed.
[0073]
(2) Further, the first resistor becomes a high-frequency loss and prevents an excessive increase in gain, thereby stabilizing each transistor and preventing oscillation.
[0074]
(3) By inserting and connecting the first resistor, the second resistor, and the first capacitor, a highly efficient wireless communication device can be provided. For example, in a high-frequency power amplification module, if an HBT is used, the number of transistors is about 100, and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time, when the current amplification factor is about 80, the first capacitance is about 0.15 pF, the first resistance is about 100 ohms, and the second resistance is about 1 kilohm, and an efficiency of about 70% can be achieved. This is about 60% in the efficiency of the wireless communication device, and a highly efficient wireless communication device can be achieved.
[0075]
(4) It becomes difficult for the amplifier to run away or oscillate due to temperature fluctuation or power supply fluctuation, and stable communication can be performed without hindering transmission of radio signals.
[0076]
(Embodiment 2)
10 and 11 are diagrams relating to a wireless communication apparatus according to another embodiment (Embodiment 2) of the present invention. FIG. 10 is a block diagram showing a multi-stage high-frequency power amplification module and the like. FIG. It is a typical top view which shows the layout of each electronic component of an amplification module.
[0077]
In the second embodiment, an example in which the present invention is applied to a three-stage amplifier (multi-stage amplifier) in which amplifiers (semiconductor amplification elements) amp including HBTs, resistors, and capacitors are sequentially connected in series will be described. This multistage amplifier is incorporated in the output side output stage of the wireless communication apparatus.
[0078]
As shown in FIG. 10, the wireless communication apparatus includes an impedance matching circuit MN1, amp1 (first stage amplifier), an impedance matching circuit MN2, amp2 (middle stage amplifier), an impedance matching circuit between an input terminal (RFin) and an output terminal (RFout). MN3, amp3 (final amplifier), and impedance matching circuit MN4 are inserted and connected in series. Bias terminals (control voltages: Vapc1, Vapc2, Vapc3), which are output signals of the base bias circuit 50, are input to the control terminals (base terminals: bias1, bias2, bias3) of each high-output amplifier (amp1 to amp3). The amplification factor will be controlled. Each of the high output amplifiers (amp1 to amp3) has a circuit configuration according to the first embodiment.
[0079]
FIG. 11 is a layout of each electronic component in the high-frequency power amplification module 1. As semiconductor chips (semiconductor elements), there are bias circuits, amp1, amp2, and amp3 constituting the base bias circuit 50. Each electrode of the semiconductor chip and a predetermined wiring are connected by a conductive wire 51. The chip capacitor and the chip inductor electrode are electrically connected to predetermined wiring by solder or the like (not shown).
[0080]
In amp1, amp2, and amp3, a transistor and a first resistor, a second resistor, and a first capacitor connected to the transistor are schematically illustrated.
[0081]
In the first embodiment, the base bias circuit 50 is not particularly specified. For example, it is assumed that the high-power amplifier at each stage is controlled by a constant control voltage (Vapc). Depending on the base bias circuit 50, it is also possible to control the high-power amplifiers at each stage with a predetermined control voltage, an example of which will be described later.
[0082]
The wireless communication apparatus incorporating the high-frequency power amplification module 1 having the multi-stage amplifier configuration of the second embodiment has the same effect as that of the first embodiment. An increase in output controllability by the control circuit, linearization of the output, and the like can be achieved, and a wireless communication device with high communication performance can be provided.
[0083]
(Embodiment 3)
FIG. 12 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 3) of the present invention. The third embodiment has a structure in which the inductor Lb is inserted between the base terminal and the second resistor group, and the inductor Le is inserted between the emitter and GND in the circuit configuration of the amplifier of the first embodiment. By inserting and connecting the inductor Lb, the impedance expected for the base power supply circuit increases, leakage of a high frequency (RF) signal to the base power supply circuit can be suppressed, and loss due to leakage can be reduced, so that high efficiency can be achieved. . Further, by inserting and connecting the inductor Le, negative feedback is applied and the circuit is stabilized. Since the effects of the inductor Lb and the inductor Le are independent from each other, it is needless to say that the above-described effects are produced even when only the inductor Lb or only the inductor Le is provided.
[0084]
(Embodiment 4)
FIG. 13 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 4) of the present invention. The fourth embodiment has a structure in which, in the circuit configuration of the first embodiment, bypass capacitors that pass high-frequency component signals in parallel with the first resistors R1A to R1N that are ballast resistors, that is, second capacitors C1A to C1N are connected. Yes. In the fourth embodiment, since the first resistors R1A to R1N can be reduced by providing the second resistors R2A to R2N between the base terminal and the base terminal 6, the capacitances of the second capacitors C1A to C1N, which are bypass capacitors. The value can also be reduced. For example, since the first resistors R1A to R1N can be set to about 100Ω, the capacitance values of the second capacitors C1A to C1N can be reduced to about 5 pF. Conventionally, for example, the capacity of about 50 pF can be reduced to about 1/10 of about 5 pF, and the chip area can be reduced by the capacity. As a result, the area for forming the capacitor is reduced, the size of the semiconductor chip is reduced, and the number of semiconductor chips acquired from one semiconductor substrate (wafer) is increased, thereby reducing the manufacturing cost of the semiconductor amplifying element. it can.
[0085]
Further, since the circuit configuration is a combination of the first resistor, the second resistor, the first capacitor, and the second capacitor, the degree of freedom in designing the semiconductor amplifying element and the high-frequency power amplifying module is increased.
[0086]
In addition, the inductor Lb increases the impedance to allow for the base power supply circuit, suppresses leakage of a radio frequency (RF) signal to the base power supply circuit, and reduces loss due to leakage, thereby achieving high efficiency. The inductor Le applies negative feedback to stabilize the circuit. Therefore, this circuit can achieve high efficiency and stabilization.
[0087]
Since the effects of the inductor Lb and the inductor Le are independent from each other, it is needless to say that the above-described effects are produced even when only the inductor Lb or only the inductor Le is provided. Of course, it is not always necessary to use an inductance element if a transmission line or the like is formed on the substrate in place of these inductances and the impedance expected from each terminal is designed to have an appropriate value.
[0088]
(Embodiment 5)
14 to 16 are diagrams related to a wireless communication apparatus according to another embodiment (Embodiment 5) of the present invention. FIG. 14 is a circuit diagram showing a part of the wireless communication apparatus having a single-stage amplification configuration. Is a bias control circuit diagram incorporated in the high-frequency power amplification module, and FIG. 16 is a schematic plan view showing the layout of each electronic component of the high-frequency power amplification module.
[0089]
In the fifth embodiment, as shown in FIG. 14, a current mirror diode (sensor diode) 56 is monolithically integrated on the same semi-insulating semiconductor substrate on which the amplifier body transistor 55 is formed. The main body transistor 55 has the same circuit configuration as that of the first embodiment, and the first capacitors C2A to C2N and the first resistors R1A to R1N are connected in series between the input terminal (RFin) and the base terminal 6, and The second resistors R2A to R2N are inserted and connected between the node between the first capacitors C2A to C2N and the first resistors R1A to R1N and the control terminal (Vapc).
[0090]
The sensor diode 56 includes a diode-connected transistor Qs. The transistor Qs is made of HBT. In order to make a diode connection, a resistor Rs1 and a resistor Rs2 are inserted and connected in series between the base and collector of the transistor Qs. The collector terminal of the transistor Qs becomes Vd, and the emitter terminal becomes GND.
[0091]
By having the current mirror diode 56 on the same semi-insulating semiconductor substrate, when the temperature of the semi-insulating semiconductor substrate rises and the amount of current of the main transistor 55 increases, the current mirror diode 56 has a corresponding amount. Since the amount of current also increases, by controlling the current flowing through the current mirror diode 56 to be constant, the current flowing through the body transistor 55 can be controlled to be constant even when the temperature fluctuates, so that the bias controllability is improved. That is, the sensor diode is on the same chip as the amplification transistor, and is subject to the same temperature fluctuation as the amplification transistor. The current-voltage characteristics between the base and emitter of the transistor and the diode have a strong temperature dependence, but the same current-voltage characteristics are exhibited if the temperature is the same. Therefore, by passing a constant current Id through the sensor diode and driving the base of the transistor with the same voltage as the voltage generated there, the current flowing through the transistor regardless of the temperature change (a sensor diode with Id). The junction area ratio of the base transistor and the emitter of the main transistor can be controlled. The same effect as described above can be obtained by using a sensor transistor instead of the sensor diode.
[0092]
In FIG. 10, the base bias circuit 50 is different from that in the second embodiment as shown in FIG. 15, and the first stage amp1 is a bias (Vapc1) that generates a control in by dividing the resistances Rc1 and Rc2. The control amps 2 and 3 in the middle stage and the final stage are controlled by biases (Vapc2 and Vapc3) generated through emitter followers by the transistors Qb1 and Qb2. The transistor Qs2 connected to the transistor Qb1 is a current mirror diode 56 monolithically formed with the main transistor 55 of amp2, and the transistor Qs3 connected to the transistor Qb2 is a current mirror monolithically formed with the main transistor 55 of amp3. The diode 56 is used. These transistors Qs2 and Qs3 are used as reference voltages when the control-in is generated via the emitter followers by the transistors Qb1 and Qb2.
[0093]
The inductors Lb1 to Lb3 are provided to suppress leakage of high frequency signal components from the control terminals (Vapc1, Vapc2, Vapc3).
[0094]
In this base bias circuit 50, a control voltage based on the divided resistance is input to the control terminal Vapc1, a control current amplified by the amplification factor of the transistor Qb1 is input to the control terminal Vapc2, and a transistor Qb2 is input to the control terminal Vapc3. The control current amplified by the amplification factor is input.
[0095]
FIG. 16 is a layout of each electronic component in the high-frequency power amplification module 1 according to the fifth embodiment. As the semiconductor chip, there are bias circuits, amp1, amp2, and amp3 constituting the base bias circuit 50. Each electrode of the semiconductor chip and a predetermined wiring are connected by a conductive wire 51. The chip capacitor and the chip inductor electrode are electrically connected to predetermined wiring by solder or the like (not shown).
[0096]
In amp1, amp2, and amp3, a transistor and a first resistor, a second resistor, and a first capacitor connected to the transistor are schematically illustrated. In addition, in amp2 and amp3, a current mirror diode is clearly shown although no reference numeral is given. The resistors Rs1 and Rs2 are omitted from the current mirror diode 56 of FIG.
[0097]
(Embodiment 6)
FIG. 17 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (sixth embodiment) of the present invention. The sixth embodiment is a ballast resistor / circuit stabilizing resistor of several (all in the case of FIG. 17) transistors arranged so as to reduce the difference in thermal resistance with each other in the circuit configuration of the first embodiment. 1 resistor R1A to R1N is connected to one node on the opposite side to the side connected to the base terminal 6, and the second resistor R2 is inserted and connected as a single resistor between the node and the bias supply terminal, The first capacitor C2 is inserted and connected as a single junction capacitor between the node and the input terminal.
[0098]
In the sixth embodiment, (a) R2 causes a base voltage drop with an increase in base current due to an increase in temperature of the entire multi-finger HBT, so that an increase in current of the entire multi-finger HBT is suppressed and thermal runaway is suppressed.
[0099]
(B) Further, the first resistors R1A to R1N become high-frequency losses to prevent excessive increase in gain, thereby stabilizing each transistor and preventing oscillation.
[0100]
(C) Also, the first resistors R1A to R1N cause different base voltage drops for each finger in accordance with the difference in base current increase due to the temperature rise difference of each HBT finger. Current concentration on the fingers is suppressed, and each finger is operated uniformly.
[0101]
(D) In the element arrangement, only the first resistors R1A to R1N need to be arranged for each HBT, and R2 and C2 are composed of a plurality of HBTs arranged so as to reduce the difference in thermal resistance. Since it may be provided for each block, the degree of freedom of element arrangement increases, and the area of the isolation region between elements is reduced by reducing the total number of resistance / capacitance elements. Further, since R2 and C2 need only be provided for each block composed of a plurality of HBTs, not only can the area be reduced, but there is a degree of freedom in which the capacity can be externally attached.
[0102]
In this embodiment, “arranged so that the difference in thermal resistance between each other is small” is based on the fact that the thermal resistance between elements is generally about 1/5 or less of the thermal resistance of the entire element, in which case R1 It is an experiment that thermal stability can be obtained if the ratio of resistance to R2 when N are connected in parallel is about twice the ratio of the thermal resistance difference between the elements and the thermal resistance of the entire element. Indicated. For example, if the thermal resistance of the entire element is 20 ° C./W and the thermal resistance difference between the elements is 2 ° C./W, the parallel resistance of the first resistors R 1 A to R 1 N is 2 ohms, and the thermal stability is about R 2 = 8 ohm Sex was obtained. When the number of transistors is 100, R1A = R1N = 200Ω, and only one R2 = 8Ω is arranged compared to the case where 100 R2A = R2N = 800Ω are arranged as in the first embodiment. The device area could be reduced to 60%.
[0103]
In this embodiment, since the first resistors R1A to R1N are connected to one node between the input terminals, it is not necessary to integrate R2 and C2 with the transistor, and R2 is formed on the substrate outside the transistor chip. And C1 elements. In this case, the transistor chip area can be greatly reduced, and the chip area can be reduced to 40% of the case of the first embodiment.
[0104]
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Nor. For example, although the semiconductor amplifying element used for the amplifier is HBT in the embodiment, the present invention can be similarly applied to a silicon bipolar transistor, and the same effect can be obtained. The present invention can be applied to at least a high-frequency amplification technique.
[0105]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0106]
(1) It is possible to provide a wireless communication device that can suppress thermal runaway and has high efficiency and is less likely to cause an oscillation phenomenon.
[0107]
(2) Since the capacity value of the capacity to be used can be reduced, the semiconductor chip (semiconductor device) can be downsized and the manufacturing cost can be reduced.
[0108]
(3) The stability and efficiency of the wireless communication device can be improved by inserting and connecting an inductor to the base terminal and the emitter terminal.
[0109]
(4) Bias controllability can be improved by adopting a current mirror configuration.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a part of a wireless communication apparatus according to an embodiment (Embodiment 1) of the present invention.
FIG. 2 is a schematic perspective view showing a part of the wireless communication apparatus according to the first embodiment.
FIG. 3 shows a part of a semiconductor chip (semiconductor device) in which an amplifier including a multi-finger structure HBT incorporated in the wireless communication device of Embodiment 1 and a first capacitor, a first resistor, a second resistor, and the like is formed. It is a schematic plan view to show.
4 is a cross-sectional view taken along line AA ′ of FIG.
5 is a cross-sectional view taken along line BB ′ of FIG.
FIG. 6 is a graph showing a correlation between collector current and stabilization coefficient K.
FIG. 7 is a graph showing the correlation between input power and collector current and added efficiency.
FIG. 8 is a graph showing a correlation between input power (Pin) and collector current and load efficiency (PAE).
FIG. 9 is a graph showing a correlation between the first resistance R1, the stabilization coefficient K, and the load efficiency (PAE) in the difference between the total resistance (Rtotal) of the first resistance and the second resistance.
FIG. 10 is a block diagram showing a multistage high frequency power amplification module and the like in a wireless communication apparatus according to another embodiment (Embodiment 2) of the present invention.
FIG. 11 is a schematic plan view showing a layout of each electronic component of the high-frequency power amplification module according to the second embodiment.
FIG. 12 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (third embodiment) of the present invention.
FIG. 13 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 4) of the present invention.
FIG. 14 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 5) of the present invention.
FIG. 15 is a bias control circuit diagram of a high-frequency power amplification module incorporated in the wireless communication apparatus of the fifth embodiment.
FIG. 16 is a schematic plan view showing a layout of each electronic component of the high frequency power amplifier module according to the fifth embodiment.
FIG. 17 is a circuit diagram illustrating a part of a wireless communication apparatus according to another embodiment (sixth embodiment) of the present invention.
FIG. 18 is a circuit diagram showing a part of a wireless communication apparatus employing a conventional circuit.
FIG. 19 is a circuit diagram showing a part of a wireless communication apparatus employing a conventional circuit.
FIG. 20 is a circuit diagram showing a part of a wireless communication apparatus employing a conventional circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... High frequency power amplification module, 2 ... Antenna, 5 ... Emitter terminal, 6 ... Base terminal, 7 ... Collector terminal, 9 ... Matching circuit, 10 ... Wiring board, 11 ... Wiring, 12 ... Conductor, 14 ... Capacitance insulating film, DESCRIPTION OF SYMBOLS 15 ... Wiring metal, 16 ... Capacitor lower layer wiring metal, 19 ... Conductor, 20 ... Wiring, 21 ... Etching stopper, 22 ... Back electrode, 30 ... Semi-insulating GaAs substrate, 31 ... n ⁺ Type GaAs subcollector layer, 32... N type GaAs collector layer, 33... P ⁺ Type GaAs base layer, 34... N type InGaP emitter layer, 35... N ⁺ Type GaAs cap layer, 40 ... collector electrode, 41 ... base electrode, 42 ... emitter electrode, 45 ... insulating film, 50 ... base bias circuit, 51 ... wire, 55 ... body transistor, 56 ... current mirror diode (sensor diode) 57 ... Current mirror transistor (sensor transistor), C2A to C2N ... first capacitor, C1A to C1N ... second capacitor, GND ... second voltage terminal (emitter terminal), R1A to R1N ... first resistor, R2A to R2N ... second resistor, RFin ... input terminal, RFout ... output terminal, Vapc ... control terminal (base terminal), Vcc ... first voltage terminal (collector terminal).

Claims (23)

A wireless communication device having a high-frequency power amplification module at a transmission-side output stage and having an antenna connected to the high-frequency power amplification module,
The high frequency power amplification module includes:
An input terminal;
An output terminal;
A control terminal;
A first voltage terminal;
A second voltage terminal;
A high-power amplifier configured by connecting in parallel a plurality of transistors each including a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal;
A first capacitor disposed between the input terminal and the control terminal of each transistor, connected to the input terminal, and a first resistor connected in series to the first capacitor and connected to the control terminal;
A second resistor disposed between the control terminal and the control terminal of each transistor, and connected to a node between the first resistor and the first capacitor;
The output terminal is connected to each first terminal of the transistor;
The first voltage terminal is connected to the first terminal of each transistor;
The wireless communication device, wherein the second voltage terminal is a high frequency power amplification module connected to a second terminal of each transistor. A wireless communication device having a high-frequency power amplification module at a transmission-side output stage and having an antenna connected to the high-frequency power amplification module,
The high frequency power amplification module includes:
An input terminal;
An output terminal;
A control terminal;
A first voltage terminal;
A second voltage terminal;
A high-power amplifier configured by connecting in parallel a plurality of transistors each including a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal;
A first capacitor disposed between the input terminal and the control terminal of each transistor, connected to the input terminal, and a first resistor connected in series to the first capacitor and connected to the control terminal;
A second capacitor connected in parallel to the first resistor;
A second resistor disposed between the control terminal and the control terminal of each transistor, and connected to a node between the first resistor and the first capacitor;
The output terminal is connected to a first terminal of each transistor;
The first voltage terminal is connected to the first terminal of each transistor;
The wireless communication device, wherein the second voltage terminal is a high frequency power amplification module connected to a second terminal of each transistor. The DC voltage drop during the operation of each transistor is about 0.15 V or less, the resistance value of the first resistor is about 1Ω or less, and the capacitance value of the second capacitor is about 5 pF or less. The wireless communication apparatus according to claim 2. The high-frequency power amplification module has a multi-stage configuration in which a plurality of the high-power amplifiers are sequentially connected in cascade.
Each control terminal of the first stage high output amplifier is connected to the input terminal,
Each first terminal of the final stage high power amplifier is connected to the output terminal,
Each control terminal of the middle high-power amplifier is connected to the first terminal of the front-stage high-power amplifier, and each first terminal is connected to the control terminal of the rear-stage high-power amplifier,
The first capacitor, the first resistor, and the second resistor are incorporated in at least one high-power amplifier in the first stage, the middle stage, or the last stage;
2. The wireless communication apparatus according to claim 1, wherein a predetermined control voltage is applied to each control terminal of the high-power amplifier at each stage. The high-frequency power amplification module has a multi-stage configuration in which a plurality of the high-power amplifiers are sequentially connected in cascade.
Each control terminal of the first stage high output amplifier is connected to the input terminal,
Each first terminal of the final stage high power amplifier is connected to the output terminal,
Each control terminal of the middle high-power amplifier is connected to the first terminal of the front-stage high-power amplifier, and each first terminal is connected to the control terminal of the rear-stage high-power amplifier,
The first capacitor, the first resistor, the second resistor, and the second capacitor are incorporated in at least one high-power amplifier in the first stage, the middle stage, or the last stage,
4. The wireless communication apparatus according to claim 2, wherein a predetermined control voltage is applied to each control terminal of the high-power amplifier at each stage. The wireless communication apparatus according to claim 1, wherein an inductance is connected between the control terminal and the second resistor. The wireless communication apparatus according to claim 1, wherein an inductance is connected between the second voltage terminal and the second terminal. 3. The radio communication apparatus according to claim 1, wherein the transistors constituting the high-power amplifier are monolithically formed on a single semiconductor substrate. 9. The wireless communication apparatus according to claim 8, wherein a sensor transistor constituting a current mirror circuit is monolithically formed on the semiconductor substrate. 9. The wireless communication apparatus according to claim 8, wherein a sensor diode constituting a current mirror circuit is monolithically formed on the semiconductor substrate. A wireless communication device having a high-frequency power amplification module at a transmission-side output stage and having an antenna connected to the high-frequency power amplification module,
The high frequency power amplification module includes:
An input terminal;
An output terminal;
A control terminal;
A first voltage terminal;
A second voltage terminal;
A high-power amplifier configured by connecting in parallel a plurality of transistors each including a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal;
A first resistor connected to a control terminal of each transistor; a single second capacitor connected in series to each first resistor and connected to the input terminal; and connected in series to each first resistor. A single second resistor connected to the control terminal;
The output terminal is connected to a first terminal of each transistor;
The first voltage terminal is connected to the first terminal of each transistor;
The wireless communication device, wherein the second voltage terminal is a high frequency power amplification module connected to a second terminal of each transistor. 12. The plurality of transistors constituting the high-power amplifier are arranged so as to consist of one or a plurality of blocks, and each of the blocks has the first capacitor and the second resistor, respectively. Wireless communication device. The wireless communication apparatus according to claim 12, wherein a difference in heat radiation resistance between transistors in each block is smaller than heat radiation resistance of the high-power amplifier. The ratio of the heat dissipation thermal resistance of the high power amplifier to the deviation of the heat dissipation thermal resistance between the transistors in each block is the second resistance value with respect to the parallel resistance value of the first resistor connected in parallel for each block, and The wireless communication apparatus according to claim 13, wherein the wireless communication apparatus is about ½ or less of a ratio of a sum of parallel resistance values of the first resistors. An input terminal;
An output terminal;
A bias terminal;
A high-power amplifier configured by connecting in parallel a plurality of transistors each including a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal;
The first capacitors C2A to C2N and the first capacitors C2A to C2N, which are arranged between the input terminal and the control terminal of each transistor and connected to the input terminal, are connected in series to the control terminal. First resistors R1A to R1N
The first resistor R1A to R1N and the second resistor R2A to R2N connected to the node between the first capacitor C2A to C2N are disposed between the bias terminal and the control terminal of each transistor. ,
The output terminal is a semiconductor device connected to each first terminal of the transistor. 16. The semiconductor device according to claim 15, further comprising second capacitors C1A to C1N connected in parallel to the first resistors R1A to R1N. The terminal;
An output terminal;
A bias terminal;
A high-power amplifier configured by connecting in parallel a plurality of transistors each including a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal;
A single first capacitor C2 disposed between the input terminal and the control terminal of each transistor, connected to the input terminal, and connected in series to the first capacitor C2 and connected to the control terminal. First resistors R1A to R1N;
A single second resistor R2 disposed between the bias terminal and the control terminal of each transistor and connected to a node between the first resistors R1A to R1N and the first capacitor C2,
The output terminal is a semiconductor device connected to each first terminal of the transistor. 18. The semiconductor device according to claim 17, further comprising second capacitors C1A to C1N connected in parallel to the first resistors R1A to R1N. The DC voltage drop during the operation of each transistor is about 0.15 V or less, the resistance value of the first resistor is about 1Ω or less, and the capacitance value of the second capacitor is about 5 pF or less. The semiconductor device according to claim 15 or 17. 17. The semiconductor device according to claim 15, wherein a sensor circuit constituting a current mirror circuit is monolithically formed on a semiconductor substrate constituting the semiconductor device. 16. The plurality of transistors constituting the high-power amplifier are arranged so as to be composed of one or a plurality of blocks, and each of the blocks has the first capacitor and the second resistor, respectively. 16. The semiconductor device according to 16. The semiconductor device according to claim 21, wherein a difference in heat radiation thermal resistance between transistors in each block is smaller than that of the high power amplifier. The ratio of the heat dissipation thermal resistance of the high power amplifier to the deviation of the heat dissipation thermal resistance between the transistors in each block is the second resistance value with respect to the parallel resistance value of the first resistor connected in parallel for each block, and The semiconductor device according to claim 21, wherein the semiconductor device is about ½ or less of a ratio of a sum of parallel resistance values of the first resistors.

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