JP3853066B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device in which a plurality of memories are mixed in one chip.
[0002]
[Prior art]
In recent years, with the miniaturization of integrated circuits due to progress in semiconductor manufacturing technology, higher integration of semiconductor devices has been advanced. Against this background, semiconductor chips in which a plurality of memories are mixed (called “combo chips”) have been developed. As such a combo chip, there is a chip in which a plurality of memories having different address sizes are integrated on one chip as shown in FIG. The combo chip 100 includes a first memory 11 realized by a ROM (Read Only Memory), a second memory 12 realized by a RAM (Random Access Memory), and a control circuit 14. The first memory 11 inputs address signals A0, A1,..., An, An + 1,..., Am, and inputs or outputs data signals D0, D1,. The second memory 12 has an address size smaller than that of the first memory 11, inputs address signals A0, A1,..., An, and inputs or outputs data signals D0, D1,. The second memory 12, which is a rewritable memory, also receives a write enable signal WEB that controls whether to write or read. As shown in FIG. 5, the first memory 11 and the second memory 12 share the address signals A0, A1,..., An and the data signals D0, D1,. The control circuit 14 inputs a selection signal ACEB for selecting the first memory and a selection signal BCEB for selecting the second memory, and controls whether the first memory 11 is enabled or disabled. An activation signal CSMA and an activation signal CSMB for controlling whether the second memory 12 is enabled or disabled are output.
[0003]
When the second memory 12 having the smaller address size is selected from the two memories 11 and 12 built in the combo chip 100 shown in FIG. 5 (ACEB = “1”, BCEB = “0”) )), The address signals An + 1,..., Am out of the address signals A0, A1,..., An, An + 1,. These surplus address signals An + 1,..., Am are normally ignored. However, depending on the system using the combo chip 100 as described above, the surplus address signals An + 1,..., Am may be validated and used for predetermined processing. When the surplus address signal is invalidated or validated differs depending on the system using the combo chip as described above, the semiconductor manufacturer prepares two types of masks corresponding to invalidity and validity of the surplus address and manufactures them. By selecting and using any mask in the process, it is determined whether the surplus address is invalidated or validated.
[0004]
[Problems to be solved by the invention]
However, in the method of preparing two types of masks in the semiconductor manufacturing process as described above and separately creating chips according to the system in which the combo chip is used, the chip can be manufactured if the system is not determined. It cannot be done and it takes days to manufacture. Also, if a change occurs in the selection of whether to invalidate or enable the surplus address due to a change in the system that uses the chip, it cannot be dealt with immediately, and by the time the change occurs Chips that have been manufactured are wasted.
[0005]
The present invention has been made to solve the above problem, and it is not possible to determine whether or not to invalidate the surplus address, or whether or not to invalidate the surplus address by changing the system. An object of the present invention is to provide a semiconductor memory device capable of suppressing the time loss and the material loss as described above when the selection is changed.
[0006]
[Means for Solving the Problems]
Engaging Ru semiconductors storage device made the present invention in order to solve the above problems, than the first memory and the first memory-chip and the second memory address size is small, the second memory address signal In the semiconductor memory device shared with the first memory,
Control means for controlling whether the second memory is activated or deactivated by a surplus address signal which is an address signal not shared by the second memory among the address signals of the first memory ;
Control operation setting means capable of setting whether to enable or disable the operation of the control means;
Equipped with a,
The control unit activates or deactivates the second memory according to the surplus address signal when the setting of the control operation setting unit indicates that the operation of the control unit is to be enabled. If the setting of the control operation setting means indicates that the operation of the control means is invalidated, the second memory is activated or not in response to a selection signal from the outside. It is characterized by controlling whether to activate .
[0007]
Control written above operation setting means can be realized by providing a storage means for storing a signal value indicating the whether to enable or disable the operation of the control means. The storage means may be realized as a rewritable storage circuit such as a register, but may be realized by storing the signal value in a programmable ROM. Further, when at least one of the first and second memories is a ROM, the signal value may be stored in the storage means in the ROM code programming process for the ROM.
Further, the control operation setting means has a pad for setting whether to enable or disable the operation of the control means instead of having the storage means as described above, and performs wire bonding or wireless bonding. may be configured to a Rukoto is connected with the pad and a power supply line or ground line, Ru is set whether to enable or disable the operation of the control unit used.
[0008]
【The invention's effect】
According to the first semiconductor memory device of the present invention, whether or not to activate the second memory is controlled by the surplus address. This means that a chip select signal that has been conventionally generated outside the chip using the upper bits of the address can be generated inside the chip (semiconductor memory device). Further, in order to cope with various systems using the semiconductor memory device, activation control of the second memory by the surplus address can be used.
[0009]
Furthermore , it is possible to set whether to enable or disable the operation of the control means for controlling whether or not to activate the second memory by the surplus address. Therefore, the whether to enable or disable the activation control functions of the memory by such excess addresses, it is possible to set after manufacture of the semiconductor memory device (the second half step or later). Therefore, a semiconductor memory device can be manufactured even at a stage where it is not determined whether the activation control function based on the surplus address is valid or invalid, and the activation based on the surplus address can be achieved by changing the system using the semiconductor memory device. Even if there is a change in the validity / invalidity of the control function, it can be dealt with immediately, and the semiconductor memory device manufactured before the change is not wasted.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of a combo chip 110 which is a semiconductor memory device according to an embodiment (hereinafter referred to as “embodiment 1”) of the present invention. The basic configuration of the combo chip 110 according to the present embodiment is the same as that of the conventional combo chip 100 shown in FIG. 5, and includes a first memory 11 realized by ROM, a second memory 12 realized by RAM, and a control circuit. 14. The first memory 11 receives address signals A0, A1,..., An, An + 1,..., Am, and the second memory 12 receives address signals A0, A1,. Is similar to the combo chip 100 of FIG. 5 in that the address signals A0, A1,. Both memories 11 and 12 also share data signals D0 to Dk. However, the combo chip 110 of the present embodiment decodes the second memory 12 with the surplus address signals An + 1,..., Am, and controls whether to enable or disable the second memory 12. The second memory control circuit 16 for generating the digitized signal CSMB is provided, which is different from the combo chip 100 in FIG.
[0011]
In the combo chip 110, when the selection signal BCEB of the second memory 12 is “0” and the second memory 12 is selected, the second memory selection signal SMEB output from the control circuit 14 is “0”. . At this time, the second memory control circuit 16 uses the surplus address signal An + 1 that is not used as the address signal of the second memory 12 among the address signals A0, A1,..., An, An + 1,. ,..., Am are decoded, and the activation signal CSMB of the second memory is output as a decoding result. Therefore, when the second memory 12 is selected, whether the second memory 12 is enabled or disabled (whether it is activated or deactivated) is the surplus address An + 1,. Can be controlled by.
[0012]
In the conventional system having a plurality of memory chips, the chip select signal is generated using the upper bits of the address outside the chip. However, according to the combo chip 110 as described above, the second memory 12 is selected. In this case, a chip select signal can be generated inside the chip using the surplus address (the decoding operation using the surplus address signal corresponds to the generation of the chip select signal). Thus, by decoding the input of the surplus address and controlling the activation signal CSMB of the internal memory, a semiconductor chip that can be used in various systems can be realized. If the memory address space is not an integer power of 2, an address that does not exist in the corresponding memory area may be specified by the address signal. The activation signal CSMB is controlled in accordance with such an address. By doing so, it becomes possible to cope with various systems.
[0013]
<Embodiment 2>
FIG. 2 is a block diagram showing a configuration of a combo chip 120 which is a semiconductor memory device according to the second embodiment (hereinafter referred to as “embodiment 2”) of the present invention. Of the components of the combo chip 120 of the present embodiment, the same components as those of the above-mentioned combo chip 110 shown in FIG.
[0014]
Also in this embodiment, the second memory control circuit 18 activates the second memory 12 according to the surplus addresses An + 1,..., Am when the second memory 12 is selected (SMEB = “0”). (Hereinafter referred to as “activation control function by surplus address”). In the present embodiment, in addition to this, it is possible to set whether to enable or disable the activation control function based on the surplus address, and a storage circuit 20 is provided as a setting means for this purpose. The value stored in the storage circuit 20 is input to the second memory control circuit 18 as a signal ADSEL (hereinafter, this signal is referred to as an “activation control setting signal”), whereby the surplus address control by the second memory control circuit 18 is performed. Whether the function is enabled or disabled is controlled.
[0015]
FIG. 3 is a circuit diagram showing an internal configuration of the second memory control circuit 18. The second memory control circuit 18 is a surplus address signal An + 1,... That is not used as an address signal of the second memory 12 among the address signals A0, A1,..., An, An + 1,. , Am is generated as a surplus address decode signal ADE that becomes “0” only when the value is a predetermined value (in the example shown in FIG. 3, the surplus address signals An + 1,..., Am are all “0”). The surplus address decode signal ADE becomes “0”). Then, a signal ADENB is generated as a logical product of the surplus address decode signal ADE and the activation control setting signal ADSEL from the storage circuit 20, and a logical sum of the signal ADENB and the second memory selection signal SMEB from the control circuit 14 is generated. As a result, the activation signal CSMB of the second memory is generated.
[0016]
In the combo chip 120 configured as described above, when the activation control setting signal ADSEL is set to “1”, the surplus address signals An + 1,..., Am have a predetermined value (see FIG. 3). In the example shown, the ADE signal is “0” and the ADENB signal is “0” only when the surplus address signals An + 1,..., Am are all “0”. Therefore, if the second memory selection signal SMEB from the control circuit 14 is “0” at this time, the activation signal CSMB of the second memory is “0” (see FIG. 3). The activation signal CSMB is input to the second memory 12, and the second memory 12 is activated (is enabled). When the surplus address signals An + 1,..., Am are not the predetermined values, the ADE signal is “1” and the ADENB signal is “1”. Therefore, regardless of the second memory selection signal SMEB from the control circuit 14, The activation signal CSMB of the second memory becomes “1” (see FIG. 3), and the second memory 12 becomes inactive (disabled). As described above, when the activation control setting signal ADSEL is set to “1” and the second memory 12 is selected (SMEB = “0”), activation / deactivation of the second memory 12 is performed. It is determined by the surplus address signals An + 1,.
[0017]
On the other hand, when the activation control setting signal ADSEL is set to “0”, the activation control function based on the surplus address is invalidated, and the ADENB signal is “regardless of the surplus address signals An + 1,. 0 ". In this case, the activation signal CSMB of the second memory becomes “0” or “1” depending on whether the second memory selection signal SMEB from the control circuit 14 is “0” or “1”, and the second memory selection signal SMMB is changed accordingly. The memory 12 is enabled or disabled.
[0018]
The memory circuit 20 for setting the value of the activation control setting signal ADSEL may be realized as a rewritable register or the like, or may be realized by a programmable ROM (PROM). When realized as a PROM, for example, a value of the activation control setting signal ADSEL can be set by forming a fuse circuit and fusing the fuse portion with a high voltage or processing the fuse portion with a laser.
[0019]
When one of the first memory 11 and the second memory 12 in the combo chip 120 is realized by a ROM, the value of the activation control setting signal ADSEL is set in the memory circuit 20 in the ROM code programming step. It may be a simple configuration. In the PROM or ROM code programming process, the value of the activation control setting signal ADSEL cannot be changed once set. However, when a rewritable nonvolatile memory is used, the value of the activation control setting signal ADSEL is set. The setting contents can be maintained even if the power is cut off.
[0020]
Further, as shown in FIG. 4, a pad 101 to which a signal line for transmitting the activation control setting signal ADSEL to the second memory control circuit 18 is connected is provided, and the pad 101 and the pad 102 of the power supply line Vcc are connected. Alternatively, the value of the activation control setting signal ADSEL may be set by connecting either the pad or the pad 103 of the ground line GND by wire bonding. Furthermore, the pad 101 and the power supply line Vcc or the ground line GND may be connected by wireless bonding instead of wire bonding.
[0021]
According to the present embodiment as described above, the function for controlling the activation of the second memory 12 according to the surplus address An + 1,..., Am (activation control function by the surplus address) is validated or invalidated. Is set by the value stored in the memory circuit 20 (or wiring for the pad). Therefore, the activation control function can be set by the surplus address after the combo chip is manufactured (after the second half process). As a result, the combo chip can be manufactured even when it is not determined whether the surplus address is valid or invalid. Further, even if the surplus address is changed in validity / invalidity due to a change in the system using the chip, it can be dealt with immediately, and the chip manufactured before the change is not wasted.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a combo chip which is a semiconductor memory device according to an embodiment (Embodiment 1) of the present invention.
FIG. 2 is a block diagram showing a configuration of a combo chip which is a semiconductor memory device according to a second embodiment (Embodiment 2) of the present invention.
3 is a circuit diagram showing an internal configuration of a second memory control circuit in Embodiment 2. FIG.
FIG. 4 is a diagram showing an example of a means for setting a value of an activation control setting signal ADSEL in Embodiment 2.
FIG. 5 is a block diagram showing a configuration of a conventional combo chip.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... 1st memory 12 ... 2nd memory 14 ... Control circuit 16, 18 ... 2nd memory control circuit 20 ... Memory circuit 101 ... Pad 102 of activation control setting signal ADSEL ... Pad 103 of power supply line ... Pad 110 of ground line , 120 ... combo chip ADSEL ... activation control setting signals A0 to Am ... address signals An + 1 to Am ... surplus address signal CSMB ... second memory activation signal

Claims (5)

In a semiconductor memory device including a first memory and a second memory having an address size smaller than the first memory, and the second memory shares an address signal with the first memory,
Control means for controlling whether the second memory is activated or deactivated by a surplus address signal which is an address signal not shared by the second memory among the address signals of the first memory ;
Control operation setting means capable of setting whether to enable or disable the operation of the control means;
Equipped with a,
The control unit activates or deactivates the second memory according to the surplus address signal when the setting of the control operation setting unit indicates that the operation of the control unit is to be enabled. If the setting of the control operation setting means indicates that the operation of the control means is invalidated, the second memory is activated or not in response to a selection signal from the outside. A semiconductor memory device which controls whether to activate . The semiconductor memory device according to claim 1,
The semiconductor memory device according to claim 1, wherein the control operation setting unit includes a storage unit for storing a signal value indicating whether to enable or disable the operation of the control unit . The semiconductor memory device according to claim 2,
The said memory | storage means has programmable ROM, and memorize | stores the said signal value in this programmable ROM, The semiconductor memory device characterized by the above-mentioned . The semiconductor memory device according to claim 2 ,
At least one of the first and second memories is a ROM, and the storage means is configured to store the signal value in a ROM code programming process for the ROM . The semiconductor memory device according to claim 1 ,
The control operation setting means has a pad for setting whether to enable or disable the operation of the control means, and the pad is connected to the power supply line or the ground line using wire bonding or wireless bonding Thus, a setting for validating or invalidating the operation of the control means is performed .

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