JP3864488B2 - FFT device and power harmonic detection device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides an FFT (Fast Fourier Transform) device capable of executing a calculation every time one input value is sampled and continuously outputting the calculation result, and a voltage of an electric power system using the FFT device. Alternatively, the present invention relates to a device that detects harmonics contained in current at high speed.
[0002]
[Prior art]
Conventionally, in a power plant or a substation, when detecting a harmonic component of a voltage / current of an electric power system, an FFT capable of efficiently using a computer has been conventionally employed. FIG. 7 is an explanatory diagram showing a calculation procedure in the conventional FFT. In this example, 32 sampled input value sequences (1) are first input to the bit reverse processing unit (2), and the bit order is changed. Next, a butterfly operation is performed in the first butterfly stage (3). Subsequently, the butterfly operation is performed in sequence while being sent to the second, third, fourth, and fifth butterfly stages (4) to (7), and finally the output value sequence (8) is obtained. The butterfly calculation performed here will be described with reference to FIG. First, an operation of multiplying the input y by the complex number W ⁿ is performed, and the multiplication result W ⁿ · y is added to the input x. Next, after saving the obtained multiplication result W ⁿ · y and the input x in a register or the like, the addition result x + W ⁿ · y is overwritten at the memory address where x was written. Further, the saved multiplication result W ⁿ · y and the input x are read, and a value obtained by inverting the sign of W ⁿ · y is added to x. Next, x-W ⁿ · y of the obtained addition result is overwritten at the memory address where y was written.
[0003]
[Problems to be solved by the invention]
By the way, in recent years, power response measurement data having a wide dynamic range with respect to frequency has been demanded in real time when an accident occurs in order to recover and stabilize the power system after an accident.
Therefore, the following problems have occurred in the conventional detection device.
(1) In the conventional Fourier transform, rearrangement of input data (bit reverse processing) is required, so that the FFT operation can be started only after data of AC 1 cycle or more is collected. That is, the maximum delay is the time obtained by adding the FFT calculation time to one cycle. For this reason, it is necessary to have a faster calculation capability that can shorten the response time of the conventional method.
(2) Similarly, calculation with a finer pitch than one cycle was not possible with one FFT detector. Therefore, in order to detect at a pitch of 1 cycle or less, a method of preparing a plurality of FFT detectors and shifting the respective phases and calculating with a parallel circuit has been adopted. Therefore, conventionally, the configuration of the apparatus becomes expensive, and there has been a demand for the appearance of an apparatus that can be detected with a simpler configuration and a fine pitch.
[0004]
[Means for Solving the Problems]
Therefore, in order to solve the above-mentioned problem, the invention of the FFT apparatus according to claim 1 is based on 2 ^{N −1} signal values sent from the preceding stage, where the number of samplings is 2 ^N and the order of operation stages is n. executing the n sets of the butterfly operation by combining ^Nn times holding 2 ^n-1 pieces of signal values outputted from the delay element and 2 ^n-1 pieces of signal values into a delay element sent from the previous stage to be output from the N calculation stages each composed of a butterfly calculation unit are connected in a pipeline in order, and each time one sampling value is input to the first calculation stage, each calculation stage sequentially executes the butterfly calculation and obtains the calculation result. By sending to the subsequent stage, 2 ^N calculation results are output from the final calculation stage.
[0005]
According to a second aspect of the present invention, in the FFT apparatus of the first aspect, the butterfly computation unit of the final computation stage is a modified butterfly computation in which computation for calculating 2 ^N-1 computation results on the higher order side is omitted. Part.
[0006]
The invention of a power harmonic detection device according to claim 3 comprises means for sampling AC voltage or AC current of a power system inputted via an anti-aliasing filter at a constant period, and sampled AC voltage or AC current. The scalar quantity is calculated from the FFT device according to the invention of claim 1 or 2 inputted at every sampling timing, and the real and imaginary parts of the fundamental wave vector and the harmonic vector outputted from the FFT device. A scalar computing unit that calculates and outputs the power spectrum of the fundamental wave and the harmonic wave.
[0007]
A power harmonic detection device according to a fourth aspect of the present invention comprises means for sampling an AC voltage or an AC current of a power system inputted through an anti-aliasing filter at a constant period, and a sampled AC voltage or AC current. The FFT apparatus according to claim 1, wherein a value of is input at each sampling timing, a phase angle calculator that calculates a phase of a fundamental wave from a vector of the fundamental wave output from the FFT apparatus, and a phase angle Means for correcting a harmonic vector output from the FFT device to a phase vector based on the fundamental wave using the fundamental wave phase calculated by the computing unit.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of an embodiment of an FFT apparatus according to the first and second aspects of the present invention. In the figure, there are five calculation stages, and the first calculation stage includes a delay element 12 that holds a sampling value input via the signal line 11 and outputs it 16 times, and an input value and a delay element 12. And a butterfly operation unit 13 that executes a butterfly operation by combining the output values.
[0009]
Similarly, the second calculation stage includes a data bus 21 for capturing two calculation values output from the first stage butterfly calculation unit 13 and two calculation values input via the data bus 21. From the delay element 22 that is output after being held eight times, and the butterfly calculation unit 23 that executes the two butterfly calculations by combining the calculation value input via the data bus 21 and the output value from the delay element 22 It is configured. In other words, the nth operation stage has a data bus for fetching 2 ⁿ⁻¹ operation values output from the previous butterfly operation unit and 2 ⁿ⁻¹ signal values sent from the previous stage. ^5-n and delay elements to output the hold times, a combination of 2 ^n-1 pieces of the signal value and the 2 ^n-1 pieces of signal values outputted from the delay element sent from the previous stage and perform butterfly operation And a butterfly calculation unit for outputting 2 ⁿ calculation results to the subsequent stage.
[0010]
In the final fifth computation stage, the modified butterfly computation unit 53 that omits the computation for calculating the 16 computation results on the higher order side and outputs only the 16 computation results on the lower order side. It is configured. In this way, the illustrated FFT apparatus is pipeline-connected from the first operation stage to the fifth operation stage in order. Next, the operation of the FFT apparatus in FIG. 1 will be described. As the sampling value, for example, when the voltage or current value of the power system is sampled at regular intervals and inputted to the first calculation stage at the head through the signal line 11, the delay element 12 and the butterfly calculation unit 13, respectively. Is input.
[0011]
At the same time, the sampling value input 16 times before is output from the delay element 12 and input to the butterfly operation unit 13. The butterfly operation unit 13 executes the butterfly operation by combining the two input values, and outputs the obtained two operation results to the data bus 21 of the next second operation stage. Next, in the second calculation stage, when the calculation result from the first stage is input, the calculation result is input to the delay element 22 and the butterfly calculation unit 23, respectively. Pieces of calculation results are output and input to the butterfly calculation unit 23. The butterfly calculation unit 23 executes two sets of butterfly calculations by combining the four input values, and outputs the calculation results to the data bus 31 of the next third calculation stage.
[0012]
Thereafter, the third and fourth operation stages operate in the same manner, and the number of input operation results is doubled and output sequentially, and the final fifth operation stage has 16 operation results. Entered. When the sixteen computation results from the previous stage and the sixteen computation results output from the delay element 52 are input, the modified butterfly computation unit 53 of the fifth computation stage performs a modified butterfly computation by combining them. Execute and output only 16 calculation results on the fundamental wave side. That is, in the modified butterfly calculation unit 53, the calculation for calculating the 16 calculation results on the high-order side that is greatly affected by the aliasing noise is omitted.
[0013]
FIG. 2 is an explanatory diagram showing the operation of the modified butterfly computing unit 53 of FIG. The modified butterfly operation executed here is to calculate one output x + W ⁿ · y for two inputs x and y, and x−W ⁿ that has been executed in the conventional butterfly operation. The process for obtaining y is omitted. As a result, the processing for saving the multiplication result W ⁿ · y and the input x performed in the conventional normal butterfly operation in a register becomes unnecessary, and the obtained output x + W ⁿ · y is input as it is. It is possible to overwrite the memory address where x was stored. By omitting operations that are not valid in this way, this modified butterfly calculation has a calculation amount of about several tens of percent of the conventional butterfly calculation.
[0014]
FIG. 3 is a diagram showing a relationship between sampling value input and calculation timing in the FFT apparatus of FIG. An input signal consisting of a sine wave is sampled at a timing that divides one period (one wavelength) into 32 equal parts. These sampling values are input to the first first calculation stage and sequentially pipelined. After 32 samples are input for one period, every time one sampling value is input, FFT is performed on the 32 sampling values immediately before including the input value, and the fundamental wave is output from the final modified butterfly calculation unit 53. And harmonics are output. In this embodiment, the number of samplings is ^25, that is, 32. However, it is also possible to set the number of samplings to 8, 16, or the like.
[0015]
Next, an embodiment of a power harmonic detection device according to the invention of claim 3 will be described. FIG. 4 is a power system diagram showing a position where the power harmonic detection device of the embodiment is installed. In the figure, 61 is a power system bus (power transmission line), and a generator (or phase adjusting equipment) 65 is connected via a power receiving transformer 62. Further, on the secondary side of the power receiving transformer 62, the voltage / current detection which is the power harmonic detection device of the present invention is passed through the instrument transformer (PT) 63 and the instrument current transformer (CT) 64. A device 66 is connected. The voltage / current spectrum data 67 detected by the voltage / current detection device 66 is sent to the control device 68. The control device 68 sends a control command 69 to the generator (or the phase adjusting equipment) 65 based on the input voltage / current spectrum data 67.
[0016]
FIG. 5 is a block diagram showing a configuration of an embodiment of the power harmonic detection device according to the invention of claim 3. In the figure, when an AC input e is input to the A / D converter 72 via the anti-aliasing filter 71, the AC input e is sampled based on a trigger signal sent from the sampling timer 73 at a fixed period ts. Sampling data is input to the continuous FFT 74. This continuous FFT 74 is the FFT apparatus shown in FIG. 1, and outputs an output value sequence 75 composed of a real part Rn and an imaginary part In representing the power spectrum of the AC input e each time a sampling value is input. The output value sequence 75 is input to the scalar calculator 76, and the square root of the sum of the squares is calculated and output as a scalar An.
[0017]
From the above, the following effects are obtained in the above-described embodiment.
(1) Real-time: A harmonic power spectrum is calculated each time the input is sampled.
(2) Reduction of calculation load: The FFT calculation performed each time the input is sampled is less than half of the normal calculation amount.
(3) Simplification of calculation omission: Since the FFT calculation is pipelined, unnecessary calculation of harmonic orders can be eliminated, and the calculation burden can be further reduced.
[0018]
FIG. 6 is a block diagram showing a configuration of an embodiment of a power harmonic detection device according to the invention of claim 4. In the figure, when an AC input e is input to the A / D converter 82 via the anti-aliasing filter 81, the AC input e is sampled based on a trigger signal sent from the sampling timer 83 at a fixed period ts. Sampling data is input to the continuous FFT 84. This continuous FFT 84 is the FFT apparatus shown in FIG. 1, and each time a sampling value is input, an output value sequence 85 composed of a real part R1, an imaginary part I1, etc. representing the power spectrum of the fundamental wave of the AC input e. Is output. This output value sequence 85 is input to the reference phase angle calculator 86, calculates the reference phase angle θ from the ratio of the imaginary part I1 and the real part R1, and sends it to the phase angle corrector 87. The phase angle corrector 87 outputs a vector value obtained by correcting the phase angle of each harmonic based on the input phase θ of the fundamental wave.
[0019]
From the above, the following effects are obtained in the above-described embodiment.
(1) Real time: Every time the input is sampled, a harmonic vector based on the fundamental wave phase is calculated.
(2) Reduction of calculation load: The FFT calculation performed each time the input is sampled is less than half of the normal calculation amount.
(3) Simplification of calculation omission: Since the FFT calculation is pipelined, unnecessary calculation of harmonic orders can be eliminated, and the calculation burden can be further reduced.
[0020]
【The invention's effect】
As described above, according to the FFT apparatus of the first aspect of the present invention, since each arithmetic stage is provided with a delay element and connected in a pipeline, each arithmetic stage sequentially performs a butterfly calculation every time one sampling value is input. To obtain the calculation result from the final calculation stage. That is, the calculation result is always obtained in real time.
[0021]
According to the FFT apparatus of the second aspect of the present invention, the processing load on the butterfly computing unit is reduced by half by omitting the higher-order half butterfly computation in the butterfly computing unit of the final computation stage.
[0022]
According to the invention of the power harmonic detection device of claim 3, since the FFT device and the scalar calculator are provided, the power spectrum of the harmonic can be obtained in real time for every sampling.
[0023]
According to the power harmonic detection device of the fourth aspect of the present invention, it is provided with the FFT device, the phase angle calculator, and the vector correction means, so that the harmonics of the phase based on the fundamental wave in real time for every sampling. A vector is obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of an FFT apparatus according to claims 1 and 2 of the present invention;
FIG. 2 is an explanatory diagram illustrating an operation of a modified butterfly calculation unit in FIG. 1;
FIG. 3 is an explanatory diagram showing a relationship of calculation timings in FIG. 1;
FIG. 4 is a power system diagram showing an installation position of an embodiment of the power harmonic detection device according to the third and fourth aspects of the invention.
5 is a block diagram showing a configuration of an embodiment of a power harmonic detection device according to the invention of claim 3. FIG.
FIG. 6 is a block diagram showing a configuration of an embodiment of a power harmonic detection device according to the invention of claim 4;
FIG. 7 is an explanatory diagram showing a calculation procedure in a conventional FFT.
FIG. 8 is an explanatory diagram showing a butterfly operation in a conventional FFT.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Signal line 12 Delay element 13 Butterfly calculation part 21 Data bus 22 Delay element 23 Butterfly calculation part 31 Data bus 52 Delay element 53 Deformation butterfly calculation part 61 Electric power system bus (power transmission line)
62 Power transformer 63 Instrument transformer (PT)
64 Current Transformer for Instrument (CT)
65 Generator (or phase adjusting equipment)
66 Voltage / Current Detection Device 67 Voltage / Current Spectrum Data 68 Control Device 69 Control Command 71 Anti-Aliasing Filter 72 A / D Converter 73 Sampling Timer 74 Continuous FFT
75 Output value sequence 76 Scalar computing unit 81 Anti-aliasing filter 82 A / D converter 83 Sampling timer 84 Continuous FFT
85 Output value string 86 Reference phase angle calculator 87 Phase angle corrector

Claims (4)

Sampling number is 2 ^N , and the order of operation stages is n (n is an integer from 1 to N)
2 ^n-1 signal values sent from the previous stage are output after being held 2 ^Nn times, and 2 ^n-1 signal values sent from the previous stage are output from the delay element to 2 ^n-1 N stages of operation stages each composed of a butterfly operation unit that executes n butterfly operations by combining the signal values are sequentially pipelined,
Each time one sampling value is input to the first computation stage, each computation stage sequentially performs butterfly computation and sends the computation results to the subsequent stage, thereby outputting 2 ^N computation results from the final computation stage. FFT device. 2. The FFT apparatus according to claim 1, wherein the butterfly operation unit of the final operation stage is a modified butterfly operation unit in which an operation for calculating 2 ^N-1 operation results on the higher order side is omitted. FFT device. Means for sampling the AC voltage or AC current of the power system input through the anti-aliasing filter at a constant period;
The FFT apparatus according to claim 1 or 2, wherein a sampled AC voltage or AC current value is input at each sampling timing;
A scalar calculator that calculates a scalar quantity from the real part and imaginary part of the fundamental wave vector and the harmonic vector output from the FFT apparatus and outputs the power spectrum of the fundamental wave and the harmonic wave;
A power harmonic detection device comprising: Means for sampling the AC voltage or AC current of the power system input through the anti-aliasing filter at a constant period;
The FFT apparatus according to claim 1 or 2, wherein a sampled AC voltage or AC current value is input at each sampling timing;
A phase angle calculator that calculates the phase of the fundamental wave from the vector of the fundamental wave output from the FFT device;
Means for correcting a harmonic vector output from the FFT device to a phase vector based on the fundamental wave using the fundamental wave phase calculated by the phase angle calculator;
A power harmonic detection device comprising:

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