JP3920783B2 - Mask read-only memory manufacturing method and memory coding method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a mask read-only memory and a method for coding a memory. More specifically, the present invention relates to a method for manufacturing a mask read only memory (mask ROM).
[0002]
[Prior art]
  Mask read only memory (mask ROM) is a kind of non-volatile memory that retains data even when the power is turned off. Mask ROM is used in various computers and electronic devices because of its versatility. Conventionally, in order to shorten the delivery time, the embedded bit line and the word line are manufactured in advance as semi-finished products at the factory before receiving an order. When an order is placed, a photomask is produced according to the specifications and used to perform the coding process.
[0003]
  A typical coding process involves forming a photoresist layer on a substrate. Thereafter, the photoresist layer is exposed using a photomask manufactured according to specifications. After developing the exposed photoresist, a photoresist layer containing the coding holes is used as a mask for ion implantation. In this manner, ions are implanted into the area where the coding hole on the substrate is exposed, whereby the correct code is laid on the mask ROM.
[0004]
  Following the trend of miniaturization in recent years, mask ROMs are also required to achieve higher integration. However, as the device size on the chip is reduced and the device density is increased, many problems have arisen in the conventional mask ROM manufacturing method.
[0005]
  One problem with using a conventional mask ROM fabrication method is that alignment errors in patterning the photoresist layer can lead to misalignment of the coding holes. For this reason, the coding ions may be implanted not in the correct area but in an adjacent area, and as a result, a coding error may appear in the mask ROM at the product stage.
[0006]
  Another problem caused by using a conventional mask ROM manufacturing method is that variations in size and shape often occur in regions where coding holes are sparse due to the microloading effect caused by the difference in coding hole density. When such a state deteriorates, the coding holes may approach each other. Differences in the size and shape of the edge of the coding hole directly affect the position of the ion implantation region of the code, and thus can have a significant impact on the accuracy of the coding process.
[0007]
  In order to cope with the above problem, in many cases, a pattern on a photomask is corrected using a state-of-the-art processing facility. However, this method complicates the process and increases the manufacturing cost of the photomask. In addition, since the turnaround time (TAT) of the photomask becomes longer, the turnaround time of the mask ROM inevitably becomes longer.
[0008]
[Problems to be solved by the invention]
  Accordingly, one of the objects of the present invention is to provide a method of manufacturing a mask read only memory (mask ROM) that can prevent a problem caused by a coding hole being shifted from a predetermined coding region due to a coding mask arrangement error. Is to provide.
[0009]
  A second object of the present invention is to provide a mask read only memory (mask ROM) manufacturing method capable of preventing problems caused by coding hole size variations caused by a conventional coding mask manufacturing method. .
[0010]
  A third object of the present invention is to provide a method of manufacturing a mask read only memory (mask ROM) capable of realizing a higher degree of integration at a lower cost.
[0011]
  A fourth object of the present invention is to provide a method of manufacturing a mask read only memory (mask ROM) having a wider process window.
[0012]
  A fifth object of the present invention is to provide a method of manufacturing a mask read only memory (mask ROM) with a shorter turnaround time.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention of claim 1 includes: (A) preparing a substrate; (B) forming a gate insulating layer over the substrate; and (C) covering a plurality of conductive layers over the gate insulating layer. Forming a line; (D) performing ion implantation using the conductive line as a mask so that a buried bit line is formed in the substrate; (E) forming a first insulating layer between the conductive lines; (F) forming a conductive layer covering the substrate; (G) patterning the conductive layer and the conductive line to form a word line and a gate, wherein the word line is connected to the buried bit line; (H) an insulating material is deposited in the space between the word lines to form a second insulating layer; (I) a precoding layer is formed over the substrate; (J) the pre- Form multiple precoding holes in the coding layer In this case, the precoding hole is aligned with all the coding regions in the substrate under the gate; and (K) the etching rate is different from that of the precoding layer inside the precoding hole. Forming a filling layer; (L) forming a coding mask over the substrate; (M) at least within the coding mask corresponding to a location where ions are implanted by subsequent ion implantation in the coding region; One coding hole is formed, and at this time, at least a surface of the filling layer on the coding region at a position where the ions are implanted is exposed below the coding hole; and (N) the exposed filling layer Selectively removing with respect to the precoding layer; (P) the precoding hole remaining in the precoding layer and where no ions are implanted so that ions are implanted into the coding region through the precoding hole from which the filler layer has been removed. A method for producing a mask read-only memory, comprising the steps of performing ion implantation using the filling layer as a mask, and sequentially performing the steps (A) to (P). .
[0014]
  The invention of claim 2 is: (a) preparing a substrate; (b) forming a precoding mask layer covering the substrate; (c) forming a plurality of precoding holes in the precoding layer; Sometimes the precoding hole is aligned with all coding regions in the substrate; and (d) a filler layer is deposited in the precoding hole to form a filling layer having a different etching rate from the precoding layer. (E) forming a coding mask over the substrate; (f) at least one coding in the coding mask corresponding to a location where ions are implanted by subsequent ion implantation in the coding region. A hole is formed, and at this time, the ion is implanted below the coding hole. Exposing at least a surface of the filler layer on the coding region; (g) selectively removing the exposed filler layer with respect to the precoding layer; (h) removing the coding mask; (I) the precoding layer and the precoding remaining in a place where ions are not implanted so that ions are implanted into the coding region through a precoding hole from which the filling layer has been removed. A method of coding a memory, comprising: performing ion implantation using the filling layer in a hole as a mask, and performing the steps (a) to (i) in order.
[0015]
  In accordance with the objects of the present invention as embodied and broadly described below, and to achieve the above and other advantages, the present invention provides a method of fabricating a mask read only memory. Embedded bit lines are formed in the substrate, and gates and word lines are formed covering the substrate. Thereafter, a precoding layer including a plurality of precoding holes is formed to cover the substrate. The precoding hole is aligned with a plurality of coding regions in the substrate under the gate. A filler is deposited in the precoding hole to form a filler layer. A coding mask having a plurality of coding holes is then formed over the substrate. The filler in the precoding hole whose position coincides with the coding hole in the coding mask is removed. The coding mask is removed. Finally, coding ions are implanted using the precoding layer and the fill layer as a mask. Ions are driven into the coding area through the precoding holes.
[0016]
  According to the embodiment of the present invention, a high-precision process is applied to form a precoding hole in the precoding layer, while a low-precision process is used to form a coding hole in the coding mask. Yes. In addition, materials having different etching efficiencies are used for the precoding layer and the filling layer. The coding layer is manufactured using a material such as silicon oxide, silicon nitride, or metal. The filling layer is fabricated using a material such as spin-coated glass, metal, or silicon nitride. If the coding layer or filling layer is made of a metal material, the metal coding layer or filling layer must be removed after implantation of the coding ions. Furthermore, the filling layer in which the coding hole is exposed can be removed by performing a wet etching method.
[0017]
  Since the precoding layer and the filling layer are manufactured using materials having different etching efficiencies, the coding hole in the mask layer only needs to expose a part of the filling layer on a predetermined coding region. In the subsequent etching process, the filling layer on the predetermined coding region can be completely removed by selection. As described above, when the precoding holes in the precoding layer are accurately aligned with the coding region of the substrate, ions are automatically implanted into a predetermined coding region in the coding implantation process. In other words, when forming the pattern of the coding hole in the mask layer, even if there is a slight alignment error in the photolithography process and a microloading effect in the etching process, the coding hole is filled on the predetermined coding region. As long as a part of the substrate can be exposed, the etching selectivity of the filling layer and the precoding layer can be used to form a precoding hole having a uniform shape and size on the precoding region, and as a result. The implanted ions can self-align with the coding region.
[0018]
  Since the coding hole in the mask layer only needs to expose a part of the filling layer on a predetermined coding region, the processing window is enlarged, so that even a machine with slightly lower accuracy can be used for the coding process. In addition, a less sophisticated mask manufacturing technique can be used to form a photomask for forming a coding hole pattern, and the overall turnaround time (TAT) can be shortened. In addition, a low-precision photoresist can be used for forming the mask layer, and as a result, the manufacturing cost can be further reduced.
[0019]
  Furthermore, the precoding holes in the precoding layer have a uniform density. Therefore, less sophisticated mask fabrication techniques are sufficient to form a photomask for precoding hole patterning. In addition, the same precoding hole may be used regardless of the coding structure for the memory device. Therefore, the mask for forming the precoding hole can be applied to various types of products. Thus, in the manufacture of the mask ROM, an existing precoding mask can be used for pattern formation of the precoding layer. In other words, the present invention can reduce the overall manufacturing cost of the mask ROM, expand the processing window, and shorten the delivery time.
[0020]
  Both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
  A preferred embodiment of the present invention will be described in detail below. Examples are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the description and the illustration of the same or similar elements.
[0022]
  FIGS. 1 to 11 are schematic diagrams showing steps for manufacturing a mask ROM according to one embodiment of the present invention. As shown in FIG. 1, a gate insulating layer 102 and a plurality of conductive lines 104 are formed on a substrate 100. The gate insulating layer 102 is formed by, for example, thermal oxidation. The conductive line 104 is, for example, a doped polysilicon film formed by chemical vapor deposition. Thereafter, ion implantation 106 is performed using the conductive line 104 as a mask to form a plurality of embedded bit lines 108 in the substrate 100. For the ion implantation 106, for example, N type ions are used. FIG. 2 is a plan view of FIG.
[0023]
  As shown in FIG. 3, the insulating layer 110 is formed by attaching an insulating material to the space between the conductive lines 104. A conductive layer 112 is formed to cover the insulating layer 110 and the conductive line 104. The insulating layer 110 is formed, for example, by forming a silicon oxide film covering the entire substrate 100 and then performing back etching or chemical mechanical polishing on the oxide film to remove a part of the oxide film on the conductive line 104. This is a silicon oxide film. The conductive layer 112 is a composite layer including a polysilicon film and a metal silicon film formed by, for example, chemical vapor deposition.
[0024]
  Subsequently, photolithography and etching are performed, the conductive layer 112 is patterned on the word line 112a, the exposed conductive line 104 is removed, and the conductive line 104a below the word line 112a becomes a gate. An insulating layer 113 is formed by attaching an insulating material to the space between the word lines 112a. The insulating layer 113 is formed, for example, by depositing an oxide covering the entire substrate 100, and performing back etching or chemical mechanical polishing on the oxide film to remove a part of the oxide film on the word line 112a. This is a silicon oxide film. After these processing steps, the apparatus is in the state shown in the schematic cross-sectional view of FIG. 3 and the schematic plan view of FIG.
[0025]
  As shown in FIG. 5, a precoding layer 114 is formed to cover the word line 112 a and the insulating layer 113. A photoresist layer 116 is formed over the precoding layer 114, as shown in FIG. A photolithography process is performed to transfer the pattern on the photomask 118 to the photoresist layer 116. Subsequently, the precoding layer 114 is etched using the photoresist layer 116 as an etching mask to form a plurality of precoding holes 120 in the precoding layer 114a. The precoding hole 120 is aligned with the coding region 122 in the substrate 100. Since the precoding holes 120 in the precoding layer 114 a have a uniform density, a less sophisticated mask manufacturing technique can be applied to manufacture the photomask 118. In contrast, the precoding layer 114a is patterned with high accuracy. That is, more advanced equipment is used to expose the photoresist, and higher resolution photoresist material is used to form the photoresist layer 116. Furthermore, since the density of the coding holes in the memory region on the substrate 100 is uniform, the microloading effect does not occur in the process of forming the precoding holes 120 by etching. Accordingly, the shape and size of the precoding hole 120 are considerably uniform.
[0026]
  As shown in FIG. 7, a filling material is deposited in the precoding hole 120, and a filling layer 124 is formed at a position corresponding to the coding region 122 in the substrate 100. FIG. 8 is a plan view of the apparatus of FIG.
[0027]
  Since the filling layer 124 and the precoding layer 114a are made of different materials, the etching efficiency is different. The precoding layer 114a is made of a material such as silicon oxide, silicon nitride, or metal. On the other hand, the filling layer 124 is made of a material such as spin-coated glass, metal, or silicon oxide. For example, when the precoding layer 114a is a silicon oxide film or a silicon nitride film, the filling layer 124 is a spin-coated glass film or a metal film. The metal film includes a barrier layer made of titanium / titanium nitride and a tungsten layer. When the precoding layer 114a is a metal film, the filling layer 124 is a spin-coated glass film or a silicon oxide film.
[0028]
  As shown in FIG. 9, a mask layer 126 such as a photoresist layer is formed to cover the precoding layer 114 a and the filling layer 124. When photolithography is performed using the photomask 130, the pattern of the photomask 130 is transferred to the mask layer 126, and as a result, a code hole 128 is formed in the mask layer 126. The code hole 128 exposes the matching filling layer 124a in the precoding hole 120a. In other words, the code hole 128 exposes the filling layer 124a above the code region 122a. The pattern formation of the mask layer may be performed with low accuracy. For example, a low-precision photoresist material can be used to form the mask layer 126, and a less sophisticated mask manufacturing technique can be used to manufacture the photomask 130, and the exposure process can be performed. Equipment with low accuracy can be used.
[0029]
  As shown in FIG. 10, the filling layer 124a in the precoding hole 120a can be completely removed using the mask layer 126 as a mask. In other words, the filling layer 124a on the coding region 122a is completely removed. Since the precoding layer 114a and the filling layer 124a are made of materials having different etching efficiencies, the filling layer 124a can be removed using a selective isotropic etching method. Preferably, a wet etching process using a hydrofluoric acid solution as an etching solution is employed. After the filling layer 124a on the coding region 122a is completely removed, the substrate 100 is covered with the precoding layer 114a. The precoding hole 120 in the precoding layer 114a is in one or two states. The precoding hole 120 is either completely filled with filler, or there is no filler and therefore the underlying layer is exposed. All of these exposed coding holes 120 have the same size and shape.
[0030]
  As shown in FIG. 11, the mask layer 126 is removed. Subsequently, ion implantation 132 is performed using the precoding layer 114a and the filling layer 124 as a mask. The ions 134 are implanted into the coding region 122a through the precoding hole 120a from which the filling layer 124a has been removed. The ions implanted into the coding region 122a by the ion implantation 132 may be the same as or different from the ions existing in the buried bit line 108, and may be p-type ions, for example.
[0031]
  If the precoding layer 114a or the filling layer 124 is a metal film, the precoding layer 114a and the filling layer 124 must be removed after the ion implantation 132 is performed.
[0032]
  In summary, in the present invention, a photomask having a relatively high accuracy is used for patterning of the precoding hole array in the precoding layer, and a patterning of the coding hole array in the mask layer is relatively performed. Another photomask with low accuracy is used. Thereafter, using the mask layer as an etching mask, the filling layer in the precoding hole that matches the coding hole is removed. Finally, using the precoding layer and the filling layer as a mask, ions are implanted into the code region through a precoding hole in which ion implantation for coding is performed and the filler is removed in advance.
[0033]
  The precoding layer and the filling layer are made using materials having different etching efficiencies. Therefore, since the filling layer on the code region is selectively removed in a later etching step, the coding hole in the mask layer need only expose a part of the filling layer on the code region. Therefore, as long as the precoding holes in the precoding layer are accurately arranged in accordance with the code region in the substrate, ions implanted for coding perform self-alignment in accordance with the predetermined code region. In other words, when forming the pattern of the coding hole in the mask layer, even if there is a slight alignment error in the photolithography process and a microloading effect in the etching process, the coding hole is filled on the predetermined code region. As long as a part of the pattern is exposed, the etching selectivity between the filling layer and the precoding layer can be used to form a precoding hole having the same shape and size on the precoding region. In the subsequent ion implantation, the ions self-align with the code region.
[0034]
【The invention's effect】
  Since the coding hole in the mask layer only needs to expose a part of the filling layer on a predetermined coding region, the processing window is enlarged, so that even a machine with slightly lower accuracy can be used for the coding process. In addition, a less sophisticated mask manufacturing technique can be used to form a photomask for forming a coding hole pattern, and the overall turnaround time (TAT) can be shortened. In addition, a photoresist material with low accuracy can be used for forming the mask layer, and as a result, the manufacturing cost can be further reduced.
[0035]
  Furthermore, the precoding holes in the precoding layer have a uniform density. Therefore, less sophisticated mask fabrication techniques are sufficient to form a photomask for precoding hole patterning. In addition, the same precoding hole may be used regardless of the coding structure for the memory device. Therefore, high-precision photomasks can be applied to various types of products. Thus, in the manufacture of the mask ROM, an existing precoding mask can be used for pattern formation of the precoding layer. In other words, the present invention can reduce the overall manufacturing cost of the mask ROM, expand the processing window, and shorten the delivery time.
[0036]
  In short, the present invention provides a memory device that has higher integration, wider processing window, improved reliability, lower manufacturing cost and shorter turnaround time.
[0037]
  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view thereof, modifications and variations of the present invention are included in the scope of the present invention as long as they fall within the scope of the appended claims and equivalent descriptions.
[0038]
  The accompanying drawings are provided to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. Each drawing illustrates an embodiment of the present invention, and is for explaining the principle of the present invention together with the description of the text. The contents of each figure are as follows.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to an embodiment of the present invention.
2 is a plan view of FIG. 1. FIG.
FIG. 3 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
8 is a plan view of FIG. 7. FIG.
FIG. 9 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to an embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view of a substrate showing a process for manufacturing a mask ROM according to one embodiment of the present invention.
[Explanation of symbols]
100 substrates
102 Gate insulation layer
104 conductive wire
104a conductive wire
108 bit line
110 Insulating layer
112 Conductive layer
112a word line
113 Insulation layer
114 Precoding layer
114a Precoding layer
116 photoresist layer
118 photomask
120 precoding hole
120a precoding hole
122 coding region
122a coding region
124 packed bed
124a packed bed
126 Mask layer
128 code hole
130 Photomask
134 ions

Claims (2)

(A) preparing a substrate;
(B) forming a gate insulating layer over the substrate;
(C) forming a plurality of conductive lines covering the gate insulating layer;
(D) performing ion implantation using the conductive line as a mask so that a buried bit line is formed in the substrate;
(E) forming a first insulating layer between the conductive wires;
(F) forming a conductive layer covering the substrate;
(G) forming a word line and a gate by patterning the conductive layer and the conductive line, wherein the word line is perpendicular to the buried bit line;
(H) depositing an insulating material in the space between the word lines to form a second insulating layer ;
(I) forming a precoding layer over the substrate;
(J) forming a plurality of precoding holes in the precoding layer, wherein the precoding holes are aligned with all coding regions in the substrate under the gate;
(K) forming a filling layer having an etching rate different from that of the precoding layer inside the precoding hole;
(L) forming a coding mask over the substrate;
(M) At least one coding hole is formed in the coding mask corresponding to a position where ions are implanted by subsequent ion implantation in the coding region. At this time, the ions are formed below the coding hole. Exposing at least the surface of the filling layer on the coding region at the location of implantation;
(N) selectively removing the exposed filler layer with respect to the precoding layer ;
(O) removing the coding mask;
(P) The precoding layer and the filling layer in the precoding hole remaining in a place where ions are not implanted so that ions are implanted into the coding region through the precoding hole from which the filling layer has been removed. A method for manufacturing a mask read-only memory, comprising the steps of performing ion implantation using a mask and performing the steps (A) to (P) in order. (A) preparing a substrate;
(B) forming a precoding mask layer over the substrate;
(C) forming a plurality of precoding holes in the precoding layer, wherein the precoding holes are aligned with all coding regions in the substrate;
(D) depositing a filler in the precoding hole to form a filling layer having a different etching rate from the precoding layer;
(E) forming a coding mask over the substrate;
(F) At least one coding hole is formed in the coding mask corresponding to a position where ions are implanted by subsequent ion implantation in the coding region. At this time, the ions are formed below the coding hole. Exposing at least the surface of the filling layer on the coding region at the location of implantation;
(G) selectively removing the exposed filler layer with respect to the precoding layer ;
(H) removing the coding mask;
(I) so that ions are implanted into the coding region through a precoding hole the filling layer has been removed, the packed bed of the pre-coding holes remaining in place, wherein no implanted precoding layer and ion A method of coding a memory, comprising the step of performing ion implantation using a mask, wherein the steps (a) to (i) are sequentially performed.

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