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JP3929178B2 - IC mounting structure - Google Patents
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JP3929178B2 - IC mounting structure - Google Patents

IC mounting structure Download PDF

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Publication number
JP3929178B2
JP3929178B2 JP21514098A JP21514098A JP3929178B2 JP 3929178 B2 JP3929178 B2 JP 3929178B2 JP 21514098 A JP21514098 A JP 21514098A JP 21514098 A JP21514098 A JP 21514098A JP 3929178 B2 JP3929178 B2 JP 3929178B2
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JP
Japan
Prior art keywords
bump
chip
directional
mounting structure
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP21514098A
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Japanese (ja)
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JP2000049196A (en
Inventor
芳弘 石田
順生 井口
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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Priority to JP21514098A priority Critical patent/JP3929178B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)

Description

【0001】
【発明の属する技術分野】
本発明はICチップの実装構造に係わり、更に詳しくは突起電極を有するフリップチップ実装構造に関するものである。
【0002】
【従来の技術】
近年、半導体パッケージの小型化、高密度化に伴いベア・チップを直接フェイスダウンで、基板上に実装するフリップチップボンディングが開発されている。カメラ一体型VTRや携帯電話機等の登場により、ベア・チップと略同じ寸法の小型パッケージ、所謂CSP(チップサイズ/スケール・パッケージ)を載せた携帯機器が相次いで登場してきている。最近CSPの開発は急速に進み、その市場要求が本格化している。
【0003】
図5は、ICウエファー上に突起電極を製造する工程を示している。図5(a)のICウエファー製造工程では、ICウエファー8上に電気回路を形成し、外部接続用にボンディングパッド9を形成する。
【0004】
図5(b)に示すUBM(UnderBumpMetal)析出工程では、ICウエファー8のボンディングパッド9側に、電解バンプ析出用の共通電極とバンプとボンディングパッド9を接続するための金属であるUBM10を、スパッター等により析出させる。
【0005】
図5(c)に示すメッキレジスト形成工程では、UBM10上に電解バンプ析出用のメッキレジスト11をフォトリソ工程により形成する。
【0006】
図5(d)に示す半田メッキ工程では、メッキレジスト11の開口部に電気メッキ法により半田12を電解析出させる。
【0007】
図5(e)に示すレジスト剥離工程では、メッキレジスト11をレジスト剥離液により剥離する。
【0008】
図5(f)に示すUBMエッチィング工程では、半田12下のUBM10を残し、ICウエファー8上のUBM10をエッチィングにより除去する。
【0009】
図5(g)に示すリフロー工程では、半田12にフラックスを塗布し、リフローすることで、半田バンプ13を形成する。その後、フラックスを洗浄し、突起電極付ICウエファー14が完成する。
【0010】
図6にIC実装工程を示す。図6(a)の突起電極付ICウエファー製造工程は、図5で示した製造工程であり、突起電極付ICウエファー14を製造する。
【0011】
図6(b)に示すダイシング工程では、突起電極付ICウエファー14をダイシングソーで、個々の突起電極付ICチップ15に切断する。
【0012】
図6(c)に示すフラックス塗布工程では、突起電極付ICチップ15をフラックス槽に浸けてICチップ15の半田バンプ13上に、フラックス16を塗布する。
【0013】
図6(d)に示すプレースメント工程では、ICチップ15と回路基板5上のボンディングパターン2を認識し、ICチップ15の半田バンプ13をボンディングパターン2上に載置する。
【0014】
図6(e)に示すリフロー工程では、半田バンプ13をリフローすることで、ICチップ15を回路基板5に接続する。
【0015】
図6(f)に示す封止工程では、ICチップ15と回路基板5の空隙を封止樹脂4により封止する。こうして、IC実装基板17が完成する。
【0016】
図7は、従来のIC実装基板17のX線透過図を示す。ICチップ1上に半田バンプ13が対称に配置され、ボンディングされている。
【0017】
【発明が解決しようとする課題】
しかしながら、前述したIC実装構造には次のような問題点がある。即ち、IC実装後、ICが正常な方向を向いて、正しい位置にプレースメントされたかどうかを検査するには、ICチップは裏面が出ているため、外観では判別できない。ICをプレースメントした基板をX線透過させることで、バンプとボンディングパターンが判別できるが、半田バンプが対称に配列された場合、ICチップの方向性が判別できなくなる。そのため、判定には、電気検査をする必要があるので生産性が低く、コストアップ等の問題があった。
【0018】
本発明は、上記従来の課題に鑑みなされたものであり、その目的は、小型携帯機器等に搭載する信頼性及び生産性に優れたフリップチップ実装をにおいて容易なプレースメント判別法をもつIC実装構造を提供するものである。
【0019】
【課題を解決するための手段】
上記目的を達成するために、本発明におけるIC実装構造は、回路基板上のボンディングパターンと接続させるための接続用突起電極を有するICチップを回路基板にフリップチップ実装したIC実装構造において、前記ICチップの接続用突起電極形成面内に該ICチップの方向性を示す方向性突起電極を有すると共に、前記回路基板と接触しないように前記方向性突起電極の高さを前記接続用突起電極の高さよりも低く形成したことを特徴とするものである。
【0020】
また、前記方向性を示す方向性突起電極は、ICチップと電気的に接触していないこと
を特徴とするものである。
【0021】
また、前記方向性を示す方向性突起電極は、その根本形状が他の接続用突起電極とは形状が異なることを特徴とするものである。
【0023】
また、前記接続用突起電極と前記方向性突起電極の材料は、半田により形成したことを特徴とするものである。
【0024】
【発明の実施の形態】
以下図面に基づいて本発明におけるIC実装構造について説明する。図1は本発明の実施形態で、(a)は実装回路基板のX線投影図、(b)はバンプ断面図を示す図(a)のA−A′断面図である。図2は本発明の実施の形態で、方向性バンプの形状を示す説明図である。図3(a)、(b)および図4(a)、(b)は、方向性バンプの断面図で、バンプ高さを示す説明図である。従来技術と同一部材は同一符号で示す。
【0025】
図1(a)は、実装回路基板のX線透過図を示す。回路基板5に実装されたバンプの中で、方向性バンプ3は、他の半田バンプ13と比べ、その平面形状が異なるため、容易にチップの方向性が判断できる。また、回路基板5に接続しないため、回路基板5上には、対応するボンディングパターンが存在しない。
【0026】
図1(b)は、図1(a)のA−A′断面図である。方向性バンプ3の高さは、他の半田バンプ13より低いため、リフロー後も、回路基板5に接触しない。そのため、ICチップ1を回路基板5にプレースメントしたとき、方向性バンプ3が他の半田バンプ13よりも高くなって、半田バンプ13がボンディングパターンと接続できないという問題は発生しない。さらに、方向性バンプ3はICチップと電気的に独立していると同時に、回路基板5とも電気的に独立しているため、封止後も確実に絶縁され、信頼性上の問題も発生しない。
【0027】
図2は、方向性バンプの根本形状と半田バンプ形成時の上面図を示す。バンプ根本形状6を十字型にすることで、半田バンプ形状は円形とは異なる形状になる。通常半田バンプは円形をしているので、X線透過図において、どのバンプが、方向性バンプ3であるかは容易に判断でき、回路基板上に正常にプレースメントできたか容易に判断できる。
【0028】
図3は、電解半田メッキバンプにおける一般バンプと方向性バンプのバンプ高さを変える方法である。電気メッキにおけるメッキレジスト開口径を“一般バンプレジスト開口径(R)”>“方向性バンプレジスト開口径(r)”の関係にすることで、電気メッキ後の方向性バンプのメッキ量が少なくなる。この半田をリフローすることで形成される半田バンプ高さは“一般バンプ高さ(H)”>“方向性バンプ高さ(h)”の関係になる。バンプ材料に半田を使うことで容易にバンプ高さを変えることができる。
【0029】
図4は、無電解半田バンプにおける一般バンプと方向性バンプのバンプ高さを変える方法である。無電解バンプ形成法に、1個の半田ボール供給方法を考えた場合、供給半田量は同じである。レジスト開口径を“一般バンプ径(R)”<“方向性バンプ径(r)”の関係にし、リフローすることで形成される半田バンプ高さは“一般バンプ高さ(H)”>“方向性バンプ高さ(h)”の関係になる。バンプ材料に半田を使うことで容易にバンプ高さを変えることができる。
【0030】
【発明の効果】
以上説明したように、本発明のIC実装構造によれば、ICチップの接続用突起電極である一般バンプの形成面内に方向性突起電極を形成したことで、ボンディング時に容易に方向性の判定をすることが出来る。また、方向性突起電極である方向性バンプをICと電気的に接触させないことで、ICチップ内に自由に配置できる。また、この方向性バンプ形状を他のバンプと変えることで、容易に方向性を判定できる。また、この方向性バンプが、固定基板と接触しないことで、実装を容易に出来ると同時に、信頼性を向上できる。また、方向性バンプ材料と一般バンプ材料に半田を使うことで、容易に高さを変えることができる。
【図面の簡単な説明】
【図1】本発明の実施の形態に係わるIC実装構造を示す説明図である。
【図2】本発明の実施の形態に係わる方向性バンプの形状をを示す説明図である。
【図3】本発明の実施の形態に係わる電解バンプの高さを変える方法を示す説明図である。
【図4】本発明の実施の形態に係わる無電解バンプの高さを変える方法を示す説明図である。
【図5】ウエファーでの突起電極の製造方法を示す説明図である。
【図6】突起電極を回路基板に実装する方法を示す説明図である。
【図7】従来のIC実装基板のX線透過図である。
【符号の説明】
1 ICチップ
2 ボンディングパターン
3 方向性バンプ
4 封止樹脂
5 回路基板
6 バンプ根本形状
7 バンプ形状
8 ウエファー
9 ボンディングパッド
10 UBM
11 メッキレジスト
12 半田
13 半田バンプ
14 突起電極付ICウエファー
15 ICチップ
16 フラックス
17 IC実装基板
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC chip mounting structure, and more particularly to a flip chip mounting structure having protruding electrodes.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flip chip bonding has been developed in which a bare chip is directly mounted face-down on a substrate as semiconductor packages become smaller and higher in density. With the advent of camera-integrated VTRs, mobile phones, and the like, mobile devices on which small packages of approximately the same dimensions as bare chips, so-called CSP (chip size / scale packages), have appeared one after another. Recently, the development of CSP is progressing rapidly, and the market demand is in full swing.
[0003]
FIG. 5 shows a process of manufacturing the protruding electrode on the IC wafer. In the IC wafer manufacturing process of FIG. 5A, an electric circuit is formed on the IC wafer 8, and a bonding pad 9 is formed for external connection.
[0004]
In the UBM (UnderBumpMetal) deposition process shown in FIG. 5B, the UBM 10 which is a metal for connecting the common electrode for electrolytic bump deposition and the bump to the bonding pad 9 is sputtered on the bonding pad 9 side of the IC wafer 8. It precipitates by etc.
[0005]
In the plating resist forming process shown in FIG. 5C, a plating resist 11 for electrolytic bump deposition is formed on the UBM 10 by a photolithography process.
[0006]
In the solder plating process shown in FIG. 5D, the solder 12 is electrolytically deposited on the opening of the plating resist 11 by electroplating.
[0007]
In the resist stripping step shown in FIG. 5E, the plating resist 11 is stripped with a resist stripping solution.
[0008]
In the UBM etching process shown in FIG. 5F, the UBM 10 under the solder 12 is left and the UBM 10 on the IC wafer 8 is removed by etching.
[0009]
In the reflow process shown in FIG. 5G, a solder bump 13 is formed by applying a flux to the solder 12 and performing reflow. Thereafter, the flux is washed to complete the IC wafer 14 with protruding electrodes.
[0010]
FIG. 6 shows the IC mounting process. 6A is a manufacturing process shown in FIG. 5, and the IC wafer 14 with protruding electrodes is manufactured.
[0011]
In the dicing process shown in FIG. 6B, the IC wafer 14 with protruding electrodes is cut into individual IC chips 15 with protruding electrodes using a dicing saw.
[0012]
In the flux application process shown in FIG. 6C, the IC chip 15 with protruding electrodes 15 is immersed in a flux tank, and the flux 16 is applied onto the solder bumps 13 of the IC chip 15.
[0013]
In the placement step shown in FIG. 6D, the IC chip 15 and the bonding pattern 2 on the circuit board 5 are recognized, and the solder bumps 13 of the IC chip 15 are placed on the bonding pattern 2.
[0014]
In the reflow process shown in FIG. 6 (e), the IC chip 15 is connected to the circuit board 5 by reflowing the solder bumps 13.
[0015]
In the sealing step shown in FIG. 6 (f), the gap between the IC chip 15 and the circuit board 5 is sealed with the sealing resin 4. Thus, the IC mounting substrate 17 is completed.
[0016]
FIG. 7 shows an X-ray transmission diagram of the conventional IC mounting substrate 17. Solder bumps 13 are arranged symmetrically on the IC chip 1 and bonded.
[0017]
[Problems to be solved by the invention]
However, the above-described IC mounting structure has the following problems. That is, after the IC is mounted, in order to inspect whether the IC is oriented in the normal direction and placed in the correct position, the IC chip cannot be distinguished from the appearance because the back surface is exposed. Bumps and bonding patterns can be discriminated by transmitting X-rays through the substrate on which the IC is placed. However, if the solder bumps are arranged symmetrically, the directionality of the IC chip cannot be discriminated. For this reason, since it is necessary to conduct an electrical inspection for the determination, the productivity is low, and there are problems such as an increase in cost.
[0018]
The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an IC mounting having an easy placement discrimination method in flip chip mounting excellent in reliability and productivity mounted on a small portable device or the like. Provide structure.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, an IC mounting structure according to the present invention is an IC mounting structure in which an IC chip having a protruding electrode for connection for connecting to a bonding pattern on a circuit board is flip-chip mounted on the circuit board. A directional protruding electrode indicating the direction of the IC chip is provided in the connecting protruding electrode forming surface of the chip, and the height of the directional protruding electrode is set so as not to contact the circuit board. It is characterized by being formed lower than this.
[0020]
Further, the directional protruding electrode showing the directionality is not in electrical contact with the IC chip.
[0021]
Further, the directional protruding electrode exhibiting the directivity is characterized in that its root shape is different from that of the other connecting protruding electrodes.
[0023]
Further, the material of the connecting protruding electrode and the directional protruding electrode is formed of solder.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an IC mounting structure according to the present invention will be described with reference to the drawings. FIG. 1 is an embodiment of the present invention, in which FIG. 1A is an X-ray projection of a mounting circuit board, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. FIG. 2 is an explanatory view showing the shape of a directional bump in the embodiment of the present invention. FIGS. 3A and 3B and FIGS. 4A and 4B are cross-sectional views of directional bumps and are explanatory views showing bump heights. The same members as those in the prior art are denoted by the same reference numerals.
[0025]
FIG. 1A shows an X-ray transmission diagram of a mounted circuit board. Among the bumps mounted on the circuit board 5, the direction bump 3 has a planar shape different from that of the other solder bumps 13, so that the directionality of the chip can be easily determined. Further, since no connection is made to the circuit board 5, there is no corresponding bonding pattern on the circuit board 5.
[0026]
FIG.1 (b) is AA 'sectional drawing of Fig.1 (a). Since the height of the directional bump 3 is lower than that of the other solder bumps 13, it does not contact the circuit board 5 even after reflow. Therefore, when the IC chip 1 is placed on the circuit board 5, the directional bump 3 becomes higher than the other solder bumps 13, and the problem that the solder bumps 13 cannot be connected to the bonding pattern does not occur. Furthermore, since the directional bump 3 is electrically independent from the IC chip and also electrically independent from the circuit board 5, it is reliably insulated even after sealing, and no reliability problem occurs. .
[0027]
FIG. 2 shows the root shape of the directional bump and a top view when the solder bump is formed. By making the bump base shape 6 into a cross shape, the solder bump shape is different from the circular shape. Since the solder bumps are usually circular, it can be easily determined which bump is the directional bump 3 in the X-ray transmission diagram, and it can be easily determined whether or not the placement is normal on the circuit board.
[0028]
FIG. 3 shows a method of changing the bump height of the general bump and the directional bump in the electrolytic solder plating bump. By setting the plating resist opening diameter in electroplating to the relationship of “general bump resist opening diameter (R)”> “directional bump resist opening diameter (r)”, the amount of directional bump plating after electroplating is reduced. . The height of the solder bump formed by reflowing the solder has a relationship of “general bump height (H)”> “directional bump height (h)”. The bump height can be easily changed by using solder as the bump material.
[0029]
FIG. 4 shows a method of changing the bump height of the general bump and the directional bump in the electroless solder bump. When a single solder ball supply method is considered for the electroless bump formation method, the supplied solder amount is the same. The resist bump diameter is in the relationship of “general bump diameter (R)” <“directional bump diameter (r)”, and the solder bump height formed by reflow is “general bump height (H)”> “direction” Bump height (h) ". The bump height can be easily changed by using solder as the bump material.
[0030]
【The invention's effect】
As described above, according to the IC mounting structure of the present invention, the directional protrusion electrode is formed in the formation surface of the general bump which is the protruding electrode for connecting the IC chip, so that the directionality can be easily determined at the time of bonding. You can In addition, the directional bumps, which are directional protrusion electrodes, can be freely arranged in the IC chip by not electrically contacting the IC. In addition, the directionality can be easily determined by changing the shape of the directional bumps with other bumps. Further, since the directional bumps do not come into contact with the fixed substrate, the mounting can be facilitated and the reliability can be improved. Moreover, the height can be easily changed by using solder for the directional bump material and the general bump material .
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an IC mounting structure according to an embodiment of the present invention.
FIG. 2 is an explanatory view showing the shape of a directional bump according to an embodiment of the present invention.
FIG. 3 is an explanatory view showing a method of changing the height of the electrolytic bump according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram showing a method for changing the height of an electroless bump according to an embodiment of the present invention.
FIG. 5 is an explanatory view showing a method for manufacturing a bump electrode on a wafer.
FIG. 6 is an explanatory diagram showing a method of mounting a protruding electrode on a circuit board.
FIG. 7 is an X-ray transmission diagram of a conventional IC mounting substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 IC chip 2 Bonding pattern 3 Directional bump 4 Sealing resin 5 Circuit board 6 Bump root shape 7 Bump shape 8 Wafer 9 Bonding pad 10 UBM
11 Plating resist 12 Solder 13 Solder bump 14 IC wafer 15 with protruding electrodes IC chip 16 Flux 17 IC mounting substrate

Claims (4)

回路基板上のボンディングパターンと接続させるための接続用突起電極を有するICチップを回路基板にフリップチップ実装したIC実装構造において、前記ICチップの接続用突起電極形成面内に該ICチップの方向性を示す方向性突起電極を有すると共に、前記回路基板と接触しないように前記方向性突起電極の高さを前記接続用突起電極の高さよりも低く形成したことを特徴とするIC実装構造。 In an IC mounting structure in which an IC chip having a connection protruding electrode for connection with a bonding pattern on a circuit board is flip-chip mounted on the circuit board, the directionality of the IC chip is within the connection protrusion electrode forming surface of the IC chip. IC mounting structure characterized with, that the height of the directional protruding electrodes so as not to contact the circuit board and formed lower than the height of the connection protruding electrodes having a directional projection electrodes showing a. 前記方向性を示す方向性突起電極は、ICチップと電気的に接触していないことを特徴とする請求項1記載のIC実装構造。2. The IC mounting structure according to claim 1, wherein the directional protruding electrode indicating the directionality is not in electrical contact with the IC chip. 前記方向性を示す方向性突起電極は、その根本形状が他の接続用突起電極とは形状が異なることを特徴とする請求項1または2記載のIC実装構造。3. The IC mounting structure according to claim 1, wherein the directional protruding electrode showing the directionality has a root shape different from that of another connecting protruding electrode. 前記接続用突起電極と前記方向性突起電極の材料は、半田により形成したことを特徴とする請求項1から3のいずれか1項に記載のIC実装構造。Wherein the material of the connection protruding electrodes and the directional projection electrodes, IC mounting structure according to any one of claims 1 to 3, characterized in that formed by soldering.
JP21514098A 1998-07-30 1998-07-30 IC mounting structure Expired - Lifetime JP3929178B2 (en)

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