JP3949673B2 - Manufacturing method of liquid crystal display - Google Patents

Description

  The present invention relates to a method for manufacturing a liquid crystal display, and more particularly to a method for manufacturing a transflective or semi-reflective liquid crystal display.

  For a long time, liquid crystal displays have been widely applied to digital electronic products such as electronic watches and calculators. As thin film transistor and liquid crystal display technologies continue to develop and advance, their advantages such as small size, light weight, low drive voltage and low power consumption make notebook computers, personal digital processing systems and color televisions. It has been applied in large quantities to John and is gradually replacing the traditional cathode ray tube, which is a display. While thin film transistor and liquid crystal display designs have evolved toward larger sizes, many problems have been encountered in manufacturing and research and development. For example, the current product yield of thin film transistors and liquid crystal displays (TFT-LCDs) is still low, and the production capacity could not be increased effectively, so that the production cost could not be lowered.

  In general, a thin film transistor and a liquid crystal display (TFT-LCD) include a lower substrate formed by a thin film transistor (TFT) and a pixel electrode, and an upper substrate having a coloring filter. Liquid crystal is filled between the upper substrate and the lower substrate. When operating, a signal voltage is applied to the gate of the TFT, that is, applied to the switching element for each pixel unit, and when the TFT receives the signal voltage, it is turned on, and the data voltage having image information corresponds through the TFT. Applied on the pixel electrode and the liquid crystal. It should be noted here that when a data voltage is applied to the TFT, the alignment of the liquid crystal molecules changes, the optical characteristics change, and an image is displayed. In general, a voltage on a pixel electrode is applied to a corresponding TFT by a signal line, and the TFT performs switching control by a gate voltage provided via a gate line.

  In the prior art, in order to effectively reduce the cost required for the manufacturing process and the complicated manufacturing process and the time required for the process, the number of masks required is reduced by reducing the number of photolithography required during the design process. It was decreasing.

  In the prior art, when a TFT element and a peripheral complementary metal oxide semiconductor (CMOS) field effect transistor are simultaneously formed in a reflective or transmissive liquid crystal display, the process is completed by eight or more mask manufacturing processes. It was. Therefore, the manufacturing process is uneconomical and the cost for the mask is high.

  FIG. 1 shows the structure of a thin film transistor (TFT) element 200 and its CMOS peripheral control circuit 202. This is formed on a glass substrate 100, on which a TFT element 200 having a position and size defined by a photoresist and formed of a polysilicon thin film and an active area 101 of its CMOS peripheral control circuit 202 are formed. , 102, 103 are provided. The active regions 102 and 103 are used in subsequent manufacturing steps to form an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS) in CMOS, respectively. Thereafter, an insulating layer 104 is formed on the glass substrate 100 described above and covers the plurality of active regions 101, 102, 103. Subsequently, after the gate structure 106 is formed above the insulating layer 104 and the active regions 101, 102, 103, an n + doped polysilicon layer 108 is formed in each of the active regions 101, 102 by ion implantation, and active A P + doped polysilicon layer 110 is formed in the region 103, but a step of forming a lightly doped drain region (Lightly Doped Drain: LDD) 124 is performed before the step of forming the n + doped polysilicon layer 108. May be added. Thereafter, an interlayer dielectric layer 112 is formed on the upper surface of the insulating layer 104, and vias and contact windows are etched. At the same time, a metal layer is filled to form source / drain electrodes 114. Subsequently, a protective layer 116 is formed on the interlayer dielectric layer 112, and the protective layer 116 has a contact hole 120 through which the upper surface of the source / drain electrode 114 is exposed. Thereafter, an indium tin oxide (ITO) layer 122 serving as a pixel electrode is formed on the upper surface of the protective layer 116, and the source / drain electrodes 114 are connected. Finally, in the subsequent manufacturing process, the TFT element 200 and the source / drain electrodes of the CMOS peripheral control circuit 202 are connected.

  However, it should be noted here that, like the structure of the TFT element 200 and its CMOS peripheral control circuit 202 shown in FIG. This mask defines the gate structure 106, and the third mask defines the NMOS region and the TFT structure region in the CMOS control circuit 202, and at the same time, defines the lightly doped drain region 124. Subsequently, the fourth mask defines the n + doped polysilicon layer 108 and the fifth mask defines the PMOS region and p + doped polysilicon layer 110 in the CMOS control circuit 202. The sixth mask defines vias in the interlayer dielectric layer 112 and the seventh mask defines source and drain metal electrode patterning. The eighth mask defines the contact hole 120 on the protective layer 116 and the ninth mask defines the patterning of the indium tin oxide (ITO) layer 122 of the pixel electrode. Thus, the CMOS peripheral control circuit 202 and the TFT structure 200 as shown in FIG. 1 can be obtained. However, as many as nine mask manufacturing processes complicate the entire manufacturing process and require a relatively long process time.

  In view of the above-mentioned background of the invention, in the prior art, a TFT element and a CMOS peripheral control circuit were simultaneously formed in a reflective or transmissive liquid crystal display. However, in order to complete this, eight or more mask processes are generally required. Not only is this a necessary and uneconomical process, it also has the disadvantage that the mask is expensive. Therefore, a TFT element and its CMOS peripheral control circuit are formed at the same time, and the formed thin film transistor liquid crystal display has a transmission region and a reflection function at the same time, so that a part of incident light is transmitted through the transmission region and the remaining incident light There has been a demand for a more ideal method that does not require a large amount of mask manufacturing process, in which the light is reflected by the reflective region. And such a liquid crystal display still has the advantages of a reflective liquid crystal display even under circumstances where the surrounding light source is very weak.

A first object of the present invention is to provide a method of manufacturing a liquid crystal display device in which a TFT element and its CMOS peripheral control circuit are simultaneously formed using six masks.
A second object of the present invention is to provide a method of manufacturing a transmissive and reflective thin film transistor liquid crystal display using six masks.
It is a third object of the present invention to provide a manufacturing method for simultaneously forming a thin film transistor element and its CMOS peripheral control circuit, which can reduce manufacturing process time and cost.

  In order to achieve the above-described object, the method for manufacturing a liquid crystal display according to the present invention first forms a conductive layer on a substrate, forms a first metal layer on the conductive layer, and then concentrates on the first metal layer at a high concentration. Forming a doped layer, patterning the heavily doped layer, the first metal layer and the conductive layer, defining a peripheral control circuit region, a transistor region, a reflective region, a transmissive region and a capacitor region, and onto the substrate and the heavily doped layer; A semiconductor layer is formed, an insulating layer is formed on the semiconductor layer, the insulating layer, the semiconductor layer, and the heavily doped layer are patterned, a source / drain region and a channel region are defined, and the first metal layer is exposed. A resin layer is formed on the substrate, the first metal layer, and the insulating layer, and the resin layer is patterned to define the resin layer in a continuous non-planar reflective region. A thermal process is performed to melt a continuous non-planar surface to form a smooth surface, and a second metal layer is formed on the resin layer, the substrate, the first metal layer, and the insulating layer. The second metal layer is patterned to define a gate electrode, a reflective electrode, and a capacitor electrode. A patterned photoresist layer is formed on the gate structure, reflective electrode, substrate, first metal layer, capacitor electrode and insulating layer. Using the patterned photoresist layer as a mask, an ion implantation step is performed on the source / drain regions located in the peripheral control circuit region. The patterned photoresist layer is removed, a protective layer is formed on the gate structure, the reflective electrode, the substrate, the first metal layer, the capacitor electrode, and the insulating layer, and the protective layer is patterned to expose the transmissive region. Then, a part of the first metal layer is removed by etching to expose the conductive layer.

  The present invention has many advantages. First, the CMOS peripheral control circuit region 312, the thin film transistor region 314, and the capacitor region 340 can be simultaneously manufactured by the method provided by the present invention, and the number of masks used in the entire manufacturing process can be effectively reduced to six. Since the liquid crystal display formed by this method has a reflective region and a transmissive region at the same time, the light utilization is greatly improved. Further, the structure of the CMOS peripheral control circuit region 312 and the thin film transistor region 314 formed by the method of the present invention is completely defined by the first mask in this embodiment by the metal electrode of the source / drain structure, and the metal electrode Is located below the source / drain structure. In the subsequent manufacturing process of the data line, it is not necessary to perform etching of the contact window again, so that the complexity of the manufacturing process is effectively reduced, and the time and cost required for the process can be greatly reduced.

  Hereinafter, although one Example of this invention is described, it does not limit the thought and application range of this invention. Those skilled in the art can understand the idea of the present invention and then apply the method of the present invention to various liquid crystal displays to simultaneously form a thin film transistor and its CMOS peripheral control circuit. it can. The method and structure of the present invention can simultaneously form a thin film transistor and its CMOS peripheral control circuit using relatively few masks. When the method of the present invention is used, a liquid crystal display including transmissive and reflective thin film transistors is completed by the same mask manufacturing process, and a part of incident light is transmitted through the transmissive region, and the remaining incident light is reflected in the reflective region. Can be reflected. For this reason, the liquid crystal display manufactured by this manufacturing process can still have the advantages of the reflective liquid crystal display even in the situation where the surrounding light source is weak. Further, the application of the present invention is not limited to the most preferred embodiment described below.

  The present invention provides a method of simultaneously manufacturing a thin film transistor (TFT) and its CMOS peripheral control circuit. In this method, a necessary thin film transistor and its CMOS peripheral control circuit can be formed only by performing six photoresist manufacturing steps on the glass substrate. Therefore, not only the time required for the manufacturing process can be shortened, but also the cost for the manufacturing process can be effectively reduced. In addition, the present invention provides a new manufacturing process system. By this manufacturing process system, a thin film transistor liquid crystal display having a transmission region and a reflection function can be formed. Next, the present invention will be described in detail.

As shown in FIG. 2A, in a preferred embodiment, a transparent insulating substrate 300 is first formed of glass, quartz, or a similar material. In this embodiment, glass is used as the transparent insulating substrate 300, which is hereinafter referred to as the glass substrate 300. Subsequently, an indium tin oxide (ITO) thin film having a thickness of about 800 to 1100 mm is formed on the glass substrate 300 as a transparent conductive layer 302 by sputtering under an environment of about 25 to 100 ° C. . Subsequently, a metal layer 304 having a temperature of about 25 to 100 ° C. and a thickness of about 1000 to 8000 mm is formed to form an electrode having a subsequent source / drain structure. In general, the material of the metal layer 304 described above can be selected from chromium, tungsten, tantalum, titanium, molybdenum, aluminum, copper, an aluminum alloy, or any other combination. Thereafter, a heavily doped layer 306 is formed on the upper surface of the metal layer 304 to form source / drain regions necessary for the subsequent transistor region and the NMOS transistor in the CMOS peripheral control circuit region. The material of the above-described heavily doped layer 306 can be formed by selecting an n + doped silicon layer, and in the preferred embodiment, using chemical vapor deposition, the thickness is about 300- A 2000Å n + doped silicon layer is formed, the concentration of which is about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² .

Subsequently, as shown in FIG. 2B, a photolithography process is performed on the heavily doped layer 306 using the first mask, and the transmissive conductive layer 302, the metal layer 304, and a part of the heavily doped layer 306 are formed. The source / drain structure of the transistor (which may be a thin film transistor (TFT)) region 314 and the CMOS peripheral control circuit region 312 is defined on the glass substrate 300 at the same time, and at the same time, the reflective region 310 and the transmissive region 308 are formed in the subsequent manufacturing process. And a predetermined portion where the capacitor region 340 is formed is defined. In the preferred embodiment, the above-described steps are performed by dry etching or wet etching, but when wet etching is used, the etching solution may be a mixed solution of HCl and HNO ₃ or a mixed solution of HCl and FeCl ₂ .

  Next, as shown in FIG. 3A, a polysilicon thin film layer 316 is formed on the heavily doped layer 306 and the top surface of the glass substrate 300, and is required for the subsequent transistor region 314 and the CMOS peripheral control circuit region 312. Channel. In the preferred embodiment, the polysilicon thin film layer 316 is formed by first forming an amorphous silicon thin film having a thickness of about 500 to 600 on the upper surface of the heavily doped layer 306 and the glass substrate 300 by chemical vapor deposition (CVD). Then, the amorphous silicon thin film is converted into the polysilicon thin film 316 by a method in which energy is provided by thermal annealing and a laser. Subsequently, an insulating layer 318 is formed on the upper surface of the polysilicon thin film 316, and the insulating layer 318 is used as a gate insulating layer of a subsequent gate structure. The material may be silicon oxide, and in the preferred embodiment, plasma is used. Then, a chemical vapor deposition method (PECVD) is performed to form a silicon oxide film having a thickness of about 500 to 2000 mm.

  As shown in FIG. 3B, a photolithography process is performed using the second mask on the insulating layer 318, the polysilicon thin film layer 316, and the heavily doped layer 306, and the polysilicon thin film layer 316 and the insulating layer 318 are formed. Then, a part of the heavily doped layer 306 is etched away to define the gate / drain region 410, the channel region 420, and the gate insulating layer 430 in the transistor region 314 and the CMOS peripheral control circuit region 312. In the preferred embodiment, the polysilicon thin film 316 and the insulating layer 318 are etched by a dry etching method.

  As shown in FIG. 4A, a single resin layer (which may be a photosensitive material) 320 is applied over the entire surface of the glass substrate 300, the insulating layer 318, the metal layer 304, and the gate insulating layer 430. Subsequently, a photolithography process is performed using the third mask for the resin layer 320, and the resin layer 320 located on the reflective region 310 is etched to make the surface continuous uneven. At the same time, the resin layer 320 located in the transistor region 314, the CMOS peripheral control circuit region 312, the transmission region 308, and the capacitor region 340 is removed. Subsequently, as shown in FIG. 4B, the structure in which the photolithography process of the resin layer 320 is completed is put into a high temperature furnace (not shown), and a high temperature manufacturing process is performed at a temperature of 220 ° C. for 1 hour. The functional resin 320 is melted to form a smooth shape.

  As shown in FIGS. 5A and 5B, a metal layer 322 is formed on the upper surfaces of the resin layer 320, the insulating layer 318, and the gate insulating layer 430, and the metal layer 322 is used as the gate electrode 440. 450 and the metal layer 304 located in the capacitor region 340 form another metal electrode 460 of the capacitor two electrode. In general, the material of the metal layer 322 described above can be selected from an aluminum alloy such as a Mo—Al alloy or an Al—Nd alloy. Thereafter, a photolithography process is performed using the fourth mask to the metal layer 322, a part of the metal layer 322 is etched away, and the metal electrode 460 located in the gate structure 440, the reflective electrode 450, and the capacitor region 340 is defined. To do. Further, this metal layer 322 may be reserved in the CMOS transistor region, and may be a conductor between the PMOS transistor and the NMOS transistor. In the preferred embodiment, a dry etching photolithography process of the metal layer 322 is performed using a plasma gas formed of chloride.

As shown in FIG. 6, a photoresist layer 328 is applied over the entire surface. Subsequently, a photolithography process is performed using the fifth mask on the photoresist layer to expose the gate / transistor 410 of the PMOS transistor 402 in the CMOS peripheral control circuit region 312. Thereafter, using this patterned photoresist layer 328 as a mask, P-type ions in the PMOS transistor gate / drain region 410 are implanted in the direction indicated by the arrow 330, and the gate / source originally formed by the n + doped silicon layer is implanted. The drain region 410 becomes a P + doped region. According to a preferred embodiment of the present invention, the amount of ion implanter is about 10 ¹⁷ / cm ² and the implantation energy used is about 60-70 Kev.

As shown in FIG. 7A, after implanting P-type ions in the PMOS transistor source / drain region 410, the photoresist layer 328 is removed, and the transistor region 314, the CMOS peripheral control circuit region 312, the reflective region 310, and the glass substrate 300 are removed. A protective layer 332 is formed. The material of the protective layer 332 is selected from common dielectric materials such as nitride layers, oxide layers, organic materials, or any combination thereof. In a preferred embodiment of the present invention, a chemical vapor deposition method (PECVD) is performed using plasma, and a silicon oxide or silicon nitride layer having a thickness of about 3000 to 4000 mm in an environment at a temperature of about 330 ° C. Form. The reaction gas used in the manufacturing process includes SiH ₄ , N ₂ O, NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ , N ₂ O. Subsequently, the protective layer 332 is etched using the sixth mask to define the patterning of the protective layer 332 and to expose the transmissive region 308. In a preferred embodiment of the present invention, when the protective layer 332 is composed of a silicon nitride layer, the etching formulation is selected from CF ₄ / H ₂ , CHF ₃ or CH ₃ CHF ₂ .

  As shown in FIG. 7B, the transmissive region 308 in this preferred embodiment is etched by etching the metal layer 304 by dry etching or wet etching to expose the transmissive conductive layer 302 (which may be an ITO layer). Let Thereafter, in this embodiment, a partial liquid crystal display structure having a transistor region 314, a CMOS peripheral control circuit region 312, a reflective region 310, a transmissive region 308, and a capacitor 340 is formed at the same time, and a partial side view thereof is shown in FIG. 7B. . The pixel electrode in the thin film transistor region 314 simultaneously controls the reflective region 310 and the transmissive region 308, which simultaneously has a transmissive and reflective function, with some incident light being transmitted through the transmissive region 308 and the rest Since the incident light is reflected by the reflection region 310, the light utilization rate is increased.

  On the other hand, since the CMOS control circuit region 312 is also formed on the glass substrate 300 at the same time, the connection between the CMOS control circuit region 312 and the thin film transistor region 314 can be easily performed in the subsequent manufacturing process. The alignment between the circuit region 312 and the thin film transistor region 314 is completed.

  It should be noted here that the transparent conductive layer 302 is buried in the lowermost layer, and a metal layer 304 and a heavily doped layer 306 having a transistor source / drain structure are sequentially formed thereon. Therefore, when the heavily doped layer 306 is used as data lines, it is not necessary to etch the metal electrode contact window of the gate / drain structure in the protective layer 332. Since the metal electrode is defined in the first mask of the present invention, the transmissive conductive layer 302 can be used as a data line. Therefore, the present invention has convenience when connecting subsequent data lines.

  In the present invention, preferred embodiments have been disclosed as described above. However, these embodiments are not intended to limit the present invention, and any person who is familiar with the technology can use various embodiments within the scope and spirit of the present invention. Fluctuations and hydration can be added. Therefore, the scope of protection of the present invention is based on the contents specified in the claims.

It is sectional drawing of the insulation permeation | transmission board | substrate which shows the structure of the thin-film transistor formed by the prior art, and its CMOS periphery control circuit. It is sectional drawing of the insulated transmission board | substrate which shows the step which forms a transparent conductive layer, a metal layer, and a high concentration doped layer in order on the insulated transmission board by one Example of this invention. FIG. 3 is a cross-sectional view of an insulating transmissive substrate illustrating a step of etching a transmissive conductive layer, a metal layer, and a heavily doped layer according to an embodiment of the present invention. It is sectional drawing of the insulated transmissive board | substrate which shows the step which forms the polysilicon thin film layer and insulating layer by one Example of this invention. 4 is a cross-sectional view of an insulating transmissive substrate illustrating steps of etching a polysilicon thin film layer, an insulating layer, and a heavily doped layer according to an embodiment of the present invention. FIG. It is sectional drawing of the insulated transmissive board | substrate which shows the step which apply | coats the resin layer by one Example of this invention. It is sectional drawing of the insulated transmissive board | substrate which shows the step which forms the resin layer which has a smooth surface after heating the resin layer by one Example of this invention. It is sectional drawing of the insulated transmissive board | substrate which shows the step which forms the gate electrode and reflective electrode by one Example of this invention. 1 is a cross-sectional view of an insulating transmissive substrate illustrating the formation of a TFT structure according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an insulating transmissive substrate illustrating formation of source / drain regions of a PMOS transistor by implanting ions according to an embodiment of the present invention. It is sectional drawing of the insulation permeation | transmission board | substrate which shows formation of the protective layer by one Example of this invention. FIG. 3 is a cross-sectional view of an insulating transmissive substrate illustrating a step of removing a part of a metal layer located in a transmissive region and exposing a transmissive conductive layer according to an embodiment of the present invention.

Explanation of symbols

  300 transparent insulating substrate, 302 transparent conductive layer, 304 metal layer, 306 heavily doped layer, 308 transparent region, 310 reflective region, 312 CMOS peripheral control circuit region, 314 transistor region, 316 polysilicon thin film layer, 318 insulating layer, 320 Resin layer, 322 metal layer, 324 gate electrode, 326 reflective electrode, 328 photoresist layer, 330 arrow, 332 protective layer, 400 NMOS transistor, 402 PMOS transistor, 410 gate / drain region, 420 channel region, 430 reflective electrode, 460 Metal electrode

Claims (6)

Preparing a substrate;
Forming a conductive layer on the substrate;
Forming a first metal layer on the conductive layer;
Forming a heavily doped layer on the first metal layer;
Patterning the heavily doped layer, the first metal layer and the conductive layer to define a peripheral control circuit region, a transistor region, a reflective region, a transmissive region and a capacitor region;
Forming a semiconductor layer on the substrate and the heavily doped layer;
Forming an insulating layer on the semiconductor layer;
Patterning the insulating layer, the semiconductor layer, and the heavily doped layer to define source / drain regions and channel regions, and exposing the first metal layer;
Forming a resin layer on the substrate, the first metal layer and the insulating layer;
Patterning the resin layer to define a continuous non-flat surface in the reflective region of the resin layer;
Performing a thermal process to melt the continuous uneven surface to form a smooth surface;
Forming a second metal layer on the resin layer, the substrate, the first metal layer and the insulating layer;
Patterning the second metal layer to define a gate structure, a reflective electrode and a capacitor electrode;
Forming a patterned photoresist layer on the gate structure, the reflective electrode, the substrate, the first metal layer, the capacitor electrode and the insulating layer;
Performing an ion implantation step on the source / drain regions located in the peripheral control circuit region using the patterned photoresist layer as a mask;
Removing the patterned photoresist layer;
Forming a protective layer on the gate structure, the reflective electrode, the substrate, the first metal layer, the capacitor electrode, and the insulating layer;
Patterning the protective layer to expose the transmissive region;
Etching away a portion of the first metal layer to expose the conductive layer;
A method for producing a liquid crystal display, comprising:   2. The method of manufacturing a liquid crystal display according to claim 1, wherein the heavily doped layer has N-type doped ions, and the ion implantation step is P-type doped ion implantation.   2. The method of manufacturing a liquid crystal display according to claim 1, wherein the heavily doped layer has a thickness of 300 to 2000 mm, and the insulating layer has a thickness of 500 to 2000 mm.   2. The method of manufacturing a liquid crystal display according to claim 1, wherein the semiconductor layer has a thickness of 500 to 600 mm.   2. The method of manufacturing a liquid crystal display according to claim 1, wherein the heating step is performed at a temperature of 220 [deg.] C. for 1 hour.   2. The method of manufacturing a liquid crystal display according to claim 1, wherein the material of the second metal layer is selected from a Mo-Al alloy or an Al-Nd alloy.

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