JP3955360B2 - Reticle wiring pattern manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention Reticle wiring pattern In particular, it is possible to planarize the surface suitable for use in a semiconductor device having a multilayer wiring structure. Reticle Wiring pattern It relates to the manufacturing method.
[0002]
[Prior art]
Conventionally, a wiring for connecting each element of a semiconductor device is provided with a plurality of diffusion layer regions 12 serving as sources and drains on a semiconductor substrate 10 as shown in an example of a MOS transistor in FIG. The first layer metal wiring 20 made of aluminum or the like is used via the contact hole 17 therebetween. The metal wiring layer varies depending on the arrangement state of each element. In FIG. 24, a lower layer wiring 18 such as a polysilicon gate is also provided.
[0003]
In this case, as is well known, the flatness of the wiring interlayer film with respect to the lower wiring layer depends on the wiring width and the wiring interval of the lower layer wiring 18 and the like, and particularly depends on the wiring interval. Therefore, when it is assumed that various wiring intervals are generated inside the semiconductor device, there has been a problem that conditions and methods for forming an interlayer film become complicated.
[0004]
In order to solve such a problem, as shown in FIG. 25, electrically independent dummy wirings 21 are provided at wide wiring intervals. By forming the dummy wiring 21 as described above, the wiring interval can be narrowed, and the conditions and method for forming the interlayer film can be simplified as compared with the case without the dummy wiring.
[0005]
However, in the conventional method in which the dummy wiring 21 independent of the normal wiring 20 is provided, if the interval between the normal wirings 20 is not larger than the interval at which the dummy wiring with the minimum wiring width allowed in the process can be arranged, the dummy wiring is inserted. Had the problem of not being able to.
[0006]
That is, as shown in FIG. 26, if the interval between the normal wirings 20 is 2S + L (where S is the minimum wiring interval allowed by the wiring rule, L is also the minimum wiring width), the width is L + α of L or more. The dummy wiring 21 can be inserted. However, as shown in FIG. 27, if the interval between the regular wirings 20 is less than 2S + L, the width of the dummy wiring 21 becomes L−α less than the minimum wiring width L, which violates the design rule. The dummy wiring 21 was erased and the dummy wiring 21 could not be left.
[0007]
As described above, the flattening of the wiring interlayer film depends on the wiring interval. For example, as shown in FIG. 28, as an interlayer film between the lower layer wiring 18 and the wiring 20, a general SOG (Spin On When the coating film 34 by Glass) is sandwiched between the CVD (Chemical Vapor Deposition) oxide films 36, there is an optimum wiring interval for flattening the interlayer film by filling the recesses with the coating film 34. As described above, if there is a wiring interval in which the dummy wiring cannot be inserted, the interlayer film cannot be sufficiently flattened.
[0008]
In addition, with the high integration of LSI (Large Scale Integrated circuit), the miniaturization of wiring and the multilayering of wiring are progressing. In order to realize finer and multi-layered wiring, it is necessary to ensure the depth of focus when exposing the resist pattern in the patterning process of the wiring with a reticle. Therefore, flattening in each layer is important. ing.
[0009]
One method for planarizing each layer is a chemical mechanical polishing (CMP) method, in which an oxide film is formed on a formed wiring, and then a step portion is polished and flattened, so-called CMP (Chemical Mechanical Polishing). There is a law and it is widely used.
[0010]
This CMP method will be described with reference to FIGS. It is assumed that an interlayer insulating film 16 and a metal wiring 20 formed thereon are formed in advance by a normal method on a semiconductor substrate 10 such as a silicon substrate. From this state, first, as shown in FIG. 29, in a subsequent process of the metal wiring 20, between the metal wirings 20 and between upper layer wirings (not shown) formed on the metal wirings 20 are insulated. An insulating film 22 is formed. Next, the surface of the insulating film 22 is chemically and mechanically polished by CMP to form a flat interlayer film as shown in FIG.
[0011]
When the insulating film 22 is formed in the process of the CMP method, the metal wiring 20 is formed so as to have a necessary insulating film thickness between the lowest surface level portion 22l of the insulating film 22 and the upper wiring (not shown). It is necessary to make it relatively higher than the surface position 20u. There are three methods for this purpose.
[0012]
A. Film formation is performed using a high-density plasma CVD method, which is a film formation method with excellent embedding between wirings.
[0013]
B. For example, the wiring is embedded with SOG or the like.
[0014]
C. A thick film is formed by the normal CVD method until the wiring is buried.
[0015]
However, the high-density plasma CVD method used in the method A is the latest technology at present, and it is necessary to introduce a new apparatus. In the method B, since the film quality of the embedding material used in SOG is poor and the insulating property is low, it is necessary to have a sandwich structure in which the upper and lower surfaces of the embedding material are sandwiched between materials having good insulating properties, and the number of processing steps is increased by three steps End up. Therefore, the C method is often selected, but even with this C method, in the film formation method with poor coverage that does not reflect the step of the base, as shown in FIG. 31, an overhang is formed at the upper part between the wirings. Since a void 38 is generated in this case, when polishing is performed to the level of the broken line A by the CMP method, a recess 22r is formed on the flat surface.
[0016]
In order to prevent this, it is necessary to use a film forming method with good coverage such as a TEOS-based P-CVD method. However, when there is a wide portion of about 2 to 5 μm in the wiring interval, the thickness B of the insulating film 22 deposited on the wiring 20 and the thickness C of the insulating film 22 deposited between the wirings as shown in FIG. Since the ratio (film formation ratio) is about 5 to 3, for example, when the step due to the wiring thickness (referred to as a wiring step) is 5000 mm, and it is desired to leave an insulating film thickness of 5000 mm on the wiring after the CMP process, The insulating film on the top
17000Å = (5000Å + 5000Å) × 5 ÷ 3
The film is formed to be fairly thick, and then the CMP method is used.
12000? = 17000? -5000?
It is necessary to polish to a certain extent, resulting in a large loss in apparatus throughput and manufacturing costs.
[0017]
In order to prevent this, a dummy pattern is arranged between the metal wirings 20 to narrow the space between the wirings, and the wirings are filled by film growth from the wiring side walls 20s, and the insulating film thickness required before CMP is reduced. Has been made. However, even in this method, as shown in FIG. 32, the film forming ratio on the wiring side wall 20s is quite low, for example, B: D = 5: 2, so that the wirings arranged in parallel as shown in FIG. A slight increase in the wiring interval, which occurs when the 20 is bent, etc., leads to a thickening of the insulating film before CMP, resulting in a decrease in throughput and an increase in manufacturing cost. It was. In the example of FIG. 33, the wiring interval of the straight wiring portion is 1.2 μm, but the wiring bend is spread to 1.2√2 μm.
[0018]
In the wiring pattern of FIG. 33, consider a case where a flat insulating film is formed with a wiring level difference of 6000 mm and a minimum insulating film thickness of 7000 mm between the upper layer wiring. It is assumed that an interlayer insulating film 16 and a metal wiring 20 having a thickness of 6000 mm formed thereon are previously formed on a silicon substrate (not shown) by a normal method using the pattern of FIG. At this time, a cross-sectional view taken along line EE in FIG. 33, which is the widest wiring interval in the pattern, is as shown in FIG. From this state, the insulating film 22 that insulates from the upper wiring is formed using a P-TEOS CVD apparatus that is an insulating film forming apparatus with good coverage. In the P-TEOS CVD apparatus, the film forming ratio between the upper portion of the wiring and the side wall is 5 to 2. Therefore, in order to embed the wiring interval of 1.2√2 μm shown in FIG. 34, about 21000 mm as shown in FIG. A film thickness is required. Since the maximum film thickness at which a stable film can be formed at one time with a P-TEOS CVD apparatus is 9000 mm, 7000 mm is formed in three steps. The shape after film formation is as shown in FIG. From this state, by polishing 14,000 mm by CMP, a desired flat insulating film shape as shown in FIG. 36 is obtained.
[0019]
In this way, in the wiring pattern of FIG. 33, a flat insulating film as shown in FIG. 36 cannot be formed unless the insulating film 16 is formed in 2 steps in 3 times and then polished by 14000 mm by CMP.
[0020]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described conventional problems, and a first object is to planarize the surface of a semiconductor device.
[0021]
The second object of the present invention is to facilitate the flattening of the interlayer film by reducing the wiring interval of S or more and less than L + 2S, which is not permitted in the conventional method.
[0022]
The third object of the present invention is to make it possible to form an insulating film that needs to be planarized in a subsequent process with a minimum necessary thickness.
[0023]
[Means for Solving the Problems]
The present invention relates to a method of manufacturing a reticle wiring pattern in which the space between regular wiring patterns is narrow and the dummy wiring is not allowed to be inserted, and the regular wiring pattern is thickened. Generate a virtual wiring pattern with a predetermined width at an unacceptable location, and By moving the virtual wiring pattern By adhering to any of the regular wiring patterns facing the inter-wiring space, by erasing the portion of the wiring pattern after the adhesion that did not reach the minimum wiring width, and thickening the regular wiring pattern, The problem is solved.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0036]
First, Comparative example Will be explained.
[0037]
FIG. 1 shows a state where normal wiring 20 between diffusion layer regions is performed according to the prior art.
[0038]
FIG. 2 shows a state in which a dummy wiring 21 is added to the regular wiring 20 as shown in FIG. 1 by a conventional method. When arranging the dummy wiring, for example, an inversion pattern (pattern of a non-wiring portion) of the regular wiring 20 shown in FIG.
S + (L / 2) = 1.0 + (1.4 / 2) = 1.7 μm
Undersize, then
L / 2 = 1.4 / 2 = 0.7 μm
By oversizing, the dummy wiring 21 having the minimum wiring interval S with respect to the regular wiring 20 can be generated.
[0039]
In this case, the reverse pattern of the wiring area is not simply undersized by S, but is oversized by L / 2 and then oversized by L / 2 and then restored. This is to prevent a portion that violates the rule of the minimum wiring width L from being undersized only. For example, if the wiring interval is 3.0 μm, the reverse pattern S undersize of the reverse pattern has a reverse pattern of 3 μm wide due to the undersize.
3.0− (2 × 1.0) = 1.0 μm
It becomes a width and violates the minimum wiring width of 1.4 μm. On the other hand, if the undersize is S + (L / 2),
3.0− (2 × 1.7) = − 0.4 μm
Therefore, the pattern disappears in normal CAD design, and no rule violation occurs.
[0040]
By generating the dummy wiring 21 by such an operation and combining it with the regular wiring 20, it is possible to obtain a wiring pattern after the dummy wiring is inserted. FIG. 2 shows this state. The wiring interval M after the dummy wiring is inserted is
2 × {S + (L / 2)} = 2 × {1.0+ (1.4 / 2)} = 3.4 μm
Less than.
[0041]
The pattern as shown in FIG. 2 is obtained by the prior art, and the method of inserting the dummy wiring is not limited to the above method.
[0042]
The wiring interval of the pattern in which the dummy wiring shown in FIG. Comparative example FIG. 3 shows a specific example where the minimum wiring interval is reduced by the above.
[0043]
In the above specific example, the space between wirings where insertion of dummy wirings is not allowed, and the wiring pattern facing the space between wirings is thickened by the minimum interval S = 1.0 μm or more and less than 2S + L = 3.4 μm, It is characterized by decreasing.
[0044]
Further, the wiring pattern facing the inter-wiring space is approximately evenly thickened.
[0045]
The inter-wiring space is preferably reduced to the minimum wiring interval.
[0046]
The specific implementation method is not particularly limited, and can be realized by CAD.
[0047]
Realized by CAD below Book Invention No. 1 An embodiment will be described.
[0048]
In the present embodiment, as shown in FIG. 4, the minimum wiring width L is set so that the remaining wiring interval is, for example, T / 2 at a position where the space between the wirings is narrow and the dummy wiring is not allowed to be inserted. A first virtual wiring pattern 50 having a small predetermined width L1 is generated. As shown in FIG. 5, the generated virtual wiring pattern 50 is connected to one of the normal wirings 20 facing the space between the wirings (the left side in the figure). Of the normal wiring 20L).
[0049]
Further, as shown in FIG. 6, the second virtual space having a predetermined width L2 narrower than the first virtual wiring pattern 50 is set so that the remaining wiring space is S, for example, at the center position of the remaining wiring space T. A wiring pattern 52 is generated and brought into close contact with the regular wiring on the opposite side, as shown in FIG. As a result, the interval between the right regular wiring 20L with which the first virtual wiring pattern 50 is in close contact and the right regular wiring 20R with which the second virtual wiring pattern 52 is in close contact is reduced to 2S.
[0050]
Next, as shown in FIG. 8, the notch portions 50N and 52N that do not reach the minimum wiring width among the first and second virtual wiring patterns 50 and 52 and that do not have the normal wirings closely contact with each other are replaced with the normal CAD design. In accordance with the rules, for example, undersize (reduction), then oversize (enlargement) and then erasing can be performed to obtain a target wiring pattern.
[0051]
By performing such work in advance at the time of design, the maximum value of the wiring interval can be reduced to 2S. For example, when a structure in which a general coating film is sandwiched between CVD oxide films is used With this interlayer film structure, flattening can be performed more easily.
[0052]
In general, the reticle minimum spot size on CAD is G, the maximum wiring interval before the wiring width expansion operation is M, the maximum wiring interval after the wiring width expansion operation is F, and the i-th in the first (second) direction. The maximum wiring interval in the first (second) direction generated after the above operation is Ti, and the number of operations of the wiring width expansion operation is n, and can be performed in the following procedure.
[0053]
(1) A wiring pattern and a dummy wiring pattern are synthesized.
[0054]
(2) An inversion pattern corresponding to the non-wiring portion of the synthesized wiring pattern is created. ₁ / 2 undersize and -T in the first direction (eg X direction) ₁ / 2 is moved so as to be in close contact with the combined wiring pattern of the normal wiring pattern and the dummy wiring.
[0055]
(3) Repeat the procedure of (2) as necessary. That is, when the number of operations for increasing the wiring width is n, the i-th operation is to create an inverted pattern of the wiring patterns synthesized in the operations up to the i−1th operation. _i / 2 undersize and (-1) in the first direction ⁱ × (T _i / 2) Move and synthesize with the wiring pattern synthesized in the operations up to the (i-1) -th operation. Here, the movement amount T in the first direction _i / 2 to (-1) ⁱ The reason is that the coefficient is multiplied by the regular wiring on the opposite side at the (i-1) -th time and the i-th time.
[0056]
(4) The wiring pattern formed by (2) or (3) is undersized by (SG) / 2, and the same amount of oversize is applied to eliminate the notch generated in the work in the first direction. .
[0057]
(5) An inversion pattern of the wiring pattern formed in (4) is created. ₁ / 2 undersize and -T in second direction (eg Y direction) ₁ And is brought into close contact with the wiring pattern formed in (4) and synthesized.
[0058]
(6) Repeat the procedure of (5) as necessary. That is, when the number of operations for increasing the wiring width is n, the i-th operation creates a reverse pattern of the wiring pattern synthesized by the operations up to the i-1th operation, and this is expressed as T _i Undersize to / 2, in the second direction (-1) ⁱ × (T _i / 2) It is moved and brought into close contact with the wiring pattern synthesized in the operations up to the (i-1) -th operation.
[0059]
(7) The wiring pattern formed by (5) or (6) is undersized by (SG) / 2, and the same amount of oversize is applied, so that notches generated in the work in the second direction are formed. Turn off.
[0060]
Here, the parameter satisfies the relationship of the following equation.
[0061]
MT ₁ <S (1)
T _i-1 -T _i <S (2)
MT ₁ <L (3)
T _i-1 -T _i <L (4)
M> T ₁ >...> T _i >...> T _n = F (5)
n ≦ (M−F) / G (6)
[0062]
In this way, the wiring interval between S and less than L + 2S where dummy wiring cannot be provided can be reduced to F = 2S by thickening the regular wiring on both sides.
[0063]
next, Book A specific example of the invention 2 The embodiment will be described in detail.
[0064]
In this embodiment, the minimum wiring width L is 1.4 μm, and the minimum wiring interval S is 1.0 μm. In order to perform patterning, it is necessary to use a reticle. However, in order to create a reticle, there is a minimum spot size G for that purpose. Here, this is 0.1 μm.
[0065]
FIG. 2 shows a state in which a dummy wiring is inserted according to the prior art.
[0066]
The pattern as shown in FIG. Book According to the invention, for example, 2 × S = 2.0 μm or less by a total of four operations, ie, twice in the X direction and twice in the Y direction. In the present embodiment, T satisfying the above-mentioned expressions (1) and (2) is satisfied. ₁ , T ₂ As the value of T ₁ = 2.6 μm, T ₂ = 2.0 μm was selected. Where T ₂ 2.0 μm selected as is the maximum value F of the wiring interval in the final state, which is twice the minimum wiring interval S.
[0067]
First, an operation of increasing the wiring width in the X direction is performed. As shown in FIG. 2 The reverse pattern of the wiring area of T ₁ /2=2.6/2=1.3 μm Undersize, the first virtual wiring pattern 50 in the X direction is generated.
[0068]
Next, this virtual wiring pattern 50 is moved in the X direction.
(-1) ¹ × (T ₁ / 2) = (-1) ¹ × 1.3 = -1.3μm
It is moved and brought into close contact with the regular wiring on the left side as shown in FIG. The first work of thickening the wiring width in the X direction is completed by synthesizing the closely attached virtual wiring pattern with the normal wiring.
[0069]
Next, the second operation for thickening the wiring width in the X direction is performed in the same manner. That is, as shown in FIG. 11, the pattern of the non-wiring portion obtained by inverting the wiring pattern of FIG.
T ₂ /2=2.0/2=1.0 μm
An undersized second virtual wiring pattern 52 in the X direction is generated, and the virtual wiring pattern 52 is generated in the X direction.
(-1) ² × T ₂ / 2 = -1 ² × 1.0 = 1.0 μm
After being moved and brought into close contact with the right regular wiring, the wiring pattern as shown in FIG. 12 is obtained by combining with the regular wiring.
[0070]
Next, with respect to the wiring pattern as shown in FIG. 12, in order to erase the notch 50N violating the wiring rule, the wiring pattern is changed.
(LG) / 2 = (1.4−0.1) /2=0.65 μm
Undersize and oversize. As a result, the notch portion that violates the wiring rule (in this embodiment, the entire first virtual wiring pattern 50) is erased, and a wiring pattern as shown in FIG. 13 is obtained.
[0071]
This completes the work of thickening the wiring in the X direction. Next, the work of thickening the wiring in the Y direction is performed.
[0072]
Specifically, as shown in FIG. 14, the inversion pattern of the wiring layer in FIG.
T ₁ /2=2.6/2=1.3 μm
The first virtual wiring pattern 54 in the Y direction is generated by undersize. Next, this virtual wiring pattern 54 is arranged in the Y direction.
(-1) ¹ × T ₁ / 2 = -1 ¹ × 1.3 = 1.3μm
As shown in FIG. 15, it moves and is brought into close contact with the normal wiring on the lower side of the drawing, and is combined with the normal wiring to obtain a wiring pattern as shown in FIG. This completes the first operation of thickening the wiring width in the Y direction.
[0073]
Next, the second operation of increasing the wiring width in the Y direction is performed in the same manner. That is, the inversion pattern of the wiring layer in FIG.
T ₂ /2=2.0/2=1.0 μm
Undersize to generate the second virtual wiring pattern 56 in the Y direction, and (−1) in the Y direction. ² × T ₂ / 2 = (-1) ² × 1.6 = 1.6μm
After moving and bringing into close contact with the regular wiring on the upper side of the figure, it is combined with the wiring pattern to obtain a new wiring pattern as shown in FIG.
[0074]
Next, in order to erase the notch 56N of the virtual wiring pattern for this wiring pattern,
(LG) / 2 = (1.4−0.1) /2=0.65 μm
Undersize and oversize. By this operation, the pattern that violates the wiring rule is erased. In the finally obtained pattern, F is 2S as shown in FIG.
[0075]
Half In the manufacturing method of the conductor device, the wiring layer is formed using the wiring reticle designed and created by this work. Specifically, a first insulating film is provided on a MOS transistor formed in advance on a semiconductor substrate, contact holes are opened in the first insulating film, and, for example, an aluminum wiring layer is deposited, and FIG. Patterning is performed based on the following pattern. Next, an interlayer insulating film that separates the first-layer wiring and the second-layer wiring is formed of, for example, a coating insulating film, and a predetermined via hole is opened. In the subsequent formation of the upper layer wiring, the semiconductor chip can be completed by using the same method as that for the first layer.
[0076]
In the present embodiment, the width of the virtual wiring pattern is assigned to the wiring patterns on both sides facing the space between the wirings twice as the value of approximately half of the wiring thickening width necessary for obtaining the target wiring interval. Therefore, the wiring on both sides of the space between the wirings can be thickened with the minimum number of operations. Note that the number n of the wiring expansion operations is not limited to two, and the predetermined width of the virtual wiring pattern is set to a predetermined value equal to or less than the maximum wiring width, and the predetermined interval is reduced while the predetermined value is reduced to the target wiring interval. It is also possible to repeatedly assign a plurality of wiring patterns facing the space. In this case, the width of the normal wiring on both sides can be made substantially the same by increasing the number n of times of wiring expansion work and allocating the normal wiring on both sides little by little. Can be averaged out. The operation of removing the notch in this case may be performed every time as in the above embodiment, or may be performed collectively at the end.
[0077]
In the above description, the MOS transistor is taken as an example, but the subject of the first invention is not limited to this, and the same applies to other semiconductor devices such as a bipolar transistor as long as it has a multilayer wiring structure. It is clear that it can be applied to.
[0078]
next, Book Invention No. 3 The embodiment will be described in detail.
[0079]
In this embodiment, in the wiring bent portion as shown in FIG. 33, as shown in FIG. 19, the outer wiring corner is provided with a 45 ° corner, thereby reducing the wiring interval of the wiring bent portion of the wiring straight portion. This is less than the wiring interval.
[0080]
The film forming process in the present embodiment is shown in FIGS. 20, 21, and 22 in comparison with FIGS. 34, 35, and 36 of the conventional example. In the wiring pattern of FIG. 19, a case where a flat insulating film having a minimum insulating film thickness of 7000 mm with respect to the upper layer wiring at a wiring level difference of 6000 mm is formed as in the conventional example.
[0081]
It is assumed that an interlayer insulating film 16 and a metal wiring 20 having a thickness of 6000 mm formed thereon are previously formed on a silicon substrate (not shown) by a normal method using the pattern of FIG. At this time, a cross-sectional view taken along line FF in FIG. 19 which is the widest wiring interval in the pattern is as shown in FIG. From this state, an insulating film 22 that insulates from the upper wiring is formed using a P-TEOS CVD apparatus. In the P-TEOS CVD apparatus, since the film formation ratio between the upper part of the wiring and the side wall is 5 to 2, in order to embed 1.2 μm between the wirings shown in FIG. 20, as shown in FIG. Thickness is required. Since the maximum film thickness at which a stable film can be formed at one time with a P-TEOS CVD apparatus is 9000 mm, 7000 mm is formed in two steps. The shape after film formation is as shown in FIG. From this state, a desired flat insulating film shape as shown in FIG. 22 is obtained by polishing 7000 mm by CMP.
[0082]
As described above, when the wiring pattern of FIG. 20 is used, the insulating film is formed in 14000 in two portions and polished by 7000 mm by CMP, whereby the flat insulating film 22 in FIG. 22 can be formed.
[0083]
In the case of polishing by the CMP method, it is empirically known that the in-plane uniformity of the surface after polishing decreases when the amount of cutting is large, but according to the present embodiment, the amount of polishing by the CMP method is 14,000 mm. Can be reduced to 7000 mm, so that not only the throughput is improved, but also the in-plane uniformity is improved. Note that the polishing method is not limited to the CMP method.
[0084]
In the present embodiment, since only the corners are formed on the outer wiring pattern, the wiring interval of the bent portion becomes 1 / √2 of the wiring interval of the straight portion, but the wiring pattern design is easy. .
[0085]
Note that the method of narrowing the wiring interval of the wiring bent portion as compared with the case of the simple bent pattern as shown in FIG. 33 is not limited to this, and the first method shown in FIG. 4 As in the embodiment, it is possible to corner the outer wiring corner and cut the inner wiring corner. In this case, the wiring interval of the bent portion can be set to be close to the wiring interval of the straight portion.
[0086]
【The invention's effect】
According to the present invention, the surface of a semiconductor device can be planarized.
[0087]
That is Even if the wiring interval cannot be inserted, it is possible to reduce the wiring interval by increasing the width of the wiring layer on both sides by a simple method of automatic work on CAD. Therefore, the coverage of the upper layer wiring can be further improved, wiring defects can be eliminated, and wiring with higher reliability can be formed by simplifying the manufacturing method.
[0088]
Even when the wiring coupling capacity becomes a problem, optimization is possible by appropriately selecting the final wiring interval maximum value F.
[0089]
or, Book According to the present invention, since the film thickness of the insulating film before polishing for obtaining a desired flat insulating film can be reduced to the minimum necessary, the throughput of the film forming apparatus and the polishing apparatus can be improved and the manufacturing cost can be reduced. . Further, when planarization is performed by the CMP method, the amount of polishing can be reduced, and the flatness is improved.
[Brief description of the drawings]
[Figure 1] Comparative example The top view which shows the regular circuit pattern before dummy wiring insertion for demonstrating
FIG. 2 is a top view showing a state in which dummy wirings are inserted into the circuit pattern of FIG.
FIG. 3 shows an interval between wirings in FIG. Comparative example Top view showing a specific example of reducing the minimum wiring interval by
[Fig. 4] Of the present invention The top view which shows the state which generated the 1st virtual wiring pattern between normal wiring in 1st Embodiment.
FIG. 5 is a top view showing a state in which the first virtual wiring pattern is brought into close contact with the left regular wiring in the first embodiment.
FIG. 6 is a top view showing a state in which a second virtual wiring pattern is generated in the first embodiment.
7 is a top view showing a state in which the second virtual wiring pattern is brought into close contact with the right regular wiring in the first embodiment. FIG.
8 is a top view showing a state in which the notch is removed in the circuit pattern of FIG. 7;
9 is a top view showing a state in which the first virtual wiring pattern in the X direction is generated in order to increase the wiring width in the X direction in the circuit pattern of FIG. 2;
10 is a top view showing a state in which the first virtual wiring pattern of FIG. 9 is in close contact with the left circuit pattern. FIG.
11 is a top view showing a state where a second virtual wiring pattern in the X direction is generated in the circuit pattern of FIG.
12 is a top view showing a state in which the second virtual wiring pattern of FIG. 11 is brought into close contact with the circuit pattern on the right side.
13 is a top view showing the circuit pattern of FIG. 12 with the notch removed. FIG.
14 is a top view showing a state in which the first virtual wiring pattern in the Y direction is generated in order to expand the wiring width in the Y direction in the circuit pattern of FIG.
15 is a top view showing a state in which the first virtual wiring pattern of FIG. 14 is in close contact with the lower circuit pattern.
16 is a top view showing a state in which the circuit pattern so far and the first virtual wiring pattern in FIG. 15 are combined. FIG.
17 is a top view showing a state in which a second virtual wiring pattern in the Y direction is generated and is in close contact with the upper circuit pattern in the circuit pattern of FIG. 16;
18 is a top view showing a final circuit pattern obtained by erasing notches in the circuit pattern of FIG. 17;
FIG. 19 Book Invention No. 3 The top view which shows the example of the wiring pattern by embodiment
20 is a sectional view taken along line FF in FIG.
21 is a sectional view showing a state immediately after an insulating film is formed on the metal wiring of FIG.
22 is a cross-sectional view showing a state after the insulating film of FIG. 21 is polished to a predetermined thickness.
FIG. 23 Book Invention No. 4 The top view which shows the example of the wiring pattern by embodiment
FIG. 24 is a top view showing an example of multilayer wiring in a conventional MOS transistor.
25 is a top view showing a state in which dummy wiring is added to the wiring pattern of FIG.
FIG. 26 is a top view showing a conventional state in which dummy wirings are inserted where there is sufficient wiring spacing.
FIG. 27 is a top view showing a conventional state in which dummy wiring is attempted to be placed where the wiring interval is insufficient.
FIG. 28 is a cross-sectional view of a semiconductor chip for explaining problems of the prior art
FIG. 29 is a sectional view showing a conventional state immediately after an insulating film is formed on a metal wiring.
30 is a cross-sectional view showing a state after the insulating film of FIG. 29 is polished.
FIG. 31 is a cross-sectional view showing a conventional state in which an insulating film is formed on a wiring by a film formation method with poor coverage;
FIG. 32 is a diagram for explaining a conventional film forming ratio;
FIG. 33 is a plan view showing an example of a conventional simple bending pattern;
34 is a cross-sectional view taken along line EE of FIG.
35 is a cross-sectional view showing a state immediately after an insulating film is formed on the metal wiring of FIG. 34.
36 is a cross-sectional view showing a state after the insulating film of FIG. 35 has been polished to a predetermined thickness.
[Explanation of symbols]
10 ... Semiconductor substrate
12 ... diffusion layer region
16: First interlayer insulating film
17 ... Contact hole
18 ... Lower layer wiring
20, 20R, 20L ... wiring
21 ... Dummy wiring
22 ... Insulating film
50, 52, 54, 56 ... Virtual wiring pattern
50N, 52N, 56N ... Notch

Claims (1)

A method for manufacturing a reticle wiring pattern in which a space between regular wiring patterns is narrow and the dummy wiring is not allowed to be inserted, and the regular wiring pattern is thickened.
Generate a virtual wiring pattern of a predetermined width at a place where the insertion of the dummy wiring is not allowed,
By moving the generated virtual wiring pattern, the virtual wiring pattern is brought into close contact with any of the normal wiring patterns facing the space between the wirings,
A method for manufacturing a reticle wiring pattern, wherein the regular wiring pattern is thickened by erasing a portion that has not reached the minimum wiring width in the contacted wiring pattern.

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