JP3995582B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device that realizes miniaturization of the device and a manufacturing method thereof.
[0002]
[Prior art]
Field effect transistors (MOSFETs) can be broadly classified according to whether the current flows in the vertical direction or the element surface direction. The former is called a vertical element and the latter is called a horizontal element. A vertical element is often used as an individual element that handles particularly high power because one of the main electrodes is on the back surface of the semiconductor element and has excellent current-carrying capacity per unit area. On the other hand, a horizontal element is suitable for integration because all electrodes can be arranged on one surface, and is often used as a component of an integrated circuit.
[0003]
FIG. 6 shows a cross-sectional view of a lateral MOSFET according to the prior art. MOSFET 115 is obtained by diffusing n-type source region 103 and n-type drain region 102 on its surface by a self-alignment technique, and forming a channel region on the surface of p-type substrate 101 immediately below gate electrode 107. .
[0004]
Both the source region 103 and the drain region 102 are formed by ion implantation into the surface of the substrate 101 and then thermal diffusion, and are connected to the source electrode 111 and the drain electrode 110, respectively (see, for example, Patent Document 1).
[0005]
Next, the principle of operation of this MOSFET will be described with reference to FIG. A source terminal S and a drain terminal D are drawn from the source electrode and the drain electrode, respectively, and the gate electrode is insulated from the p substrate by a silicon oxide film or the like. Even if a voltage is applied between the drain and source in this state, no current flows because the two n regions are separated by the p region.
[0006]
When a positive voltage is applied to the gate electrode, electrons, which are negative charges included in the p substrate, are attracted to the gate through the insulating film, and the polarity of the semiconductor at the boundary with the insulating film is reversed, resulting in a channel. A region is formed. As a result, the drain region-substrate-source region is continuous with the n-type semiconductor, and a current flows according to the polarity of the voltage applied between the drain and source.
[0007]
At this time, if there is a potential difference between the ground potential of the gate and the ground potential of the source,
The cells in the chip operate unevenly, leading to an increase in leakage current and a reduction in breakdown resistance.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-284187 (2nd page, FIG. 2)
[0009]
[Problems to be solved by the invention]
FIG. 8A illustrates an example of a semiconductor device in which the source electrode 111 is short-circuited to the substrate 101. As shown in FIG. 6, after element diffusion regions and electrodes connected to each region are formed on the wafer, the scribe line 108 is cut and divided into individual MOSFET chips 115.
[0010]
The back surface of each chip 115 is fixed to a lead header 116a, and a source pad electrode 111P connected to the source electrode 111 is wire-bonded to the header 116a. The gate pad electrode 107P connected to the gate electrode 107 is wire-bonded to the lead 116b serving as the gate terminal, and the drain pad electrode 110P connected to the drain electrode is bonded to the lead 116c serving as the drain terminal.
[0011]
By connecting the source electrode having the GND potential to the header, the potential difference between the gate ground potential and the source ground potential is eliminated, and the MOSFET cells operate uniformly.
[0012]
In the wire bonding, the bonding wire 118 is carried on the chip 115 by the capillary 150 to perform the bonding. As shown in FIG. 8B, the tip of the capillary 150 has a diameter φ of, for example, about 200 μm. For example, in the case of source wire bonding, the bonding wire 118 is fixed to the chip 115 and then moved to the header 116a to fix the wire. To do. At this time, if the capillary 150 contacts the chip 115, the chip 115 is destroyed, so this contact must be avoided. For this reason, a space of about 400 μm square is required as the wire bond area 130 in the header 116a.
[0013]
However, at present, the chip has been miniaturized, and the chip size of a small chip has shrunk to 0.3 mm square. In such a chip, securing the wire bond area 130 of about 400 μm square on the header is a major factor that prevents the reduction in size of the outer shape.
[0014]
[Means for Solving the Problems]
The present invention has been made in view of such problems. First, an element region provided on the surface of a semiconductor substrate, a plurality of electrodes connected to the element region, and at least one of the electrodes provided on the substrate side wall are connected. A semiconductor chip having a conductive path and a lead for fixing the chip, which is solved by exposing a conductive adhesive for fixing the chip from an end of the chip and connecting the conductive path. is there.
[0015]
Second, a reverse conductivity type source region and drain region provided on the surface of one conductivity type substrate, a source electrode and a drain electrode in contact with the source region and the drain region, and a substrate surface between the source region and the drain region A semiconductor chip comprising a gate electrode provided through an insulating film, a conductive path provided on a side surface of the substrate and connected to the source electrode, and a lead for fixing the chip, and fixing the chip The problem is solved by exposing the conductive adhesive from the end of the substrate and connecting the conductive path.
[0016]
The lead is applied with a GND potential.
[0017]
The conductive path is formed by adhering a conductive material to the side surface of the chip.
[0018]
The conductive path is an impurity diffusion region provided on the side surface of the chip.
[0019]
Third, a step of forming an element diffusion region on the substrate, a step of forming a groove on the scribe line of the substrate, and a conductive path that covers the inner wall of the groove and is connected to a part of the element diffusion region. And a step of cutting the scribe line, fixing each semiconductor chip to the lead with a conductive adhesive, and connecting the conductive path exposed from the chip end to the conductive path. To do.
[0020]
Further, the groove is formed to a depth that does not reach the back surface of the substrate by anisotropic etching.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5 by taking an n-channel MOSFET chip as an example.
[0022]
The semiconductor device of the present invention comprises a MOSFET chip 15 having a conductive path 12 on the side wall, a lead 16 and a conductive adhesive 17 as shown in FIG.
[0023]
As shown in FIG. 1B, a MOSFET chip 15 includes a one-conductivity type substrate 1, a source region 3 and a drain region 2, a source electrode 11 and a drain electrode 10, a gate electrode 7, and a conductive path 12.
[0024]
The substrate 1 is a p-type semiconductor substrate, and a source region 3 and a drain region 2 are provided on the surface thereof by diffusing n-type impurities by a known method. Source electrode 11 and drain electrode 10 are in contact with source region 3 and drain region 2.
[0025]
The gate electrode 7 is provided on the surface of the substrate 1 between the source region 3 and the drain region 2 via a gate insulating film 6. By applying a voltage to the gate electrode 7, a channel region is formed on the substrate surface between the source region 3 and the drain region 2 immediately below the gate electrode 7.
[0026]
The source electrode 11 and the drain electrode 10 are arranged in a shape in which comb teeth are engaged, and the gate electrode 7 is arranged between the respective comb teeth. A semiconductor material (for example, polysilicon) constituting the gate electrode 7 extends outside the element diffusion region 20 to be connected to the gate pad electrode 7P, and the drain electrode 10 also extends to the drain pad electrode 10P outside the element region 20. Connected. The source electrode 11 extends from the element diffusion region and is patterned so as to substantially surround the outer periphery of the element diffusion region 20.
[0027]
The conductive paths 12 are respectively provided on the side surfaces of the MOSFET chip 15 having the above components. After the element diffusion region 20 is formed in the state of a wafer, it is provided using a scribe line when it is divided into individual chips 15 by dicing. The conductive path 12 is a region in which a conductive material such as metal or polysilicon doped with impurities is attached to the side surface of the chip 15 or a region in which high-concentration impurities are diffused to the side surface of the chip 15. Since this conductive path 12 is a region that serves as a substitute for the wire bond that brings the source electrode 11 to the GND potential, it is connected to the source electrode 11 that extends to the outer periphery of the chip 15 and has at least one line along the side surface of the chip 15. A plurality of them are preferably arranged. In order to make the GND potential of the entire chip 15 uniform, it is desirable to provide it uniformly from the entire periphery.
[0028]
The conductive path 12 does not reach the back surface of the chip 15 in the manufacturing process of the semiconductor device as will be described later. That is, it is provided on the side surface of the chip 15 extending from the surface of the chip 15 and 20 μm to 50 μm above the back surface of the chip.
[0029]
Further, the MOSFET chip 15 is mounted on the header 16a of the lead 16 as shown in FIG. 1A, and the back surface of the chip 15 is fixed to the header 16a by a conductive adhesive 17 such as solder or epoxy resin.
[0030]
At this time, the conductive adhesive 17 protrudes from the fixing region of the chip 15 and rises and adheres to the chip end by about 20 μm to 50 μm. As a result, the conductive path 12 provided on the side surface of the chip 15 comes into contact with the source electrode 11 on the surface of the chip 15 and the header 16a. That is, the source electrode 11 and the header 16a can be connected without using a wire bond.
[0031]
FIG. 2 shows a plan view in which the chip 15 is mounted.
[0032]
The chip is fixed to the header 16 a as described above, and the source electrode 11 and the header 16 a are connected through the conductive path 12. The gate pad electrode 7P is connected to the lead 16b serving as the gate terminal G by a bonding wire, and the drain pad electrode 10P is connected to the lead 16c serving as the drain terminal D by a bonding wire. The header 16 a is a source terminal S, and the GND potential is applied as usual, and the GDN potential is applied to the source electrode 11. Further, it is molded with a resin layer 19 or the like to become a finished product.
[0033]
Conventionally, as shown in FIG. 8A, the source electrode 11 and the header 16a are connected by the bonding wire 118, and since the capillary 150 is used, it is necessary to secure a space of about 400 μm square as a wire bond region on the header. This hindered the miniaturization of the outer shape. However, according to the present embodiment, it is sufficient to secure at least a region necessary for fixing the chip, the outer shape can be greatly shrunk, and there is an advantage that mounting on a small outer shape is possible.
[0034]
Furthermore, the bonding wire for the source electrode 11 is not required, and the cost can be reduced.
[0035]
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 to 5 by taking an n-channel MOSFET chip as an example.
[0036]
The method for manufacturing a semiconductor device of the present invention includes a step of forming an element diffusion region 20 on a substrate, a step of forming a groove 9 on a scribe line 8 of the substrate, a part of the element diffusion region 20 covering the inner wall of the groove 9. A step of forming the conductive path 12 to be connected to the semiconductor chip, a step of cutting the scribe line 8 to separate the individual semiconductor chips 15, and a semiconductor chip 15 fixed to the lead 16 with the conductive adhesive 17 to connect the conductive path 12 and the conductive path. And a step of connecting the adhesive 17.
[0037]
First step (FIG. 3A): a step of forming the element diffusion region 20 on the substrate 1 by a known method.
[0038]
First, the p-type silicon semiconductor substrate 1 is oxidized at about 800 ° C., and a gate oxide film 6 of about several hundreds of liters is formed by a driving voltage. Next, polysilicon having a resistance reduced by introducing impurities is deposited on the gate oxide film 6 so as to remain on the gate oxide film 6 between the planned source region 3 and the planned drain region 2. The gate electrode 7 is formed by patterning. Further, the entire surface is thermally oxidized to cover the gate electrode 7 with the gate oxide film 6.
[0039]
Thereafter, the oxide film on both ends of the gate electrode 7 is removed to expose the semiconductor substrate 1, and n-type impurities are ion-implanted and then thermally diffused to form the source region 3 and the drain region 2. Preferably, a p + type region 4 is provided around the source region 3 in order to ground the channel region formed immediately below the gate electrode 7 at the same potential as the source electrode 11, and a contact is provided around the chip 15. An annular 5 for reducing the resistance is formed to form an element diffusion region 20 of the MOSFET.
[0040]
Second step (FIG. 3B): a step of forming the groove 9 on the scribe line 8 of the substrate 1.
[0041]
In order to form the conductive path 12, a groove 9 is formed on the scribe line 8. The region other than the groove 9 is masked, and the groove 9 is formed substantially perpendicular to the surface of the substrate 1 by anisotropic etching using plasma. The grooves 9 are formed at a depth of 20 μm to 50 μm above the back surface so as not to reach the back surface of the substrate 1 because the chips are individually separated when reaching the back surface of the substrate 1 and the subsequent process becomes complicated. This groove 9 becomes a conductive path 12 in a later step. “Up from 20 μm to 50 μm” from the back surface is a distance necessary for the conductive adhesive to rise from the end of the chip 15 to the side surface of the chip 15 and connect to the conductive path 12. This is because the contact with the agent may be poor, and if a groove is formed (deeply) below 20 μm, the strength of the wafer cannot be maintained in the subsequent manufacturing process.
[0042]
In addition, isotropic etching using a mixed solution of hydrofluoric acid and nitric acid may be used, but in the case of isotropic etching, etching proceeds in the lateral direction with the same length as the depth direction, so that a 100 μm groove is formed. In some cases, a 200 μm scribe line is required. Since the scribe line is generally about 100 μm to 150 μm, depending on the thickness of the wafer (usually about 100 μm to 400 μm), anisotropic etching is preferable if a deep groove is formed.
[0043]
Third step (FIG. 3C): a step of forming a conductive path 12 that covers the inner wall of the groove 9 and is connected to a part of the element diffusion region 20.
[0044]
A source electrode 11 and a drain electrode 10 that contact the source region 3 and the drain region 2 are formed by sputtering metal on the entire surface, and at the same time, a conductive path 12 is formed on the inner wall of the groove 9. The source electrode 11 extending so as to surround the outer periphery of the element diffusion region 20 and the conductive path 12 on the inner wall of the groove 9 are formed using a patterned mask having a desired shape. The drain pad electrode 10P is also patterned at the same time.
[0045]
Here, as shown in FIGS. 4A and 4B, the conductive path 12 is not limited to metal but may be polysilicon 12a doped with impurities. Polysilicon 12 a is deposited so as to cover the inner wall of the groove 9, and the drain electrode 10 and the source electrode 11 are formed to connect the source electrode 11 and the conductive path 12.
[0046]
Furthermore, as shown in FIGS. 4C and 4D, the conductive path 12 may be a region having conductivity by injecting and diffusing high-concentration impurities into the groove inner wall. In this case, after the trench 9 is formed, the impurity diffusion region 12b is formed on at least the side wall of the trench 9 by oblique ion implantation or the like. Thereafter, the drain electrode 10 and the source electrode 11 are formed, and the source electrode 11 and the conductive path 12 are connected.
[0047]
Fourth step (FIG. 5): The scribe line 8 is cut and separated into individual semiconductor chips 15, and the semiconductor chips 15 are fixed to the leads 16 a with the conductive adhesive 17 to connect the conductive paths 12 and the conductive adhesive 17. Process.
[0048]
The remaining scribe lines 8 are cut and separated into individual semiconductor chips 15 (FIG. 5A). In this state, as shown in FIG. 1 or FIG. 5B, a plurality of conductive paths 12 connected to the source electrode 11 on the chip surface are extended on the side surface of the chip. Next, the individual semiconductor chips 15 are fixed to the lead headers 16a in the assembly process. For fixing, a conductive adhesive 17 such as solder or epoxy resin is used, and an amount of about 30 μm is supplied and fixed. As a result, the conductive adhesive 17 rises and adheres to the side surface of the chip 15 from the end of the chip 15 and comes into contact with the conductive path 12. As described above, since the conductive path 12 is provided at a depth from 20 μm to 50 μm above the chip back surface, it is sufficiently high to contact the conductive adhesive 17. Thereby, the source electrode 11 and the header can be connected without using a bonding wire, and it is not necessary to secure a wire bonding region.
[0049]
Further, the lead 16b and the gate pad electrode 7P to be the gate terminal G are connected to the lead 16c and the drain pad electrode 10P to be the drain terminal D by the bonding wires 18, respectively, and the resin mold 19 is formed to obtain the final structure shown in FIG. Get.
[0050]
【The invention's effect】
According to the present invention, a space of about 400 μm square required for wire bonding between the source electrode and the header can be omitted. Even if the size of the chip has been reduced, the conventional structure that secures the wire bond region has not been reduced in size. However, according to the present invention, only the chip fixing region is required, and the size can be greatly reduced.
[0051]
Furthermore, since no bonding wire for the source electrode is required, there is an advantage that it can contribute to cost reduction.
[Brief description of the drawings]
FIG. 1A is a perspective view and FIG. 1B is a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 2 is a plan view illustrating a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view illustrating a conventional semiconductor device.
FIG. 7 is a conceptual diagram illustrating a conventional semiconductor device according to the present invention.
8A is a plan view and FIG. 8B is a side view for explaining a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Drain region 3 Source region 4 P + type region 5 Annular 6 Gate insulating film 7 Gate electrode 7P Gate pad electrode 8 Scribe line 9 Groove 10 Drain electrode 10P Drain pad electrode 11 Source electrode 12 Conductive path 12a Polysilicon 12b Impurity diffusion Region 15 Semiconductor chip 16 Lead 16a Header 16b Lead 16c Lead 18 Bonding wire 19 Resin layer 20 Element diffusion region 101 Semiconductor substrate 102 Drain region 103 Source region 104 P + type region 105 Annular 106 Gate insulating film 107 Gate electrode 107P Gate pad electrode 108 Scribe Line 110 Drain electrode 110P Drain pad electrode 111 Source electrode 111P Source pad electrode 115 Semiconductor chip 116 Lead 116a Header 116 Lead 116c lead 118 bonding wires 119 resin layer 120 element diffusion region 130 wire bonding region 120 capillaries

Claims (7)

An element region provided on the surface of the semiconductor substrate;
A plurality of electrodes connected to the element region;
A semiconductor chip comprising a conductive path provided on the substrate side wall and connected to at least one of the electrodes;
A lead for fixing the chip;
A semiconductor device, wherein a conductive adhesive for fixing the chip is exposed from an end of the chip and connected to the conductive path. Reverse conductivity type source region and drain region provided on the surface of one conductivity type substrate;
A source electrode and a drain electrode in contact with the source region and the drain region;
A gate electrode provided on the substrate surface between the source region and the drain region via an insulating film;
A semiconductor chip comprising a conductive path provided on a side surface of the substrate and connected to the source electrode;
A lead for fixing the chip;
A semiconductor device, wherein a conductive adhesive for fixing the chip is exposed from an end of the substrate and connected to the conductive path. The semiconductor device according to claim 1, wherein a GND potential is applied to the lead. The semiconductor device according to claim 1, wherein the conductive path is formed by attaching a conductive material to a side surface of the chip. The semiconductor device according to claim 1, wherein the conductive path is an impurity diffusion region provided on a side surface of the chip. Forming an element diffusion region on the substrate;
Forming a groove on a scribe line of the substrate;
Forming a conductive path that covers the inner wall of the groove and connects to a part of the element diffusion region;
Cutting the scribe line, fixing each semiconductor chip to a lead with a conductive adhesive, and connecting the conductive adhesive exposed from the end of the chip and the conductive path. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the groove is formed to a depth that does not reach the back surface of the substrate by anisotropic etching.

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