JP5055892B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a conductive wall around the entire periphery of a semiconductor substrate and a method for manufacturing the semiconductor device.

As portable electronic devices such as digital video cameras, digital mobile phones, and notebook computers become smaller, thinner, and lighter, there is an increasing demand for miniaturization of semiconductor devices used inside.
As a technology for reducing the size of a semiconductor device that solves this problem, a package technology called CSP (Chip Size Package) in which the area of the semiconductor chip is the same as the mounting area, and a plurality of semiconductor chips are stacked in the same package. A technology called a stack package has been developed.

  A semiconductor device in which two or more digital chips and analog chips are embedded is affected by digital noise from the digital chip to the analog chip. However, a CSP type semiconductor device cannot be shielded by a ground mesh. For this reason, since it is necessary to keep a sufficient distance or cut off by a dielectric material in order to obtain a stack structure, at present, a structure in which it is laid flat on the same plane is taken. However, the flat structure increases the size and cannot satisfy the demand for miniaturization.

Further, it is conceivable to cover the semiconductor device with a noise shielding sheet or the like. However, at present, there is no sheet having a thickness of 100 μm or less, so that it cannot be applied to a stack structure. For this reason, analog chips and digital chips are mounted on both sides of the organic substrate, but it is necessary to form bumps on the substrate through-holes and one side, making the entire semiconductor device thicker and thinner. Can't plan.
JP 2003-124236 A JP-A-10-79623

  Therefore, an object of the present invention is to provide a semiconductor device that can be shielded without using a ground mesh in a semiconductor device having a plurality of semiconductor chips, and a method for manufacturing the same.

  A semiconductor device according to the present invention includes a substrate, a first isolation region of a first conductivity type formed over the entire surface of the substrate, below the element region where the element is formed on the substrate, and a peripheral portion of the substrate A second separation region of the first conductivity type formed from the surface of the substrate to a depth reaching the first separation region over the entire periphery, and connected to the second separation region, and the entire peripheral portion on the substrate And a conductive wall formed around the periphery.

  In the semiconductor device of the present invention, the first conductivity type first isolation region is formed in the substrate, and the first conductivity type so as to be connected to the first conductivity type first isolation region in the substrate. A second separation region is formed, and a conductive wall is formed on the substrate so as to be connected to the second separation region.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a conductive wall on the entire periphery of a peripheral portion on a substrate, and sandwiches a scribe line in the wafer on which the substrate is integrated. The first conductivity type formed from the surface to a depth reaching the first isolation region of the first conductivity type formed on the entire surface of the substrate under the element region where the element is formed on the substrate. The method includes a step of forming a conductive wall on the entire periphery of the peripheral portion on the recording substrate so as to be connected to the second separation region, and a step of dicing the wafer in the scribe line.

In the semiconductor device manufacturing method of the present invention, first, a second separation region is formed in the wafer, and a conductive wall is formed so as to be connected to the second separation region with a scribe line in the wafer interposed therebetween.
Next, the wafer is diced with a scribe line.
Next, bumps are formed on the upper surface portion of the conductive posts to obtain individual semiconductor devices.

  According to the present invention, it is possible to provide a semiconductor device that can be shielded without using a ground mesh in a semiconductor device having a plurality of semiconductor chips, and a manufacturing method thereof.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment. FIG. 2 is a perspective view showing a schematic configuration of the semiconductor device according to the embodiment.
As shown in FIG. 1, a first isolation region 2 of a first conductivity type (hereinafter also referred to as a first isolation region) made of high-concentration impurities is formed in a semiconductor substrate 1 by epitaxial growth, for example. For example, a first conductivity type second isolation region 3 (hereinafter also referred to as a second isolation region) made of a high concentration impurity is formed so as to be connected to the first isolation region 2 in FIG.

  Further, a pad 5 made of, for example, Al connected to a part of the internal wiring of the semiconductor substrate 1a is formed on the surface layer of the semiconductor substrate 1a, and the entire surface of the semiconductor substrate 1 and the peripheral portion of the pad 5 are formed. A passivation film 4 made of, for example, silicon oxide, silicon nitride, silicon oxynitride or the like is formed so as to cover and expose at least a part of the upper surface of the pad 5.

Further, an insulating film 6 made of, for example, photosensitive polyimide is formed on the passivation film 4. A wiring groove WD is formed in the insulating film 6 so that the pad 5 is exposed on the bottom surface.
The insulating film 6 is formed with a post groove PD1 so that the second isolation region 3 is exposed on the bottom surface.

Further, a seed film 7 made of, for example, TiCu is formed so as to cover the inner walls of the wiring groove WD and the post groove PD1. In the upper layer, for example, a wiring 9 made of Cu is formed in the wiring groove WD, and a conductive wall 11b made of Cu, for example, is formed in the post groove PD1.
Further, a post groove PD2 is formed in the upper layer of the wiring 9 so that the wiring 9 is exposed on the bottom surface, and a conductive post 11a made of Cu, for example, is formed in the post groove PD2.

  Furthermore, the upper layer of the insulating film 6 in the gap between the wirings 9 or in the gap between the conductive posts 11a and the conductive walls 11b is made of, for example, polyamide resin, polyimide resin, epoxy resin, phenol resin, or polarphenylene benzobisoxazole resin. An insulating buffer layer 12 is formed.

Further, bumps 13a are formed on the surface of the buffer layer 12 by solder balls, solder paste, or the like so as to be connected to the conductive posts 11a. Further, bumps 13b are formed by solder balls, solder paste, or the like so as to be connected to the conductive wall 11b.
As described above, the semiconductor device 20 shown in FIGS. 1 and 2 is formed.

  In the semiconductor device according to the embodiment, the first isolation region 2 and the second isolation region 3, the second isolation region 3 and the conductive wall 11b, and the conductive wall 11b and the bump 13b are connected to each other. Therefore, by applying a constant voltage such as a ground to the bump 13b formed on the upper surface of the conductive wall 11b, the connected inner region (hereinafter also referred to as an element region) is casing with a shield case. As in the case, it can be shielded, and digital noise acting on the element region can be suppressed. In particular, it is effective for shielding a semiconductor device that cannot be shielded by a ground mesh, such as a CSP type semiconductor device.

Next, a method for manufacturing a semiconductor device according to the above embodiment will be described.
FIG. 3 is a plan view showing a schematic configuration of a semiconductor wafer according to an embodiment of the present invention.
As shown in FIG. 3, the semiconductor wafer 1 is divided into semiconductor devices 20 by scribe lines SL.
4 to 11 are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In one embodiment, for example, all the steps shown in FIGS. 4-11 can be performed at the wafer level.
First, as shown in FIG. 4A, active elements (not shown) are formed on the semiconductor wafer 1. A first isolation region 2 made of high-concentration impurities is formed by, for example, epitaxial growth on the entire surface of the semiconductor wafer 1 below the element region in the semiconductor wafer 1 where active elements are formed. The second separation region 3 made of high-concentration impurities is formed, for example, by ion implantation so as to be connected to the first separation region 2 across the scrub line SL in the upper layer. Then, a pad 5 made of, for example, Al from an active element is formed on the semiconductor wafer 1 in a peripheral shape or a matrix shape, and on the semiconductor wafer 1, for example, silicon oxide, A passivation film 4 made of silicon nitride, silicon oxynitride or the like is formed.

Next, as shown in FIG. 4B, an insulating film 6 made of photosensitive polyimide or the like is formed on the second isolation region 3, the passivation film 4 and the pad 5 by, for example, spin coating or printing. Form. The insulating film 6 is made to have a film thickness of 4 to 10 μm after curing.
When the insulating film 6 is made of photosensitive polyimide, for example, application is performed while changing the conditions in the order of the following 1 to 5 using a coating apparatus such as a spin coater.
Rotational speed Time 1: 1000rpm 30s
2: 1950 rpm 40 s
3: 1000rpm 10s
4: 1500rpm 10s
Next, as shown in FIG. 4C, after the insulating film 6 is pre-baked, the insulating film 6 is subjected to pattern processing of the wiring groove WD and the post groove PD1 by photolithography. Then, the patterned insulating film 6 is developed by a phenomenon device such as a spin developer to form wiring grooves WD and post grooves PD1.

Next, as shown in FIG. 5A, a seed film 7 made of Ti / Cu or the like is formed by, for example, physical vapor deposition such as sputtering. For example, the seed film 7 has a thickness of 160 nm for Ti and 600 nm for Cu.
Next, as shown in FIG. 5B, the upper layer of the seed film 7 is covered with a resist film 8 by, for example, a resist coater such as a spin coater, and patterning of the wiring groove WD is performed on the resist film 8 by photolithography. do. Then, the patterned resist film 8 is developed by a developing device such as a spin developer to form a wiring groove WD in the resist film 8.

Next, as shown in FIG. 6A, for example, the seed film 7 is energized in the wiring trench WD in the upper layer of the exposed seed film 7, and the wiring 9 made of Cu, for example, is formed by electrolytic plating or the like. .
Next, as shown in FIG. 6B, the resist film 8 is removed by, for example, plasma ashing. The seed film 7 is left as a seed for forming, for example, a conductive post 11a and a conductive wall 11b made of Cu by an electrolytic plating method to be described later.

Next, as shown in FIG. 7A, a resist film 10 is coated on the seed film 7 and the wiring 9 by a resist coating apparatus such as a spin coater, and the post groove PD1 is formed in the resist film 10 by photolithography. And pattern processing of the post groove PD2. Then, the patterned resist film 10 is developed by a developing device such as a spin developer to form post grooves PD1 and post grooves PD2.
Next, as shown in FIG. 7B, the seed film 7 and the post groove PD2 in the upper layer of the exposed seed film 7 and wiring 9 are made conductive by, for example, energizing the seed film 7 and electrolytic plating. Posts 11a and conductive walls 11b are formed. The height of the conductive posts 11a and the conductive walls 11b is set to 80 to 180 μm, and the width or diameter is set to 180 to 300 μm.

Next, as shown in FIG. 8A, the resist film 10 is removed by, for example, plasma ashing.
Next, as shown in FIG. 8B, the seed film 7 is removed by performing etching such as plasma etching using the wiring 9, the conductive posts 11a, and the conductive walls 11b as a mask.

Next, as shown in FIG. 9 (a), the conductive posts 11a and the conductive walls 11b are filled up to the height where the conductive posts 11a and the conductive walls 11b are filled for protection and stress relaxation of the circuit portion, for example, polyamideimide, polyimide, epoxy resin, A buffer layer 12 made of phenol resin or polyparaphenylene benzobisoxazole is formed.
Next, as shown in FIG. 9B, after the buffer layer 12 is cured, the buffer layer 12 is subjected to, for example, the following conditions until the surfaces of the conductive posts 11a and the conductive walls 11b are exposed by, for example, a grinding method. Grind by.
・ Wheel: # 600
・ Rotation speed: 3500 rpm
・ Polishing speed: 5mm / sec

Next, as shown in FIG. 10A, the semiconductor wafer 1 is half-cut by dicing at a scribe line to form a dicing street DS. The depth of the dicing street DS is a depth that reaches at least the first isolation region 2 and is, for example, 40 μm deeper than the desired thickness of the semiconductor device 20.
Next, as shown in FIG. 10B, bumps 13a and bumps 13b are formed on the surfaces of the conductive posts 11a and the conductive walls 11b whose upper surfaces are exposed by using, for example, solder balls or solder paste.
Next, as shown in FIG. 11, the back surface of the semiconductor wafer 1 is formed from the back surface side of the surface on which the bumps 13a are formed by, for example, BGR (back grinding) so that the semiconductor device 20 has a desired thickness. The semiconductor wafer 1 is ground to divide the semiconductor wafer 1 into pieces, thereby forming the semiconductor device 20 shown in FIG.

  In implementing the present invention, the present invention is not limited to the above-described embodiment, and various modifications can be employed.

In the above embodiment, Cu is used as the wiring. However, the present invention is not limited to this. For example, a conductive metal such as Al, Ag, Au, Pt, W, or Co may be used.
Moreover, although TiCu was used as the seed film, it is not limited to this, and for example, Cu or the like may be used.
Further, either the donor or the acceptor may be used as the high concentration impurity in the first isolation region and the second isolation region.
Further, although photosensitive polyimide is used as the insulating film, the insulating film is not limited to this, and for example, an insulating material such as silicon oxide or silicon nitride may be used. When silicon oxide or silicon nitride is used as the insulating film 6, it is necessary to pattern the resist film after covering it.
Moreover, although the conditions for applying the insulating film are described, the present invention is not limited to this.
Moreover, although the conditions for polishing the buffer layer are described, the present invention is not limited to this.

  According to the method of manufacturing a semiconductor device according to the above-described embodiment, the first isolation region 2 made of the high concentration impurity is formed in the semiconductor wafer 1, and the high concentration impurity is connected to the first isolation region 2. The second separation region 3 is formed, the conductive wall 11b is formed so as to be connected to the second separation region 3, and the bump 13b is formed so as to be connected to the upper surface of the conductive wall 11b. The bump 13b formed on the upper surface of the conductive wall 11b is shielded by applying a constant voltage such as a ground to the connected inner region (element region) in the same manner as in the case of casing with a shield case. Thus, the semiconductor device 20 capable of suppressing digital noise acting on the element region can be manufactured.

  In addition, the semiconductor substrate 1a in the above embodiment corresponds to the substrate of the invention. Further, the semiconductor wafer 1 in the above-described embodiment corresponds to the wafer of the invention. Further, the wiring 9 in the above-described embodiment corresponds to a wiring layer of the invention.

FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a perspective view showing a semiconductor according to an embodiment of the present invention. FIG. 3 is a plan view showing a schematic configuration of a semiconductor wafer according to an embodiment of the present invention. 4A to 4C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10A and FIG. 10B are cross-sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Explanation of symbols

1: Semiconductor wafer 1a: Semiconductor substrate 2: First isolation region 3: Second isolation region 4: Passivation film 5: Pad 6: Insulating film 7: Seed film 8: Resist film 9: Wiring 10: Resist film 11a: Conductivity Post 11b: Conductive wall 12: Buffer layer 13a, 13b: Bump 20: Semiconductor device SL: Scribe line DS: Dicing street WD: Wiring groove PD1, PD2: Post groove

Claims (2)

In order to manufacture a semiconductor device having a conductive wall on the entire periphery of a peripheral portion on a semiconductor substrate,
The semiconductor substrate is integrated with a scribe line in between, and an element is formed on one surface, and a first isolation region of the first conductivity type is formed on the entire surface of the semiconductor substrate below the element region where the element is formed. In which a second separation region of the first conductivity type is formed from the one surface to a depth reaching the first separation region on the entire periphery of the outer periphery of the element including the scribe line region. Forming a conductive wall around the entire periphery of the periphery of the element including the region of the scribe line on the semiconductor substrate so as to be connected to the second isolation region;
By dividing the second separation region and the conductive wall by half-cutting from the one surface side to the first separation region of the first conductivity type formed on the wafer to form a dicing street , A step of forming the second isolation region and the conductive wall formed on the entire periphery of the side edge of the adjacent semiconductor device ;
Polishing the wafer from the side of the other surface opposite to the one surface of the wafer until the bottom surface of the dicing street is reached, and separating the wafer into individual pieces. The semiconductor device according to claim 1 , further comprising a step of forming a bump on each upper surface of the conductive wall divided by dicing between the step of forming a dicing street and the step of dividing the wafer into pieces. Production method.

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