JP4004744B2 - MROM circuit and cell data determination method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a NAND-type MROM circuit used in a microcomputer system, and more particularly to a cell data determination method for reading data from a selected cell.
[0002]
[Prior art]
FIG. 9 is a diagram showing a conventional circuit example of a NAND-type MROM circuit. The basic signals required in the NAND MROM circuit are a ROM address input signal IAn, a ROM data output signal IDB31, a read control signal RD, a chip select control signal ROMCS, and a stop state control signal TE. Further, in the case of a NAND MROM circuit in a microcomputer system, FPH, PH1, and PH2 of system clock groups are used.
[0003]
FIG. 10 is an operation timing chart of the NAND MROM circuit described above. The NAND-type MROM circuit operates in the order divided by the FPH of the system clock. The T1 period is the address determination / ROMCS determination period, the T2 period is the precharge period, the T3 period is the MROM data determination period, and the T4 period is the MROM data. The LATCH period and the T5 period operate in the order of the reading period to the system bus.
[0004]
The detailed operation of the NAND MROM circuit will be described below with reference to FIG. MROM circuit operation in the state where the stop state control signal TE is “1” and the system clocks FPH, PH1, PH2 (FIGS. 10A, 10B, 10C) are supplied to the control circuit 1. It becomes possible. At this time, a chip select control signal ROMCS (FIG. 10E) indicating a ROM address area created from the CPU address bus signal is input to the control circuit 1 separately. The chip select control signal ROMCS is also input to CL7-0 generation circuit 2 and DIS1-0 generation circuit 5.
[0005]
As a result, the control circuit 1 generates a precharge control signal PRE “1” (FIG. 10K), and outputs the signals HA0 to HA3 decoded from the ROM address input signal IAn (FIG. 10G). In this case, since the signal HA0 is “1”, the output PRCV of the NAND 6 becomes “0” (FIG. 10L), and the P-type transistor 7 is turned on. At this time, DIS0 generated from the generation circuit 5 of DIS1-0 is "0" (FIG. 10M), so the transistor 10 is off.
[0006]
On the other hand, at this time, the CL7-0 generating circuit 2 generates addresses CL0-CL7 from the ROM address input IAn signal (FIG. 10H), and the SELn-0 generating circuit 3 receives the select signals SEL0-SEL0 from the ROM address input signal IAn. SELn is generated (FIG. 10 (I)), and the WL7-0 generation circuit 4 generates word line signals WL0-WL7 from the ROM address input signal IAn (FIG. 10 (J)).
[0007]
In this example, since the address signal CL0 is “1” and the other CLs are “0”, the transistor 8 is turned on, and the SELn to 0 generation circuit 3 has the select signal SELn “1” and the other SEL0s Since it is “0”, the transistor 9 is turned on. At this time, the WL7-0 generation circuit 4 inputs the word signals WL0-WL7 to the transistor group of the memory cell 9-1 selected by SELn, and turns these transistors on and off.
[0008]
In this example, WL0 is “0”, the other WL is “1”, and there is connection data between the drain and source of the transistor 91 on the WL0 line. Turn on. As a result, VDD is applied to all of the transistor groups of the memory cell 9-1 through the transistors 7, 8, and 9. As a result, PREBIT of the drain line of the transistor 8 becomes “1”, and this “1” is held in the holding circuit including the NAND 12, the clocked inverter 13, and the inverter 14, thereby turning on the transistor 11.
[0009]
Thereafter, when the precharge control signal PRE becomes “0”, the output PRCV of the NAND 6 becomes “0”, the transistor 7 is turned off, and the signal DIS0 of the DIS1-0 generation circuit 5 becomes “1”. Thus, the transistor 10 is turned on. As a result, the charge of the BIT line is discharged through the transistor group of the memory cell 9-1 and the charge is discharged through the transistor 8, so that the PREBIT of the data read line becomes “0”. At this time, the VOTV level of the clocked inverter 13 changes from “0” to “1” when the discharge level of the PREBIT line transitions below the threshold value of the clocked inverter 13.
[0010]
Next, the read control signal RD is input to the control circuit 1 during the period T4, and ACTE2 becomes “1” (FIG. 10Q), and VOTV “1” held in the holding circuit described above (FIG. 10). (P)) is input to and held in the latch 15. Next, the IDBn read control signal CSRD generated by the control circuit 1 during the period T5 becomes “1”, and the latch 15 (inverted signal of VOTV) data “0” is output from the tristate buffer 16 to the IDB 31.
[0011]
FIG. 11 is a waveform diagram showing a transition state until the output PRCV of the NAND 6 changes from “0” to “1” and the cell data is determined to be “0” in the process in which it is cut off after the above-described precharge. First, when the memory cell is precharged when PRCV is at a low level “0”, PREBIT of the data read line is set at a high level “1”. Thereafter, when the PRCV returns to the high level and the precharge is terminated, the discharge occurs through the memory cell, and the PREBIT gradually falls from the high level to the low level.
[0012]
When PREBIT falls to a certain level, VOTV, which is the output of the holding circuit, rises from a low level, and VOTV goes to a high level. When VOTV goes high, the cell data is fixed to “0”. At this time, BIT, which is the potential on the drain side of the transistor 8, also gradually decreases to a low level. This tendency becomes prominent when the parasitic capacitance CBIT of the bit line 60 increases or operates at a low voltage, and the data reading speed of the MROM circuit becomes increasingly slower.
[0013]
[Problems to be solved by the invention]
In the conventional NAND-type MROM circuit described above, in the transition state from when the precharge is terminated until the cell data is determined to be “0”, the falling of the BIT signal and PREBIT signal is slow as shown in FIG. Since the VOTV fixed time = 18.3 nsec and the delay amount are large, there is a problem that it cannot be used in a high-speed microcomputer system.
[0014]
In the conventional circuit example, since the fall of the PREBIT signal is gradual, the GND level float max = 0.5V and the VDD level float max = 0.5V of the input VOTV of the latch 15, and the clocked inverter of the holding circuit There was a problem that the leakage current after 13 increased.
[0015]
Further, in the conventional circuit example, since the rise of the output VOTV of the clocked inverter 13 of the holding circuit is gentle, there is a problem that the data setup time of the latch 15 is greatly reduced.
[0016]
The conventional NAND system circuit example described above has a fatal problem that the speed is significantly inferior to about 1/4 of the NOR system MROM circuit.
[0017]
The present invention has been made in order to solve the above-described conventional problems, and its purpose is to greatly shorten the time until the cell data “0” is determined after the precharge is completed and to greatly increase the data setup time. An object of the present invention is to provide an MROM circuit and a cell data determination method capable of realizing reduction, improving the operation speed, and suppressing leakage current.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized in that after precharging a selected cell among a plurality of cells, cell data is read from the selected cell by a BIT signal by stopping the precharge. in MROM circuit NAND type, is connected to the cell data read line connected to the transistor for selecting the cell, the cell data read line when changing from the high level to the low level, pull out charges from the cell data read line A speed-up circuit, and a holding circuit for holding a PREBIT signal, which is a potential on the cell data read line , wherein the speed-up circuit controls the precharge signal and the cell data read line. a NOR circuit which takes the NOR of the above signal, the cell data read And is composed of a transistor which is turned on and off by the output of the NOR circuit is inserted between the line and the ground potential, operates other than the precharge period and outputs the PREBIT signal to the cell data readout line, said holding circuit Includes a clocked inverter that selectively inverts the PREBIT signal, an inverter that inverts an output from the clocked inverter, a NAND circuit that takes a NAND of the selection signal and the output of the inverter, and an output of the NAND circuit by being constituted by an on-off and the transistor for supplying said PREBIT signal to the cell data readout line, the circuit threshold value of the NOR circuit is the circuit threshold value or more of said clocked inverter of said holding circuit of said PREBIT signal There is.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration according to an embodiment of an MROM circuit of the present invention. The MROM circuit of this example includes a control circuit 1, CL7-0 generation circuit 2, SELn-0 generation circuit 3, WL7-0 generation circuit 4, DIS1-0 generation circuit 5, NAND6, transistors 7, 8, and memory cell 9- 1, 9-2,..., Transistors 10 and 11, a clocked inverter 13 that constitutes a signal holding circuit, an inverter 14, a NAND 12, an MROM data latch circuit 15, an output buffer 16, and a speed-up circuit 30. The speed-up circuit 30 includes a NOR 18 and an N-type transistor 17, and is connected to a cell data read line (PREBIT line) 22 and a precharge line 21.
[0024]
The detailed configuration examples of the control circuit 1, CL7-0 generation circuit 2, SELn-0 generation circuit 3, WL7-0 generation circuit 4, and DIS1-0 generation circuit 5 shown in FIG. 4, 5, and 6.
[0025]
Next, the operation of this embodiment will be described with reference to the timing chart of FIG. The NAND-type MROM circuit operates in the order divided by the system clock FPH (FIG. 7A). The T1 period is the address determination / ROMCS determination period, the T2 period is the precharge period, and the T3 period is the MROM data determination. The period T4 operates in the order of the MROM data LATCH period, and the period T5 reads in the system bus reading period.
[0026]
In the state where the stop state control signal TE is “1” and the system clocks FPH, PH1, and PH2 are supplied to the control circuit 1 as shown in FIGS. 7 (A), (B), and (C), the MROM Circuit operation becomes possible. At this time, a chip select control signal ROMCS (FIG. 7E) indicating a ROM address area generated from the CPU address bus signal is input to the control circuit 1 separately. This chip select control signal ROMCS is also input to CL7-0 generating circuit 2 and DIS1-0 generating circuit 5.
[0027]
As a result, the control circuit 1 generates a precharge control signal PRE “1” (FIG. 7K) and outputs the signals HA0 to HA3 decoded from the ROM address input signal IAn. In this case, since the signal HA0 is “1”, the output PRCV (FIG. 7L) of the NAND 6 becomes “0”, and the P-type transistor 7 is turned on. At this time, DIS0 generated from the generation circuit 5 of DIS1-0 is "0", so that the transistor 10 is off.
[0028]
On the other hand, CL7-0 generating circuit 2 generates addresses CL0-CL7 (FIG. 7H) from ROM address input signal IAn, and SELn-0 generating circuit 3 selects select signals SEL0-SEL0 from ROM address input signal IAn. SELn (FIG. 7 (I)) is generated, and WL7-0 generation circuit 4 generates word line signals WL0-WL7 (FIG. 7 (J)) from ROM address input signal IAn.
[0029]
In this example, since the address signal CL0 is “1” and the other CLs are “0”, the transistor 8 is turned on, and the SELn to 0 generation circuit 3 has the select signal SELn “1” and the other SEL0s Since it is “0”, the transistor 9 is turned on. At this time, the WL7-0 generation circuit 4 inputs the word signals WL0-WL7 to the transistor group of the memory cell 9-1 selected by SELn, and turns these transistors on and off.
[0030]
In this example, WL0 is “0”, the other WL is “1”, and there is connection data between the drain and source of the transistor 91 on the WL0 line. Turn on. As a result, VDD is applied to all of the transistor groups of the memory cell 9-1 through the transistors 7, 8, and 9. Therefore, PREBIT (FIG. 7 (O)) of the drain line of the transistor 8 becomes “1”, and this “1” is held in the holding circuit including the NAND 12, the clocked inverter (receiving circuit) 13, and the inverter 14. Thereby, the transistor 11 is turned on.
[0031]
Thereafter, when the precharge control signal PRE becomes “0”, the output PRCV of the NAND 6 becomes “0”, the transistor is turned off, and the signal DIS0 of the DIS1-0 generation circuit 5 becomes “1”. The transistor 10 is turned on. As a result, the charge of the BIT line is discharged through the transistor group of the memory cell 9-1 and the charge is discharged through the transistor 8, so that the PREBIT of the memory cell data read line becomes “0”. At this time, the VOTV level of the clocked inverter 13 changes from “0” to “1” when the discharge level of the PREBIT line transitions below the threshold value of the NOR 18 of the speed-up circuit 30.
[0032]
Next, the read control signal RD (FIG. 7F) is input to the control circuit 1 during the period T4, and ACTE2 (FIG. 7R) becomes “1”, and is held in the memory circuit described above. VOTV (FIG. 7 (Q)) “1” is input to the latch 15 and held. Next, the IDBn read control signal CSRD (FIG. 7 (S)) generated by the control circuit 1 during the period T5 becomes “1”, and the latch 15 (VOTV inversion signal) data “0” is received from the tristate buffer 16. It is output to IDB31.
[0033]
Here, the operation of the high speed circuit 30 will be described. During the precharge period, the input connected to the cell data read line 22 of the NOR 18 of the acceleration circuit 30 is “1”, and the input connected to the line 21 is also “1”. It is. Therefore, the transistor 17 is turned off and does not affect the above operation. Thereafter, when the precharge is terminated, the input connected to the line 21 of the NOR 18 becomes “0”, but the input connected to the cell data read line 22 reads “0” from the selected memory cell. When it is done, it becomes “0”. As a result, the output CNT of the NOR 18 becomes “1”, the transistor 17 is turned on, and the line 22 is rapidly brought to a low level. When “1” is read from the memory cell, the CNT that is the output of the NOR 18 remains “0”, so that the transistor 17 is kept off.
[0034]
FIG. 8 is a waveform diagram showing a transition state until the output PRCV of the NAND 6 changes from “0” to “1” and the cell data is determined to be “0” in the process where it is cut off after the above-described precharge. First, when the memory cell is precharged when PRCV is low level “0”, PREBIT of the cell data read line 22 becomes high level “1”. After that, when the PRCV returns to the high level and the precharge is cut off, the discharge occurs through the memory cell, and the PREBIT gradually falls from the high level to the low level at first. The transistor 17 of the circuit 30 is turned on and suddenly goes to a low level. When PREBIT goes to a low level rapidly, VOTV, which is the output of the memory circuit, rises rapidly from the low level and immediately goes to a high level. When VOTV goes high, the cell data is fixed to “0”. At this time, BIT that is the potential on the source side of the transistor 8 also rapidly drops to a low level.
[0035]
As described above, FIG. 2 is a detailed diagram of the control circuit 1, but in this example, PRE, ACTE2 signals are created from TE, PH1, PH2, FPH, ROMCS by a simple circuit of NAND41, 42, AND43, By these signals, precharge on / off and latch 15 are controlled, and data is read from the memory cell. That is, since ROMCS and TE are “1”, when PH1 is “1”, FPH is “1” and NAND41 is “0”, NAND42 is “1” and PRE is “1”. Precharge. When FPH, TE, PH2, and ROMCS are “1”, AND 43 is “1” and ACTE 2 is “1”. 3 to 6 is the same as the conventional circuit diagram.
[0036]
According to the present embodiment, when PREBIT changes in the “0” direction after the precharge is cut off, the line 21 is rapidly set to the low level by the speed-up circuit 30, so the precharge is cut off. From this time, the time until the cell data is determined to be “0” can be greatly shortened. Therefore, the data setup time of the latch 15 of the clocked inverter 13 output can be greatly reduced, and the data reading speed can be remarkably improved. Further, even when the parasitic capacitance CBIT of the bit line 60 is increased or the operation is performed at a low voltage, the data read speed of the MROM circuit can be increased by the high-speed circuit 30 and used in a microcomputer that requires high-speed operation. It is possible to do.
[0037]
Here, in this example, the time difference of the fixed time of the MROM data “0” can be adjusted by increasing the threshold difference between the circuit threshold value VTHC2 of the NOR 18 and the threshold value VTHC1 of the clocked inverter 13 as compared with the conventional circuit. . For example, under the conditions of VTHC2≈VTHC1, VDD = 3.0V, VTHP / N = H / L, Ta = 85 ° C., CBIT = 0.55pF (equivalent to 512KB), the fixed time for 6.4n seconds should be shortened. Can do. Furthermore, by setting the threshold value VTHC2 of NOR18> the threshold value VTHC1 of the clocked inverter 13, the operation timing of the high-speed circuit 30 can be advanced and the determination time of the MROM data “0” can be greatly shortened. However, if the operation timing of the speed-up circuit 30 is made too early, the speed-up circuit 30 is operated by a slight change in the PREBIT line, which may cause a malfunction.
[0038]
Further, since the fall of the BIT signal and PREBIT signal becomes steep, the floating time from the GND level of the clocked inverter 13 can be shortened, and the leakage current during this period can be reduced.
[0039]
Furthermore, the scale of the circuit portion for creating the PRE and ACTE2 signals in the control circuit 1 can be simplified as shown in FIG.
[0040]
In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can implement also with another various form in a concrete structure, a function, an effect | action, and an effect.
[0041]
【The invention's effect】
As described above in detail, according to the present invention, by inserting a speed-up circuit in the cell data read line, the time until the cell data is determined to be “0” after the precharge is cut off can be greatly shortened. At the same time, since the data setup time can be greatly reduced, the data reading speed can be improved. Furthermore, the leakage current after the latch circuit of the MROM data can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration according to an embodiment of an MROM circuit of the present invention.
2 is a circuit diagram showing a detailed configuration example of a control circuit shown in FIG. 1; FIG.
3 is a circuit diagram showing a detailed configuration example of a CL7-0 generation circuit shown in FIG. 1; FIG.
4 is a circuit diagram showing a detailed configuration example of a SELn to 0 generation circuit shown in FIG. 1; FIG.
5 is a circuit diagram showing a detailed configuration example of the WL7-0 generation circuit shown in FIG. 1; FIG.
6 is a circuit diagram showing a detailed configuration example of a DIS1-0 generation circuit shown in FIG. 1; FIG.
7 is a timing chart showing a read operation of the MROM circuit shown in FIG. 1. FIG.
FIG. 8 is a waveform diagram showing operations up to cell data determination in the process of precharging the MROM circuit shown in FIG.
FIG. 9 is a block diagram showing a configuration example of a conventional NAND MROM circuit.
10 is a timing chart showing a read operation of the MROM circuit shown in FIG. 9;
11 is a waveform diagram showing an operation until pre-charging of the MROM circuit shown in FIG. 9 and cell data determination in the process of cutting off.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Control circuit 2 CL7-0 generation circuit 3 SELn-0 generation circuit 4 WL7-0 generation circuit 5 DIS1-0 generation circuit 6, 12 NAND
7, 8, 9, 10, 11, 91 Transistors 9-1, 9-2,... Memory cell 13 Clocked inverter 14 Inverter 15 MROM data latch circuit 16 Output buffer 17 N-type transistor 18 NOR
21 Precharge line 22 Cell data read line (PREBIT line)
30 High-speed circuit 60 Bit line (BIT line)

Claims (2)

In a NAND-type MROM circuit that reads out cell data from the selected cell by a BIT signal by precharging the selected cell of the plurality of cells and then stopping the precharging.
Is connected to the cell data read line connected to the transistor for selecting the cell, when the cell data read line is changed from high level to low level, and high speed circuit to pull charge from the cell data read line,
A holding circuit for holding a PREBIT signal that is a potential on the cell data read line;
The speed circuit, a NOR circuit which takes the NOR precharge signal and the cell data readout line on signal for controlling the pre-charge, of the NOR circuit is inserted between the cell data readout line and a ground potential A transistor that is turned on and off by an output, operates outside the precharge period, and outputs the PREBIT signal to the cell data read line ;
The holding circuit selectively inverts the PREBIT signal, an inverter that inverts an output from the clocked inverter, a NAND circuit that takes a NAND of a selection signal and the output of the inverter, and the NAND A transistor that turns on and off according to the output of the circuit and supplies the PREBIT signal to the cell data read line;
The circuit threshold value of the NOR circuit, MROM circuit wherein said PREBIT is signal the holding circuit and the clocked inverter circuit above the threshold of. 2. The MROM circuit according to claim 1, wherein the determination timing of the BIT signal and PREBIT signal is significantly shortened by advancing the operation timing of the speed-up circuit.

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