JP4019451B2 - Harmonic mixer circuit - Google Patents

Description

【００２６】
また、抵抗素子２１の両端間に得られる第２の信号Ｓ２についての分圧成分Ｓｄである乗算出力信号の電圧Ｖｄｐ(t) は、理想的には下記の数８のようにあらわされる。
【００２７】
【数８】

【００２８】
上記数８において、ｎ＝１とされるとき、第１の信号Ｓ１の周波数の２倍の周波数を有する信号と第２の信号Ｓ２との乗算出力信号が得られ、第２の信号Ｓ２が帯域信号である場合には、そのベースバンド信号が乗算出力信号として得られる。
【００２９】
【発明が解決しようとする課題】
上述の図５に示される従来提案されている高調波ミキサー回路は、その構成において、逆向きとされた一対のダイオード１１とダイオード１２との並列接続の両端部に、短絡スタブ１５と開放スタブ１６とが夫々接続されているので、その全体の集積回路化には適していない。即ち、短絡スタブ１５及び開放スタブ１６の夫々は、第１の信号Ｓ１の波長の１／４に相当する長さを有するものとされるが、第１の信号Ｓ１が、例えば、携帯無線電話システムに用いられている準マイクロ波とされる場合にあっても、短絡スタブ１５及び開放スタブ１６の長さは比較的大とされることになり、短絡スタブ１５及び開放スタブ１６を含めた高調波ミキサー回路全体を集積回路化することが困難とされるのである。
【００３０】
また、図５に示される従来提案されている高調波ミキサー回路にあっては、第１の信号Ｓ１の振幅ｖ１が、例えば、√２・Ｖｆ（Ｖｆはダイオード１１及び１２の夫々の順方向電圧）とされているが、順方向電圧Ｖｆは、通常、例えば、−１．５ｍＶ／℃程度の温度係数を伴うものとなる。従って、仮に順方向電圧値Ｖｆの温度係数が−１．５ｍＶ／℃であるとすると、例えば、−２０℃から８０℃までの温度変化範囲においては、順方向電圧Ｖｆが１５０ｍＶも変化してしまうことになる。斯かるもとにあっては、例えば、低温時あるいは高温時において、図６に示される如くの、第２の信号Ｓ２に対しての信号源インピーダンス１９と抵抗素子２１（ダイオード１１とダイオード１２との並列接続）とによる分圧回路における抵抗素子２１についての分圧比Ｎ(t) が大幅に変動することになって、その波形が、例えば、図８に示される如く、デューティ・ファクタを５０％とする矩形波パルス波形という理想的なものとは著しく異なったものとされる。その結果、抵抗素子２１の両端間に得られる第２の信号Ｓ２についての分圧成分Ｓｄ、即ち、チョークコイル２０を通じて出力端子２２に導出される乗算出力信号に関する周波数変換利得が低下してしまうという不都合が生じる。
【００３１】
斯かる点に鑑み、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明は、第１の信号と第２の信号とが供給されて、第１の信号の周波数の２倍の周波数を有した信号と第２の信号との乗算出力信号が得られるものとされるにあたり、全体の集積回路化に好適であって、かつ、温度変化の影響を受け難いものとされる高調波ミキサー回路を提供する。
【００３２】
【課題を解決するための手段】
本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路は、エミッタが共通接続されて第１の差動対を形成する第１及び第２のトランジスタ，エミッタが共通接続されて第２の差動対を形成する第３及び第４のトランジスタ，エミッタが共通接続されて第３の差動対を形成する第５及び第６のトランジスタ、及び、エミッタが共通接続されて第４の差動対を形成する第７及び第８のトランジスタが設けられ、第１及び第５のトランジスタの夫々のベースが共通接続されて形成される第１の共通接続点と第２及び第６のトランジスタの夫々のベースが共通接続されて形成される第２の共通接続点との間に、第１の信号の電圧から所定のオフセット電圧が減じられて得られる電圧が供給されるとともに、第３及び第７のトランジスタの夫々のベースが共通接続されて形成される第３の共通接続点と第４及び第８のトランジスタの夫々のベースが共通接続されて形成される第４の共通接続点との間に、第１の信号の電圧に所定のオフセット電圧が加えられて得られる電圧が供給され、また、第１及び第２のトランジスタの共通接続されたエミッタ及び第３及び第４のトランジスタの共通接続されたエミッタが、各々が第２の信号によって変調されて得られる一対の差動電流である、第２の信号の電圧が大である程大とされる第１の電流と第２の信号の電圧が大である程小とされる第２の電流とを、夫々生じさせる第１及び第２の電流端子の一方及び他方に夫々接続されるとともに、第５及び第６のトランジスタの共通接続されたエミッタ及び第７及び第８のトランジスタの共通接続されたエミッタが、各々が第２の信号によって変調されて得られる一対の差動電流である、第２の信号の電圧が大である程小とされる第３の電流と第２の信号の電圧が大である程大とされる第４の電流とを、夫々生じさせる第３及び第４の電流端子の一方及び他方に夫々接続されて、第１及び第２のトランジスタの共通接続されたエミッタが第１の電流端子に接続されるとき、第５及び第６のトランジスタの共通接続されたエミッタが第３の電流端子に接続され、第１及び第２のトランジスタの共通接続されたエミッタが第２の電流端子に接続されるとき、第５及び第６のトランジスタの共通接続されたエミッタが第４の電流端子に接続される状態がとられる。そして、斯かるもとで、第１，第４，第６及び第７のトランジスタの夫々のコレクタが共通接続されて形成される第５の共通接続点、及び、第２，第３，第５及び第８のトランジスタの夫々のコレクタが共通接続されて形成される第６の共通接続点が、第１の信号の周波数の２倍の周波数を有した信号と第２の信号との乗算出力信号が得られる出力端子とされる。
【００３３】
このように構成される本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路にあっては、第１の差動対を形成する第１及び第２のトランジスタの共通接続されたエミッタ、及び、第２の差動対を形成する第３及び第４のトランジスタの共通接続されたエミッタに、各々が第２の信号によって変調された第１の電流及び第２の電流の一方及び他方が夫々流れるとともに、第３の差動対を形成する第５及び第６のトランジスタの共通接続されたエミッタ、及び、第４の差動対を形成する第７及び第８のトランジスタの共通接続されたエミッタに、各々が第２の信号によって変調された第３の電流及び第４の電流の一方及び他方が夫々流れ、その際、第１及び第２のトランジスタの共通接続されたエミッタに第１の電流が流れるとき、第５及び第６のトランジスタの共通接続されたエミッタに第３の電流が流れ、第１及び第２のトランジスタの共通接続されたエミッタに第２の電流が流れるとき、第５及び第６のトランジスタの共通接続されたエミッタに第４の電流が流れる状態とされる。そして、第１及び第５のトランジスタの夫々のベースが共通接続されて形成される第１の共通接続点と第２及び第６のトランジスタの夫々のベースが共通接続されて形成される第２の共通接続点との間に、第１の信号の電圧から所定のオフセット電圧が減じられて得られる電圧が供給され、また、第３及び第７のトランジスタの夫々のベースが共通接続されて形成される第３の共通接続点と第４及び第８のトランジスタの夫々のベースが共通接続されて形成される第４の共通接続点との間に、第１の信号の電圧から所定のオフセット電圧が減じられて得られる電圧が供給される。
【００３４】
それにより、第１の差動対を形成する第１及び第２のトランジスタのうちの第１のトランジスタ，第２の差動対を形成する第３及び第４のトランジスタのうちの第４のトランジスタ，第３の差動対を形成する第５及び第６のトランジスタのうちの第６のトランジスタ、及び、第４の差動対を形成する第７及び第８のトランジスタのうちの第７のトランジスタの夫々のコレクタ電流の総和と、第１の差動対を形成する第１及び第２のトランジスタのうちの第２のトランジスタ，第２の差動対を形成する第３及び第４のトランジスタのうちの第３のトランジスタ，第３の差動対を形成する第５及び第６のトランジスタのうちの第５のトランジスタ、及び、第４の差動対を形成する第７及び第８のトランジスタのうちの第８のトランジスタの夫々のコレクタ電流の総和との差の電流は、第１の信号の周波数の２倍の周波数を有する信号と第２の信号との乗算結果をあらわすものとされる。そして、この第１，第４，第６及び第７のトランジスタの夫々のコレクタ電流の総和と第２，第３，第５及び第８のトランジスタの夫々のコレクタ電流の総和との差の電流は、一対の出力端子に導出される。
【００３５】
従って、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路にあっては、第１の信号が所定のオフセット電圧を伴って供給されるとともに第２の信号が供給されて、一対の出力端子に、第１の信号の周波数の２倍の周波数を有した信号と第２の信号との乗算出力信号が得られることになる。そして、第１の信号が、第１の差動対を形成する第１及び第２のトランジスタの共通接続されたエミッタ，第２の差動対を形成する第３及び第４のトランジスタの共通接続されたエミッタ，第３の差動対を形成する第５及び第６のトランジスタの共通接続されたエミッタ、及び、第４の差動対を形成する第７及び第８のトランジスタの共通接続されたエミッタを夫々流れる電流を変調する事態は生じないことになり、第１〜第４の作動対において自己検波による干渉が生じるという問題はない。
【００３６】
このような本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路は、開放スタブ及び短絡スタブのいずれも備える必要がないので、その全体の集積回路化に好適である。また、所定のオフセット電圧はダイオードの順方向電圧とは無関係に設定され、それにより、ダイオードの順方向電圧の温度変化により周波数変換利得が低下してしまうという問題は生じない。
【００３７】
【発明の実施の形態】
図１は、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路の一例を示す。
【００３８】
図１に示される例においては、エミッタが共通接続されて第１の差動対を形成する第１のトランジスタ３１及び第２のトランジスタ３２，エミッタが共通接続されて第２の差動対を形成する第３のトランジスタ３３及び第４のトランジスタ３４，エミッタが共通接続されて第３の差動対を形成する第５のトランジスタ３５及び第６のトランジスタ３６、及び、エミッタが共通接続されて第４の差動対を形成する第７のトランジスタ３７及び第８のトランジスタ３８が設けられている。これらの第１〜第８のトランジスタ３１〜３８は、それらのいずれもがＮＰＮ形とされており、また、各々のエミッタ領域面積が実質的に等しくされている。
【００３９】
第１の差動対を形成する第１及び第２のトランジスタ３１及び３２と第３の差動対を形成する第５及び第６のトランジスタ３５及び３６とについて、第１のトランジスタ３１のベースと第５のトランジスタ３５のベースとが共通接続されて第１の共通接続点が形成されるとともに、第２のトランジスタ３２のベースと第６のトランジスタ３６のベースとが共通接続されて第２の共通接続点が形成される。また、第２の差動対を形成する第３及び第４のトランジスタ３３及び３４と第４の差動対を形成する第７及び第８のトランジスタ３７及び３８とについて、第３のトランジスタ３３のベースと第７のトランジスタ３７のベースとが共通接続されて第３の共通接続点が形成されるとともに、第４のトランジスタ３４のベースと第８のトランジスタ３８のベースとが共通接続されて第４の共通接続点が形成される。そして、第１の共通接続点と第２の共通接続点との間に、第１の信号Ｓ１を発する信号源４０とオフセット電圧Ｖｋを供給する直流電源４１とが直列に接続されている。また、第３の共通接続点と第４の共通接続点との間に、信号源４０とオフセット電圧Ｖｋを供給する直流電源４２とが直列に接続されている。
【００４０】
第１の信号Ｓ１は、例えば、周波数ω１を有した正弦波信号であって、その電圧Ｖ１(t) は前述の数１によりあらわされるものとされる。そして、第１の共通接続点と第２の共通接続点との間に配された信号源４０と直流電源４１とは、信号源４０が発する第１の信号Ｓ１の電圧Ｖ１(t) から直流電源４１が供給するオフセット電圧Ｖｋが減じられることになる極性をもって、直列接続されている。それにより、第１及び第２のトランジスタ３１及び３２の各々のベース間及び第５及び第６のトランジスタ３５及び３６の各々のベース間の夫々には、第１の信号Ｓ１の電圧Ｖ１(t) からオフセット電圧Ｖｋが減じられて得られる電圧が供給されることになる。
【００４１】
一方、第３の共通接続点と第４の共通接続点との間に配された信号源４０と直流電源４２とは、信号源４０が発する第１の信号Ｓ１の電圧Ｖ１(t) に直流電源４２が供給するオフセット電圧Ｖｋが加えられることになる極性をもって、直列接続されている。それにより、第３及び第４のトランジスタ３３及び３４の各々のベース間及び第７及び第８のトランジスタ３７及び３８の各々のベース間の夫々には、第１の信号Ｓ１の電圧Ｖ１(t) にオフセット電圧Ｖｋが加えられて得られる電圧が供給されることになる。
【００４２】
また、図１に示される例にあっては、第２の信号Ｓ２を発する信号源４４が接続された電流源部４５と電流源部４６とが設けられている。第２の信号Ｓ２は、例えば、第１の信号Ｓ１の周波数ω１の２倍に相当する周波数ω２を有した正弦波信号であって、その電圧Ｖ２(t) は前述の数２によりあらわされるものとされる。
【００４３】
電流源部４５は、電流端子４５Ａ及び４５Ｂを有しており、信号源４４が発する第２の信号Ｓ２によって変調される一対の差動電流である電流Ｉ１及び電流Ｉ２を、電流端子４５Ａ及び４５Ｂに夫々生じさせる。電流Ｉ１と電流Ｉ２とは、電流Ｉ１が第２の信号Ｓ２の電圧Ｖ２(t) が大である程大とされるとき、電流Ｉ２が第２の信号Ｓ２の電圧Ｖ２(t) が大である程小とされる関係、あるいは、電流Ｉ１が第２の信号Ｓ２の電圧Ｖ２ (t) が大である程小とされるとき、電流Ｉ２が第２の信号Ｓ２の電圧Ｖ２ (t) が大である程大とされる関係にあるものとされる。
【００４４】
そして、電流源部４５における電流端子４５Ａ及び４５Ｂには、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２の各々における共通接続されたエミッタ、及び、第２の差動対を形成する第３及び第４のトランジスタ３３及び３４の各々における共通接続されたエミッタが、夫々接続されている。それにより、共通接続された第１のトランジスタ３１のエミッタ及び第２のトランジスタ３２のエミッタには電流Ｉ１が分流して流れ、また、共通接続された第３のトランジスタ３３のエミッタ及び第４のトランジスタ３４のエミッタには電流Ｉ２が分流して流れる。
【００４５】
電流源部４６は、電流端子４６Ａ及び４６Ｂを有しており、信号源４４が発する第２の信号Ｓ２によって変調される一対の差動電流である電流Ｉ３及び電流Ｉ４を、電流端子４６Ａ及び４６Ｂに夫々生じさせる。電流Ｉ３と電流Ｉ４とは、電流Ｉ３が第２の信号Ｓ２の電圧Ｖ２(t) が大である程小とされるとき、電流Ｉ４が第２の信号Ｓ２の電圧Ｖ２(t) が大である程大とされる関係、あるいは、電流Ｉ３が第２の信号Ｓ２の電圧Ｖ２ (t) が大である程大とされるとき、電流Ｉ４が第２の信号Ｓ２の電圧Ｖ２ (t) が大である程小とされる関係にあるものとされる。
【００４６】
そして、電流源部４６における電流端子４６Ａ及び４６Ｂには、第３の差動対を形成する第５及び第６のトランジスタ３５及び３６の各々における共通接続されたエミッタ、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８の各々における共通接続されたエミッタが、夫々接続されている。それにより、共通接続された第５のトランジスタ３５のエミッタ及び第６のトランジスタ３６のエミッタには電流Ｉ３が分流して流れ、また、共通接続された第７のトランジスタ３７のエミッタ及び第８のトランジスタ３８のエミッタには電流Ｉ４が分流して流れる。
【００４７】
さらに、図１に示される例にあっては、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２のうちの第１のトランジスタ３１のコレクタ，第２の差動対を形成する第３及び第４のトランジスタ３３及び３４のうちの第４のトランジスタ３４のコレクタ，第３の差動対を形成する第５及び第６のトランジスタ３５及び３６のうちの第６のトランジスタ３６のコレクタ、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８のうちの第７のトランジスタ３７のコレクタが共通接続されて第５の共通接続点が形成され、その第５の共通接続点から出力端子４７Ａが導出されている。また、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２のうちの第２のトランジスタ３２のコレクタ，第２の差動対を形成する第３及び第４のトランジスタ３３及び３４のうちの第３のトランジスタ３３のコレクタ，第４の差動対を形成する第５及び第６のトランジスタ３５及び３６のうちの第５のトランジスタ３５のコレクタ、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８のうちの第８のトランジスタ３８のコレクタが共通接続されて第６の共通接続点が形成され、その第６の共通接続点から出力端子４７Ｂが導出されている。これら出力端子４７Ａ及び４７Ｂは、対を成している。
【００４８】
このようなもとで、電流源部４５と電流源部４６とは、実質的に同等の特性を備えていて、信号源４４からの第２の信号Ｓ２の電圧が０であるとき、電流Ｉ１，Ｉ２，Ｉ３及びＩ４の夫々として直流電流Ｉ０を発生し、また、電流Ｉ１，Ｉ２，Ｉ３及びＩ４の形成にあたっての相互コンダクタンスｇｍを有するものとされる。
【００４９】
電流源部４５における電流端子４５Ａ及び４５Ｂに夫々得られる電流Ｉ１及びＩ２の夫々の値Ｉ１(t) 及びＩ2 (t) と、電流源部４６における電流端子４６Ａ及び４６Ｂに夫々得られる電流Ｉ３及びＩ４の夫々の値Ｉ３(t) 及びＩ４(t) とは、下記の数９によってあらわされる。
【００５０】
【数９】
Ｉ１(t) ＝Ｉ０／２＋ｇｍ・Ｖ２(t)
Ｉ２(t) ＝Ｉ０／２−ｇｍ・Ｖ２(t)
Ｉ３(t) ＝Ｉ０／２−ｇｍ・Ｖ２(t)
Ｉ４(t) ＝Ｉ０／２＋ｇｍ・Ｖ２(t)
【００５１】
第１〜第８のトランジスタ３１〜３８の夫々について、そのコレクタ電流をＩｃ，ベース−エミッタ間電圧をＶ_BE, 逆方向コレクタ飽和電流をＩｓ，熱電圧をＶ_T （Ｖ_T ＝ｋ・Ｔ／ｑ，ｋはボルツマン係数，Ｔは絶対温度，ｑは電子の単位電荷）とすると、下記の数１０により示される関係が成立する。
【００５２】
【数１０】
Ｉｃ＝Ｉｓ・ exp (Ｖ_BE／Ｖ_T ）
【００５３】
これよりして、第１〜第８のトランジスタ３１〜３８の夫々についてのコレクタ電流Ｉｃ１(t) ，Ｉｃ２(t) ，Ｉｃ３(t) ，Ｉｃ４(t) ，Ｉｃ５(t) ，Ｉｃ６(t) ，Ｉｃ７(t) 及びＩｃ８(t) は、下記の数１１によってあらわされる。
【００５４】
【数１１】
Ｉｃ１(t) ＝ Ｉ１(t) ／〔１＋ exp｛−（Ｖ１(t) −Ｖｋ）／Ｖ_T ｝〕
Ｉｃ２(t) ＝ Ｉ１(t) ／〔１＋ exp｛（Ｖ１(t) −Ｖｋ）／Ｖ_T ｝〕
Ｉｃ３(t) ＝ Ｉ２(t) ／〔１＋ exp｛（Ｖ１(t) ＋Ｖｋ）／Ｖ_T ｝〕
Ｉｃ４(t) ＝ Ｉ２(t) ／〔１＋ exp｛−（Ｖ１(t) ＋Ｖｋ）／Ｖ_T ｝〕
Ｉｃ５(t) ＝ Ｉ３(t) ／〔１＋ exp｛−（Ｖ１(t) −Ｖｋ）／Ｖ_T ｝〕
Ｉｃ６(t) ＝ Ｉ３(t) ／〔１＋ exp｛（Ｖ１(t) −Ｖｋ）／Ｖ_T ｝〕
Ｉｃ７(t) ＝ Ｉ４(t) ／〔１＋ exp｛（Ｖ１(t) ＋Ｖｋ）／Ｖ_T ｝〕
Ｉｃ８(t) ＝ Ｉ４(t) ／〔１＋ exp｛−（Ｖ１(t) ＋Ｖｋ）／Ｖ_T ｝〕
【００５５】
出力端子４７Ａには、コレクタ電流Ｉｃ１(t) ，Ｉｃ４(t) ，Ｉｃ６(t) 及びＩｃ７(t) の和が流れ、出力端子４７Ｂには、コレクタ電流Ｉｃ２(t) ，Ｉｃ３(t) ，Ｉｃ５(t) 及びＩｃ８(t) の和が流れる。従って、一対の出力端子４７Ａ及び４７Ｂに得られる差動出力電流Ｉｃd(t)は、下記の数１２によりあらわされる。
【００５６】
【数１２】
Ｉｃd(t)＝（Ｉｃ１(t) ＋Ｉｃ４(t) ＋Ｉｃ６(t) ＋Ｉｃ７(t) ）
−（Ｉｃ２(t) ＋Ｉｃ３(t) ＋Ｉｃ５(t) ＋Ｉｃ８(t) ）
＝２・ｇｍ・Ｖ２(t)
・〔 tanh｛（Ｖ１(t) −Ｖｋ）／２・Ｖ_T ｝
−tanh｛（Ｖ１(t) ＋Ｖｋ）／２・Ｖ_T ｝〕
【００５７】
ここで、上記数１２における tanh の項を下記の数１３に示される如くの、第１の信号Ｓ１の電圧Ｖ１(t) とオフセット電圧Ｖｋとの関数Ｆ｛Ｖ１(t) ，Ｖｋ｝とする。
【００５８】
【数１３】
Ｆ｛Ｖ１(t) ，Ｖｋ｝＝ tanh｛（Ｖ１(t) −Ｖｋ）／２・Ｖ_T ｝
−tanh｛（Ｖ１(t) ＋Ｖｋ）／２・Ｖ_T ｝
【００５９】
関数Ｆ｛Ｖ１(t) ，Ｖｋ｝は、例えば、図２に示される如く、オフセット電圧ＶｋがＶ_T の４倍以上の場合、第１の信号Ｓ１の電圧Ｖ１(t) の負から正への変化に伴って、０と−２との間を２回遷移する。そして、第１の信号Ｓ１は周波数ω１を有した正弦波信号であるので、関数Ｆ｛Ｖ１(t) ，Ｖｋ｝は、図３において実線により示される如くに、周波数ω１の２倍の周波数をもって変化する。
【００６０】
例えば、第１の信号Ｓ１の振幅ｖ１が、オフセット電圧Ｖｋの√２倍（ｖ１＝√２・Ｖｋ）に選定され、オフセット電圧ＶｋがＶ_T の２倍より十分に大であるようにされると、数１３によってあらわされる関数Ｆ｛Ｖ１(t) ，Ｖｋ｝は、０と−２との間の値を繰り返しとることになる。そして、第２の信号Ｓ２は周波数ω２を有した正弦波信号であるので、数１２によってあらわされる差動出力電流Ｉｃd(t)は、下記の数１４に示されるフーリエ級数をもってあらわされる。
【００６１】
【数１４】

【００６２】
上記数１４において、ｎ＝１とされるとき、差動出力電流Ｉｃd(t)が、第１の信号Ｓ１の周波数の２倍の周波数を有する信号と第２の信号Ｓ２との乗算出力信号として、下記の数１５に示される如くに得られ、第２の信号Ｓ２が帯域信号である場合には、そのベースバンド信号が乗算出力信号として得られる。
【００６３】
【数１５】
Ｉｃd(t)＝８／π・ｇｍ・ｖ２・cos(２・ω１・ｔ) ・cos(ω２・ｔ)
＝４／π・ｇｍ・ｖ２
・〔 cos｛ (２・ω１＋ω２）・ｔ｝
＋ cos｛ (２・ω１−ω２）・ｔ｝〕
−２・ｇｍ・ｖ２・cos(ω２・ｔ)
【００６４】
上述の如くの図１に示される例は、開放スタブ及び短絡スタブのいずれも用いていず、差動対を成す複数のトランジスタ３１〜３８，直流電圧源４１及び４２，電流源部４５及び４６等を含んで構成されているので、その全体の集積回路化に好適である。また、オフセット電圧Ｖｋがダイオードの順方向電圧とは無関係に設定され、ダイオードの順方向電圧に依存しないので、ダイオードの順方向電圧の温度変化により周波数変換利得が低下してしまうという問題は生じない。
【００６５】
【実施例】
図４は、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路の一例についての具体構成例を示す。この図４に示される具体構成例は、図１に示される例における直流電圧源４１及び４２が、２組の差動対を成すトランジスタを含む回路によって構成されたものに相当する。直流電圧源４１及び４２に対応する部分以外の部分は、図１に示される例と同様であり、それらについては、図１と共通の符号を付して示し、重複説明は省略する。
【００６６】
図４に示される具体構成例にあっては、エミッタが共通接続されて差動対を形成するＮＰＮ形のトランジスタ５１及び５２，共通接続されたトランジスタ５１及び５２の夫々のエミッタに接続された電流源５３、及び、トランジスタ５１及び５２の夫々のコレクタに接続された抵抗素子５４，５５及び５６を含んで形成される電圧発生部５７と、エミッタが共通接続されて差動対を形成するＮＰＮ形のトランジスタ６１及び６２，共通接続されたトランジスタ６１及び６２の夫々のエミッタに接続された電流源６３、及び、トランジスタ６１及び６２の夫々のコレクタに接続された抵抗素子６４，６５，６６及び６７を含んで形成される電圧発生部５８とが設けられている。そして、トランジスタ５１及び５２の各々のベース間、及び、トランジスタ６１及び６２の各々のベース間の夫々に、第１の信号Ｓ１を発する信号源４０が共通に接続されている。
【００６７】
トランジスタ５１，５２，６１及び６２の各々は、実質的に同等の特性を有したものとされ、また、電流源５３及び６３の夫々は共に実質的な定電流Ｉｏを発生する。抵抗素子５４，５５、６４及び６５の各々は、実質的に同一の抵抗値Ｒｃを有しており、また、抵抗素子５６及び６６の各々も、実質的に同一の抵抗値Ｒｏを有している。さらに、抵抗素子６７は、抵抗値Ｒｋを有している。なお、図４に示されるＶｃｃは、電源電圧である。
【００６８】
このようなもとで、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２の各々のベース間、及び、第３の差動対を形成する第５及び第６のトランジスタ３５及び３６の各々のベース間には、それらに対して共通に、トランジスタ５２のコレクタとトランジスタ６１のコレクタとの間に得られる電圧が供給される。また、第２の差動対を形成する第３及び第４のトランジスタ３３及び３４の各々のベース間、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８の各々のベース間には、それらに対して共通に、トランジスタ５１のコレクタとトランジスタ６２のコレクタとの間に得られる電圧が供給される。
【００６９】
トランジスタ５２のコレクタとトランジスタ６１のコレクタとの間に得られる電圧は、信号源４０から発せられる第１の信号Ｓ１の電圧Ｖ１(t) に基づく電圧Ｖ１’(t) からオフセット電圧Ｖｋ’が減じられて得られる電圧であり、トランジスタ５１のコレクタとトランジスタ６２のコレクタとの間に得られる電圧は、信号源４０から発せられる第１の信号Ｓ１の電圧Ｖ１(t) に基づく電圧Ｖ１’(t) にオフセット電圧Ｖｋ’が加えられて得られる電圧である。ここで、電圧Ｖ１’(t) は、電圧Ｖ１(t) に比例した電圧であって、下記の数１６によってあらわされ、また、オフセット電圧Ｖｋ’は、下記の数１７によってあらわされる。
【００７０】
【数１６】
Ｖ１’(t) ＝Ｖ１(t) ・（Ｒｃ・Ｉｏ）／（２・Ｖ_T ）
【００７１】
【数１７】
Ｖｋ’＝Ｒｋ・Ｉｏ
【００７２】
このように、図４に示される具体構成例にあっては、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２の各々のベース間、及び、第３の差動対を形成する第５及び第６のトランジスタ３５及び３６の各々のベース間には、それらに対して共通に、数１６によってあらわされる電圧Ｖ１’(t) から数１７によってあらわされるオフセット電圧Ｖｋ’が減じられて得られる電圧が供給され、また、第２の差動対を形成する第３及び第４のトランジスタ３３及び３４の各々のベース間、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８の各々のベース間には、それらに対して共通に、数１６によってあらわされる電圧Ｖ１’(t) に数１７によってあらわされるオフセット電圧Ｖｋ’が加えられて得られる電圧が供給される。
【００７３】
従って、図４に示される具体構成例にあっても、第１の差動対を形成する第１及び第２のトランジスタ３１及び３２の各々のベース間、及び、第３の差動対を形成する第５及び第６のトランジスタ３５及び３６の各々のベース間には、実質的に、信号源４０が発する第１の信号Ｓ１の電圧Ｖ１(t) から所定のオフセット電圧が減じられて得られる電圧が供給されるとともに、第２の差動対を形成する第３及び第４のトランジスタ３３及び３４の各々のベース間、及び、第４の差動対を形成する第７及び第８のトランジスタ３７及び３８の各々のベース間には、実質的に、信号源４０が発する第１の信号Ｓ１の電圧Ｖ１(t) に所定のオフセット電圧が加えられて得られる電圧が供給されることになる。それゆえ、図４に示される具体構成例に備えられた、第１〜第４の差動対を形成する第１〜第８のトランジスタ３１〜３８、及び、電流源部４５及び４６を含んで構成される部分も、図１に示される例の場合と同様な動作を行う。
【００７４】
なお、図４に示される具体構成例が、実際に使用されるに際しては、図１に示される例についての説明において述べられたことからして、電圧Ｖ１’(t) の振幅がオフセット電圧Ｖｋ’の√２倍に選定され、かつ、オフセット電圧Ｖｋ’が、例えば、Ｖ_T の４倍以上とされることが望ましい。
【００７５】
【発明の効果】
以上の説明から明らかな如く、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路にあっては、第１の信号が所定のオフセット電圧を伴って供給されるとともに第２の信号が供給されて、一対の出力端子に、第１の信号の周波数の２倍の周波数を有した信号と第２の信号との乗算出力信号が得られることになり、その際、第１の信号が、第１の差動対を形成する第１及び第２のトランジスタの共通接続されたエミッタ，第２の差動対を形成する第３及び第４のトランジスタの共通接続されたエミッタ，第３の差動対を形成する第５及び第６のトランジスタの共通接続されたエミッタ、及び、第４の差動対を形成する第７及び第８のトランジスタの共通接続されたエミッタを夫々流れる電流を変調する事態は生じないことになり、第１〜第４の作動対において自己検波による干渉が生じるという問題はない。
【００７６】
そして、本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路は、開放スタブ及び短絡スタブのいずれも備える必要がないので、その全体の集積回路化に好適であるとともに、所定のオフセット電圧はダイオードの順方向電圧とは無関係に設定されて、ダイオードの順方向電圧に依存しないので、ダイオードの順方向電圧の温度変化により周波数変換利得が低下してしまうという問題を回避できるものとなる。
【図面の簡単な説明】
【図１】本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路の一例を示す回路接続図である。
【図２】図１に示される例の動作説明に供される特性図である。
【図３】図１に示される例の動作説明に供される特性図である。
【図４】本願の特許請求の範囲における請求項１から請求項４までのいずれかに記載された発明に係る高調波ミキサー回路の一例についての具体構成例を示す回路接続図である。
【図５】従来提案されている高調波ミキサー回路を示す回路接続図である。
【図６】図５に示される高調波ミキサー回路の説明に供される等価回路接続図である。
【図７】図５に示される高調波ミキサー回路の動作説明に供される特性図である。
【図８】図５に示される高調波ミキサー回路の動作説明に供される特性図である。
【符号の説明】
３１，３２，３３，３４，３５，３６，３７，３８，５１，５２，６１，６２トランジスタ ４０，４４ 信号源 ４１，４２ 直流電源 ４５，４６ 電流源部 ４７Ａ，４７Ｂ 出力端子 ５３，６３ 電流源５４，５５，５６，６４，６５，６６，６７ 抵抗素子 ５７，５８電圧発生部[0001]
BACKGROUND OF THE INVENTION
In the invention according to the present application, the first signal and the second signal are supplied, and a multiplication output signal of the signal having the frequency twice the frequency of the first signal and the second signal is obtained. The present invention relates to a wave mixer circuit.
[0002]
[Prior art]
In the field of wireless communication equipment, a reception signal through an antenna and a local oscillation signal having a predetermined frequency are supplied to a mixer circuit, and the mixer circuit supplies the reception signal to the frequency of the difference between the frequency and the frequency of the local oscillation signal. The mainstream is one that performs superheterodyne reception, which converts the signal to an intermediate frequency signal having. Such superheterodyne reception is accompanied by a problem of image interference, and as a countermeasure, it is usually necessary to provide an image suppression filter when superheterodyne reception is performed. This image suppression filter hinders downsizing of the receiving unit in the wireless communication device.
[0003]
Therefore, in order to further reduce the size and weight of the receiving unit in the wireless communication device, the receiving unit uses a mixer circuit that combines a received signal through the antenna and a local oscillation signal having a frequency equal to the carrier frequency of the received signal. It is known that reception is performed by a direct conversion method in which a reception signal is directly converted into a baseband signal by a mixer circuit. When reception by the direct conversion method is performed, it is unnecessary to provide an image suppression filter that is required when superheterodyne reception is performed.
[0004]
However, when reception by the direct conversion method is performed, a local oscillation signal having a frequency equal to the carrier frequency of the reception signal supplied to the mixer circuit together with the reception signal leaks to the antenna side and leaks in the mixer circuit. There is a problem that self-detection due to the local oscillation signal is performed and interference due to self-detection occurs. Therefore, in order to avoid such a problem, when performing reception by the direct conversion method, a mixer circuit that converts a received signal into a baseband signal is supplied with a first signal and a second signal. A harmonic mixer circuit that can obtain a multiplication output signal of a signal having a frequency twice as high as that of the second signal and the second signal is used, and the harmonic mixer circuit has a frequency 1 of the received signal. Proposed to supply a local oscillation signal having a frequency of / 2 as a first signal, supply a reception signal as a second signal, and obtain a baseband signal based on the reception signal as a multiplication output signal Has been.
[0005]
FIG. 5 shows a conventionally proposed harmonic mixer circuit that can be applied to reception by the direct conversion method as described above. The harmonic mixer circuit shown in FIG. 5 includes a pair of diodes 11 and 12 that are opposite to each other and connected in parallel, and one end of the parallel connection of the diode 11 and the diode 12. 13 and the other end 14 are connected to a short-circuit stub 15 and an open stub 16, respectively.
[0006]
Then, the first signal S1 from the signal source 17 is supplied to one end portion 13 of the diode 11 and the diode 12 connected in parallel, and the signal is supplied to the other end portion 14 of the diode 11 and the diode 12 connected in parallel. A second signal S2 from source 18 is provided through signal source impedance 19. At this time, each of the first signal S1 and the second signal S2 is a sine wave signal, and the frequency ω1 of the first signal S1 is ½ of the frequency ω2 of the second signal S2 (ω1 = ω2 / 2), and the lengths of the short-circuit stub 15 and the open stub 16 are selected to correspond to ¼ of the wavelength of the first signal S1, and accordingly, the length of the wavelength of the second signal S2. It corresponds to 1/2.
[0007]
Under such circumstances, the voltage V1 (t) of the first signal S1 and the voltage V2 (t) of the second signal S2 are expressed by the following equations 1 and 2.
[0008]
[Expression 1]
V1 (t) = v1 ・ cos (ω1 ・ t)
[0009]
[Expression 2]
V2 (t) = v2 · cos (ω2 · t)
[0010]
In the above formulas 1 and 2, ω1 = 2 · π · f1, ω2 = 2 · π · f2, and v1 >> v2, for example, the forward voltage of each of the diodes 11 and 12 is defined as Vf. , V1 = √2 · Vf.
[0011]
The short-circuit stub 15 acts as an open line for the first signal S1, and the open stub 16 acts as a short-circuit line for the first signal S1. The first signal S1 supplied to the one end 13 of the parallel connection does not leak to the signal source 18 side connected to the other end 14 of the parallel connection of the diode 11 and the diode 12, and the diode 11 and the diode 12 Between both ends of the parallel connection, that is, between the one end 13 and the other end 14. As a result, the current Idp (t) flowing through the parallel connection of the diode 11 and the diode 12 is expressed by the following equation (3).
[0012]
[Equation 3]
Idp (t) = Is · exp {V1 (t) / V_T} -Is.exp {-V1 (t) / V_T}
[0013]
In Equation 3, Is is the reverse saturation current of each of the diodes 11 and 12, and V_TIs the thermal voltage.
[0014]
The parallel connection of the diode 11 and the diode 12 is considered to be a resistance element whose resistance is dynamically changed, and the dynamic change resistance Rd (t) is expressed by the following equation (4).
[0015]
[Expression 4]
Rd (t) = V1 (t) / Idp (t)
[0016]
On the other hand, the open stub 16 acts as an open line for the second signal S2 having a frequency ω2 that is twice the frequency ω1 of the first signal S1, and the short stub 15 It acts as a short-circuit line for S2. Furthermore, the choke coil 20 exhibits a high impedance with respect to the second signal S2. Therefore, the second signal S 2 supplied to the other end 14 of the parallel connection of the diode 11 and the diode 12 through the signal source impedance 19 flows out to the short-circuit stub 15 through the parallel connection of the diode 11 and the diode 12.
[0017]
Here, when the parallel connection of the diode 11 and the diode 12 is considered as the resistance element 21 having the dynamic change resistance Rd (t), the second signal S2 from the signal source 18 is as shown in FIG. The voltage is supplied to a voltage dividing circuit composed of the signal source impedance 19 and the resistance element 21. Then, the divided voltage component Sd for the second signal S2 obtained between both ends of the resistance element 21 is led to the output terminal 22 through the choke coil 20 as a multiplication output signal.
[0018]
The voltage dividing ratio N (t) for the resistance element 21 in the voltage dividing circuit composed of the signal source impedance 19 and the resistance element 21 is expressed by the following Equation 5, where the value of the signal source impedance 19 is Rs.
[0019]
[Equation 5]
N (t) = Rd (t) / (Rs + Rd (t))
[0020]
Since the dynamic change resistance Rd (t) of the resistance element 21 changes with the frequency (2 · ω1) twice the frequency ω1 of the first signal S1 from the equation (4), the voltage dividing ratio N (t) is also The frequency changes with a frequency (2 · ω1) twice the frequency ω1 of the first signal S1. FIG. 7 shows the voltage division ratio N (t) with a solid line when the resistance value of the signal source impedance 19 is 50Ω, and shows the voltage V1 (t) of the first signal S1 with a broken line.
[0021]
Then, the second signal S2 from the signal source 18 is supplied to the voltage dividing circuit including the signal source impedance 19 and the resistance element 21, whereby the second signal S2 obtained between both ends of the resistance element 21 is divided. The voltage Vdp (t) of the pressure component Sd is expressed by the following formula 6.
[0022]
[Formula 6]
Vdp (t) = V2 (t) N (t)
[0023]
The frequency division ratio N (t) is ideally a signal having a square wave pulse waveform with a frequency of 2 · ω1, that is, twice the frequency ω1 of the first signal S1 and a duty factor of 50%. Therefore, the divided voltage component Sd, that is, the multiplication output signal derived to the output terminal 22 is obtained by multiplying the second signal S2 by a signal having a frequency twice the frequency of the first signal S1. Signal.
[0024]
An ideal rectangular wave pulse waveform with respect to the frequency division ratio N (t) is expressed by the following equation 7 using a Fourier series.
[0025]
[Expression 7]

[0026]
Further, the voltage Vdp (t) of the multiplication output signal, which is the divided voltage component Sd for the second signal S2 obtained between both ends of the resistance element 21, is ideally expressed as in the following equation (8).
[0027]
[Equation 8]

[0028]
  In the above equation 8, when n = 1, a multiplication output signal of a signal having a frequency twice the frequency of the first signal S1 and the second signal S2 is obtained, and the second signal S2ObiReligionIn issueIn some cases, the baseband signal is obtained as a multiplication output signal.
[0029]
[Problems to be solved by the invention]
The above-described conventionally proposed harmonic mixer circuit shown in FIG. 5 has a short-circuit stub 15 and an open stub 16 at both ends of a parallel connection of a pair of diodes 11 and 12 that are reversed in structure. Are connected to each other, and are not suitable for the integrated circuit as a whole. That is, each of the short-circuit stub 15 and the open stub 16 has a length corresponding to ¼ of the wavelength of the first signal S1, and the first signal S1 is, for example, a portable radio telephone system. Even when the quasi-microwave used in the above is used, the lengths of the short-circuit stub 15 and the open stub 16 are relatively large, and the harmonics including the short-circuit stub 15 and the open stub 16 are used. It is difficult to make the entire mixer circuit an integrated circuit.
[0030]
Further, in the conventionally proposed harmonic mixer circuit shown in FIG. 5, the amplitude v1 of the first signal S1 is, for example, √2 · Vf (Vf is the forward voltage of each of the diodes 11 and 12). However, the forward voltage Vf usually has a temperature coefficient of about −1.5 mV / ° C., for example. Therefore, if the temperature coefficient of the forward voltage value Vf is −1.5 mV / ° C., for example, in the temperature change range from −20 ° C. to 80 ° C., the forward voltage Vf changes by 150 mV. It will be. Under such circumstances, for example, at a low temperature or a high temperature, as shown in FIG. 6, a signal source impedance 19 and a resistance element 21 (diode 11 and diode 12 for the second signal S2). The voltage dividing ratio N (t) for the resistance element 21 in the voltage dividing circuit by the parallel connection) greatly fluctuates, and the waveform has a duty factor of 50% as shown in FIG. It is considered to be significantly different from the ideal rectangular wave pulse waveform. As a result, the divided voltage component Sd of the second signal S2 obtained between both ends of the resistance element 21, that is, the frequency conversion gain related to the multiplication output signal derived to the output terminal 22 through the choke coil 20 is reduced. Inconvenience arises.
[0031]
In view of such a point, the invention described in any one of claims 1 to 4 in the claims of the present application is provided with the first signal and the second signal, and the first signal In order to obtain a multiplication output signal of a signal having a frequency twice that of the second signal and the second signal, it is suitable for the entire integrated circuit and is hardly affected by temperature changes. A harmonic mixer circuit is provided.
[0032]
[Means for Solving the Problems]
  In the harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application, an emitter is commonly connected to form a first differential pair. Two transistors, third and fourth transistors whose emitters are commonly connected to form a second differential pair, fifth and sixth transistors whose emitters are commonly connected to form a third differential pair, And a seventh transistor and an eighth transistor having the emitter connected in common to form a fourth differential pair, and a first base formed by connecting the bases of the first and fifth transistors in common. A predetermined offset voltage is subtracted from the voltage of the first signal between the common connection point and the second common connection point formed by commonly connecting the bases of the second and sixth transistors. Voltage supplied In addition, the third common connection point formed by commonly connecting the bases of the third and seventh transistors and the fourth base formed by commonly connecting the bases of the fourth and eighth transistors. To the common connection point of the first and second transistors, and a voltage obtained by adding a predetermined offset voltage to the voltage of the first signal is supplied. A commonly connected emitter of fourth transistors is obtained, each modulated by a second signal.A pair of differential currentsA first current and a second current that generate a first current that is increased as the voltage of the second signal is increased and a second current that is decreased as the voltage of the second signal is increased, respectively. The second and the second current terminals are respectively connected to one and the other, and the commonly connected emitter of the fifth and sixth transistors and the commonly connected emitter of the seventh and eighth transistors are respectively connected to the second signal. Obtained by being modulated byA pair of differential currentsA third current and a third current that generate a third current that decreases as the voltage of the second signal increases and a fourth current that increases as the voltage of the second signal increases, respectively. When the emitters of the first and second transistors connected in common are connected to one and the other of the four current terminals, respectively, the fifth and sixth transistors are connected in common. And the emitter connected in common to the third current terminal and the commonly connected emitter of the first and second transistors connected to the second current terminal, the commonly connected emitters of the fifth and sixth transistors. Is connected to the fourth current terminal. Under such circumstances, a fifth common connection point formed by commonly connecting the collectors of the first, fourth, sixth and seventh transistors, and the second, third, fifth, And a sixth common connection point formed by commonly connecting the collectors of the eighth transistor and the eighth transistor is a multiplication output signal of a signal having a frequency twice the frequency of the first signal and the second signal. Are output terminals.
[0033]
  In the harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application configured as described above, the first differential pair is formed. Commonly connected emitters of the first and second transistors and commonly connected emitters of the third and fourth transistors forming a second differential pairIn,EachModulated by the second signalOne and the other of the first current and the second currentEach flowAndCommonly connected emitters of fifth and sixth transistors forming a third differential pair, and commonly connected emitters of seventh and eighth transistors forming a fourth differential pairIn,EachModulated by the second signalOne and the other of the third current and the fourth currentEach flowIn this case, when the first current flows through the commonly connected emitters of the first and second transistors, the third current flows through the commonly connected emitters of the fifth and sixth transistors. When the second current flows through the commonly connected emitter of the second transistor, the fourth current flows through the commonly connected emitter of the fifth and sixth transistors.. And first and first5The base of each transistorA first common connection point formed by common connectionFirst2And the base of each of the sixth transistorsWith a second common connection point formed by common connectionIn the meantime, a voltage obtained by subtracting a predetermined offset voltage from the voltage of the first signal is supplied, and the third and second voltages are supplied.7The base of each transistorA third common connection point formed by commonly connectingFirst4And the base of each of the eighth transistorsWith a fourth common connection point formed by common connectionIn the meantime, a voltage obtained by subtracting a predetermined offset voltage from the voltage of the first signal is supplied.
[0034]
Accordingly, the first transistor of the first and second transistors forming the first differential pair, and the fourth transistor of the third and fourth transistors forming the second differential pair. , A sixth transistor of the fifth and sixth transistors forming the third differential pair, and a seventh transistor of the seventh and eighth transistors forming the fourth differential pair Of the respective collector currents, the second transistor of the first and second transistors forming the first differential pair, and the third and fourth transistors of the second differential pair. Of the third transistor, the fifth transistor of the fifth and sixth transistors forming the third differential pair, and the seventh and eighth transistors forming the fourth differential pair. Each of our 8th transistors Current of the difference between the sum of the collector current is assumed to represent the multiplication result between the signal and the second signal having a frequency twice the frequency of the first signal. The difference current between the sum of the collector currents of the first, fourth, sixth and seventh transistors and the sum of the collector currents of the second, third, fifth and eighth transistors is , To a pair of output terminals.
[0035]
Therefore, in the harmonic mixer circuit according to any one of claims 1 to 4 in the claims of the present application, the first signal is supplied with a predetermined offset voltage. At the same time, the second signal is supplied, and a multiplication output signal of the signal having the frequency twice the frequency of the first signal and the second signal is obtained at the pair of output terminals. The first signal is a commonly connected emitter of the first and second transistors forming the first differential pair, and a common connection of the third and fourth transistors forming the second differential pair. Emitters, commonly connected emitters of fifth and sixth transistors forming a third differential pair, and commonly connected seventh and eighth transistors forming a fourth differential pair. There will be no situation in which the currents flowing through the emitters are modulated, and there is no problem that interference due to self-detection occurs in the first to fourth working pairs.
[0036]
The harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application does not need to include either an open stub or a short-circuit stub. It is suitable for the integration circuit. In addition, the predetermined offset voltage is set regardless of the forward voltage of the diode, so that there is no problem that the frequency conversion gain decreases due to the temperature change of the forward voltage of the diode.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example of a harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application.
[0038]
In the example shown in FIG. 1, the emitters are commonly connected to form a first differential pair, the first transistor 31 and the second transistor 32, and the emitters are commonly connected to form a second differential pair. The third transistor 33 and the fourth transistor 34, and the emitters are commonly connected to form a third differential pair, and the fifth transistor 35 and the sixth transistor 36, and the emitters are commonly connected to the fourth transistor. A seventh transistor 37 and an eighth transistor 38 forming the differential pair are provided. These first to eighth transistors 31 to 38 are all NPN type, and their emitter region areas are substantially equal.
[0039]
  First and second transistors 31 and 32 forming a first differential pairWhenFifth and sixth transistors 35 and 36 forming a third differential pair, The base of the first transistor 31 and the base of the fifth transistor 35 are connected in common to form a first common connection point, and the base of the second transistor 32 and the base of the sixth transistor 36 The base is commonly connected to form a second common connection point. The third and fourth transistors 33 and 34 forming the second differential pair and the seventh and eighth transistors 37 and 38 forming the fourth differential pair are the same as those of the third transistor 33. The base and the base of the seventh transistor 37 are connected in common to form a third common connection point, and the base of the fourth transistor 34 and the base of the eighth transistor 38 are connected in common. Common connection points are formed. And the first common connection point and the second common connection pointwhileIn addition,A signal source 40 that emits the first signal S1 and a DC power supply 41 that supplies an offset voltage Vk are connected in series. Also,Between the third common connection point and the fourth common connection point.whileIn addition,A signal source 40 and a DC power source 42 that supplies an offset voltage Vk are connected in series.
[0040]
  The first signal S1 is, for example, a sine wave signal having a frequency ω1, and the voltage V1 (t) is expressed by the above-described formula 1. And firstBetween the common connection point and the second common connection pointThe signal source 40 and the DC power supply 41 arranged in the series are connected in series with a polarity that the offset voltage Vk supplied by the DC power supply 41 is subtracted from the voltage V1 (t) of the first signal S1 generated by the signal source 40. It is connected. Thus, the voltage V1 (t) of the first signal S1 is generated between the bases of the first and second transistors 31 and 32 and between the bases of the fifth and sixth transistors 35 and 36, respectively. Thus, a voltage obtained by subtracting the offset voltage Vk is supplied.
[0041]
  On the other hand, the thirdBetween the common connection point and the fourth common connection pointThe signal source 40 and the DC power source 42 arranged in a series are connected in series with a polarity such that the offset voltage Vk supplied by the DC power source 42 is added to the voltage V1 (t) of the first signal S1 generated by the signal source 40. It is connected. Thus, the voltage V1 (t) of the first signal S1 is generated between the bases of the third and fourth transistors 33 and 34 and between the bases of the seventh and eighth transistors 37 and 38, respectively. A voltage obtained by adding the offset voltage Vk to is supplied.
[0042]
Further, in the example shown in FIG. 1, a current source unit 45 and a current source unit 46 to which a signal source 44 that emits the second signal S2 is connected are provided. The second signal S2 is, for example, a sine wave signal having a frequency ω2 corresponding to twice the frequency ω1 of the first signal S1, and the voltage V2 (t) is represented by the above-described formula 2. It is said.
[0043]
  The current source unit 45 includes current terminals 45A and 45B, and a current I1 and a current I2, which are a pair of differential currents modulated by the second signal S2 generated by the signal source 44, are supplied to the current terminals 45A and 45B. Respectively. Current I1And current I2 is current I1The larger the voltage V2 (t) of the second signal S2, the greater the value.WhenCurrent I2ButThe smaller the voltage V2 (t) of the second signal S2, the smaller it is.Or the current I1 is the voltage V2 of the second signal S2. (t) Current I2 is reduced to the voltage V2 of the second signal S2. (t) The larger the is, the greater the relationship.
[0044]
The current terminals 45A and 45B in the current source section 45 have emitters connected in common to the first and second transistors 31 and 32 forming the first differential pair, and a second differential. The commonly connected emitters of each of the third and fourth transistors 33 and 34 forming a pair are connected to each other. As a result, the current I1 flows in a divided manner to the emitter of the first transistor 31 and the emitter of the second transistor 32 that are commonly connected, and the emitter and the fourth transistor of the third transistor 33 that are commonly connected. The current I2 is diverted to the 34 emitter.
[0045]
  The current source unit 46 includes current terminals 46A and 46B, and a current I3 and a current I4, which are a pair of differential currents modulated by the second signal S2 generated by the signal source 44, are supplied to the current terminals 46A and 46B. Respectively. Current I3And current I4 is the current I3The smaller the voltage V2 (t) of the second signal S2, the smaller it is.WhenCurrent I4ButThe larger the voltage V2 (t) of the second signal S2, the greater the value.Or the current I3 is the voltage V2 of the second signal S2. (t) Is larger, the current I4 becomes the voltage V2 of the second signal S2. (t) It is assumed that the larger the is, the smaller the relationship is.
[0046]
The current terminals 46A and 46B in the current source section 46 have emitters connected in common to the fifth and sixth transistors 35 and 36 forming the third differential pair, and a fourth differential. The commonly connected emitters of each of the seventh and eighth transistors 37 and 38 forming a pair are connected to each other. As a result, the current I3 is shunted and flows to the emitter of the fifth transistor 35 and the emitter of the sixth transistor 36 that are connected in common, and the emitter and the eighth transistor of the seventh transistor 37 that are connected in common. The current I4 is diverted to the 38 emitters.
[0047]
  Further, in the example shown in FIG. 1, the collector of the first transistor 31 and the second differential pair of the first and second transistors 31 and 32 forming the first differential pair are connected. The collector of the fourth transistor 34 of the third and fourth transistors 33 and 34 to be formed, the sixth transistor 36 of the fifth and sixth transistors 35 and 36 forming the third differential pair. And the collector of the seventh transistor 37 of the seventh and eighth transistors 37 and 38 forming the fourth differential pair are connected in common.A fifth common connection point is formed,That5thAn output terminal 47A is derived from the common connection point. Of the first and second transistors 31 and 32 forming the first differential pair, the collector of the second transistor 32, the third and fourth transistors 33 forming the second differential pair, and 34, the collector of the third transistor 33, the collector of the fifth transistor 35 of the fifth and sixth transistors 35 and 36 forming the fourth differential pair, and the fourth differential pair. The collector of the eighth transistor 38 of the seventh and eighth transistors 37 and 38 formingA sixth common connection point is formed,That6thAn output terminal 47B is derived from the common connection point. These output terminals 47A and 47B form a pair.
[0048]
Under such circumstances, the current source unit 45 and the current source unit 46 have substantially the same characteristics, and when the voltage of the second signal S2 from the signal source 44 is 0, the current I1 , I2, I3, and I4 generate a DC current I0, and have a mutual conductance gm in forming the currents I1, I2, I3, and I4.
[0049]
The values I1 (t) and I2 (t) of the currents I1 and I2 obtained at the current terminals 45A and 45B in the current source unit 45, and the currents I3 and I3 obtained at the current terminals 46A and 46B in the current source unit 46, respectively. The respective values I3 (t) and I4 (t) of I4 are expressed by the following equation (9).
[0050]
[Equation 9]
I1 (t) = I0 / 2 + gm · V2 (t)
I2 (t) = I0 / 2−gm · V2 (t)
I3 (t) = I0 / 2−gm · V2 (t)
I4 (t) = I0 / 2 + gm · V2 (t)
[0051]
For each of the first to eighth transistors 31 to 38, the collector current is Ic and the base-emitter voltage is V._BE,Reverse collector saturation current is Is and thermal voltage is V_T(V_T= K · T / q, where k is a Boltzmann coefficient, T is an absolute temperature, and q is a unit charge of electrons), the relationship expressed by the following equation 10 holds.
[0052]
[Expression 10]
Ic = Is · exp (V_BE/ V_T)
[0053]
Thus, collector currents Ic1 (t), Ic2 (t), Ic3 (t), Ic4 (t), Ic5 (t), Ic6 (t) for the first to eighth transistors 31 to 38, respectively. , Ic7 (t) and Ic8 (t) are expressed by the following equation (11).
[0054]
## EQU11 ##
Ic1 (t) = I1 (t) / [1 + exp {− (V1 (t) −Vk) / V_T}]
Ic2 (t) = I1 (t) / [1 + exp {(V1 (t) −Vk) / V_T}]
Ic3 (t) = I2 (t) / [1 + exp {(V1 (t) + Vk) / V_T}]
Ic4 (t) = I2 (t) / [1 + exp {− (V1 (t) + Vk) / V_T}]
Ic5 (t) = I3 (t) / [1 + exp {− (V1 (t) −Vk) / V_T}]
Ic6 (t) = I3 (t) / [1 + exp {(V1 (t) −Vk) / V_T}]
Ic7 (t) = I4 (t) / [1 + exp {(V1 (t) + Vk) / V_T}]
Ic8 (t) = I4 (t) / [1 + exp {-(V1 (t) + Vk) / V_T}]
[0055]
The sum of collector currents Ic1 (t), Ic4 (t), Ic6 (t) and Ic7 (t) flows through the output terminal 47A, and collector currents Ic2 (t), Ic3 (t), Ic7 (t), through the output terminal 47B. The sum of Ic5 (t) and Ic8 (t) flows. Therefore, the differential output current Icd (t) obtained at the pair of output terminals 47A and 47B is expressed by the following equation (12).
[0056]
[Expression 12]
Icd (t) = (Ic1 (t) + Ic4 (t) + Ic6 (t) + Ic7 (t))
-(Ic2 (t) + Ic3 (t) + Ic5 (t) + Ic8 (t))
= 2 ・ gm ・ V2 (t)
・ [Tanh {(V1 (t) −Vk) / 2 ・ V_T}
-Tanh {(V1 (t) + Vk) / 2 · V_T}]
[0057]
Here, the term tanh in the above equation 12 is a function F {V1 (t), Vk} of the voltage V1 (t) of the first signal S1 and the offset voltage Vk as shown in the following equation 13. .
[0058]
[Formula 13]
F {V1 (t), Vk} = tanh {(V1 (t) −Vk) / 2 · V_T}
-Tanh {(V1 (t) + Vk) / 2 · V_T}
[0059]
For example, as shown in FIG. 2, the function F {V1 (t), Vk} has an offset voltage Vk of V_TIn the case of four times or more, the voltage V1 (t) of the first signal S1 transitions twice between 0 and -2 with a change from negative to positive. Since the first signal S1 is a sinusoidal signal having the frequency ω1, the function F {V1 (t), Vk} has a frequency twice as high as the frequency ω1, as indicated by a solid line in FIG. Change.
[0060]
For example, the amplitude v1 of the first signal S1 is selected to be √2 times the offset voltage Vk (v1 = √2 · Vk), and the offset voltage Vk is V_TThe function F {V1 (t), Vk} expressed by Equation 13 repeatedly takes a value between 0 and -2. Since the second signal S2 is a sine wave signal having the frequency ω2, the differential output current Icd (t) expressed by the equation 12 is expressed by a Fourier series expressed by the following equation 14.
[0061]
[Expression 14]

[0062]
In the above equation 14, when n = 1, the differential output current Icd (t) is a multiplication output signal of a signal having a frequency twice the frequency of the first signal S1 and the second signal S2. When the second signal S2 is a band signal, the baseband signal is obtained as a multiplication output signal.
[0063]
[Expression 15]
Icd (t) = 8 / π · gm · v2 · cos (2 · ω1 · t) · cos (ω2 · t)
= 4 / π · gm · v2
・ [Cos {(2 ・ ω1 + ω2) ・ t}
+ Cos {(2, ω1-ω2) · t}]
-2 ・ gm ・ v2 ・ cos (ω2 ・ t)
[0064]
In the example shown in FIG. 1 as described above, neither an open stub nor a short-circuit stub is used, and a plurality of transistors 31 to 38 forming a differential pair, DC voltage sources 41 and 42, current source portions 45 and 46, etc. Therefore, it is suitable for making the whole integrated circuit. Further, since the offset voltage Vk is set independently of the forward voltage of the diode and does not depend on the forward voltage of the diode, there is no problem that the frequency conversion gain is lowered due to a temperature change of the forward voltage of the diode. .
[0065]
【Example】
FIG. 4 shows a specific configuration example of an example of the harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application. The specific configuration example shown in FIG. 4 corresponds to a configuration in which the DC voltage sources 41 and 42 in the example shown in FIG. 1 are configured by a circuit including transistors that form two differential pairs. The parts other than the parts corresponding to the DC voltage sources 41 and 42 are the same as the example shown in FIG. 1, and the same reference numerals as those in FIG.
[0066]
In the specific configuration example shown in FIG. 4, NPN-type transistors 51 and 52 whose emitters are connected in common to form a differential pair, and currents connected to the emitters of the commonly connected transistors 51 and 52, respectively. An NPN type in which a source 53 and a voltage generator 57 formed including resistance elements 54, 55 and 56 connected to respective collectors of the transistors 51 and 52 and an emitter are connected in common to form a differential pair Transistors 61 and 62, a current source 63 connected to the emitters of the commonly connected transistors 61 and 62, and resistance elements 64, 65, 66 and 67 connected to the collectors of the transistors 61 and 62, respectively. In addition, a voltage generator 58 is provided. A signal source 40 that generates the first signal S1 is commonly connected between the bases of the transistors 51 and 52 and between the bases of the transistors 61 and 62.
[0067]
Each of the transistors 51, 52, 61, and 62 has substantially the same characteristics, and each of the current sources 53 and 63 generates a substantially constant current Io. Each of resistance elements 54, 55, 64 and 65 has substantially the same resistance value Rc, and each of resistance elements 56 and 66 also has substantially the same resistance value Ro. Yes. Furthermore, the resistance element 67 has a resistance value Rk. Note that Vcc shown in FIG. 4 is a power supply voltage.
[0068]
Under such circumstances, between the bases of the first and second transistors 31 and 32 forming the first differential pair, and the fifth and sixth transistors forming the third differential pair. A voltage obtained between the collector of the transistor 52 and the collector of the transistor 61 is supplied between the bases of the transistors 35 and 36 in common. Further, between the bases of the third and fourth transistors 33 and 34 forming the second differential pair, and the seventh and eighth transistors 37 and 38 forming the fourth differential pair, respectively. In common, the voltage obtained between the collector of the transistor 51 and the collector of the transistor 62 is supplied between the bases of the transistors.
[0069]
The voltage obtained between the collector of the transistor 52 and the collector of the transistor 61 is obtained by subtracting the offset voltage Vk ′ from the voltage V1 ′ (t) based on the voltage V1 (t) of the first signal S1 emitted from the signal source 40. The voltage obtained between the collector of the transistor 51 and the collector of the transistor 62 is a voltage V1 ′ (t based on the voltage V1 (t) of the first signal S1 emitted from the signal source 40. ) Is added to the offset voltage Vk ′. Here, the voltage V1 '(t) is a voltage proportional to the voltage V1 (t) and is expressed by the following equation (16), and the offset voltage Vk' is expressed by the following equation (17).
[0070]
[Expression 16]
V1 ′ (t) = V1 (t) (Rc · Io) / (2 · V_T)
[0071]
[Expression 17]
Vk ′ = Rk · Io
[0072]
As described above, in the specific configuration example shown in FIG. 4, between the bases of the first and second transistors 31 and 32 forming the first differential pair and the third differential pair. Between the bases of the fifth and sixth transistors 35 and 36 forming a common voltage, an offset voltage Vk ′ represented by the equation (17) to a voltage V1 ′ (t) represented by the equation (16) is common to them. A voltage obtained by being reduced is supplied, and the bases of the third and fourth transistors 33 and 34 forming the second differential pair and the seventh differential pair are formed. And the base of each of the eighth transistors 37 and 38 is obtained by adding the offset voltage Vk ′ represented by the equation 17 to the voltage V1 ′ (t) represented by the equation 16 in common with each other. Voltage It is supplied.
[0073]
Therefore, even in the specific configuration example shown in FIG. 4, the third differential pair is formed between the bases of the first and second transistors 31 and 32 forming the first differential pair. Between the bases of the fifth and sixth transistors 35 and 36, the predetermined offset voltage is substantially subtracted from the voltage V1 (t) of the first signal S1 generated by the signal source 40. Seventh and eighth transistors between the bases of the third and fourth transistors 33 and 34, which are supplied with voltage and which form a second differential pair, and between the bases of the third and fourth transistors 33 and 34, respectively. A voltage obtained by adding a predetermined offset voltage to the voltage V1 (t) of the first signal S1 generated by the signal source 40 is supplied between the bases of 37 and 38. . Therefore, the first to eighth transistors 31 to 38 forming the first to fourth differential pairs and the current source units 45 and 46 included in the specific configuration example shown in FIG. 4 are included. The configured part also performs the same operation as in the example shown in FIG.
[0074]
Note that when the specific configuration example shown in FIG. 4 is actually used, the amplitude of the voltage V1 ′ (t) is set to the offset voltage Vk because it has been described in the description of the example shown in FIG. Is selected to be √2 times the offset voltage Vk ', for example, V_TIt is desirable to be 4 times or more.
[0075]
【The invention's effect】
As is clear from the above description, in the harmonic mixer circuit according to any one of claims 1 to 4 in the claims of the present application, the first signal is a predetermined offset. The second signal is supplied together with the voltage, and a multiplication output signal of the signal having the frequency twice the frequency of the first signal and the second signal is obtained at the pair of output terminals. Where the first signal is the commonly connected emitter of the first and second transistors forming the first differential pair, the third and second forming the second differential pair. 4 transistors commonly connected emitters, fifth and sixth transistors commonly forming emitters forming a third differential pair, and seventh and eighth transistors forming fourth differential pairs. Flow through the commonly connected emitters of the transistors. That situation to modulate the current will be no, no problem that interference due to self detection occurs in the first to fourth working pair.
[0076]
The harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application does not need to include either an open stub or a short-circuit stub. In addition to being suitable for integration, the predetermined offset voltage is set independently of the forward voltage of the diode and does not depend on the forward voltage of the diode. Therefore, the frequency conversion gain is changed by the temperature change of the forward voltage of the diode. It is possible to avoid the problem of lowering.
[Brief description of the drawings]
FIG. 1 is a circuit connection diagram showing an example of a harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application.
FIG. 2 is a characteristic diagram for explaining the operation of the example shown in FIG. 1;
FIG. 3 is a characteristic diagram for explaining the operation of the example shown in FIG. 1;
FIG. 4 is a circuit connection diagram showing a specific configuration example of an example of a harmonic mixer circuit according to the invention described in any one of claims 1 to 4 in the claims of the present application.
FIG. 5 is a circuit connection diagram showing a conventionally proposed harmonic mixer circuit.
6 is an equivalent circuit connection diagram for explaining the harmonic mixer circuit shown in FIG. 5; FIG.
7 is a characteristic diagram for explaining the operation of the harmonic mixer circuit shown in FIG. 5; FIG.
FIG. 8 is a characteristic diagram for explaining the operation of the harmonic mixer circuit shown in FIG. 5;
[Explanation of symbols]
31, 32, 33, 34, 35, 36, 37, 38, 51, 52, 61, 62 Transistor 40, 44 Signal source 41, 42 DC power supply 45, 46 Current source unit 47A, 47B Output terminal 53, 63 Current source 54, 55, 56, 64, 65, 66, 67 Resistance element 57, 58 Voltage generator

Claims (4)

First and second transistors with a common emitter connected to form a first differential pair, third and fourth transistors with a common emitter connected to form a second differential pair, emitter connected in common And the fifth and sixth transistors forming the third differential pair, and the seventh and eighth transistors having the emitters connected in common to form the fourth differential pair,
The first common connection point formed by commonly connecting the bases of the first and fifth transistors and the second base formed by commonly connecting the bases of the second and sixth transistors. A voltage obtained by subtracting a predetermined offset voltage from the voltage of the first signal is supplied between the common connection point,
A third common connection point formed by connecting the bases of the third and seventh transistors in common and a fourth connection formed by connecting the bases of the fourth and eighth transistors in common. A voltage obtained by adding a predetermined offset voltage to the voltage of the first signal is supplied between the common connection point,
In the commonly connected emitters and said third and commonly connected emitters of the fourth transistor, each pair of that obtained through the modulation by the second signal differential current of said first and second transistors A first current that increases as the voltage of the second signal increases and a second current that decreases as the voltage of the second signal increases are generated. Connected to one and the other of the first and second current terminals respectively;
The fifth and the commonly connected emitters of the commonly connected emitters and transistors of the seventh and eighth of the sixth transistor is, each of the pair that is obtained is modulated by the second signal differential current A third current that is decreased as the voltage of the second signal is increased, and a fourth current that is increased as the voltage of the second signal is increased. Connected to one and the other of the third and fourth current terminals respectively;
When the commonly connected emitters of the first and second transistors are connected to the first current terminal, the commonly connected emitters of the fifth and sixth transistors are connected to the third current terminal. When the commonly connected emitters of the first and second transistors are connected to the second current terminal, the commonly connected emitters of the fifth and sixth transistors are the fourth current terminal. Connected to the
A fifth common connection point formed by commonly connecting the collectors of the first, fourth, sixth and seventh transistors; and the second, third, fifth and eighth transistors. An output from which a sixth common connection point formed by commonly connecting the respective collectors can obtain a multiplication output signal of a signal having a frequency twice the frequency of the first signal and the second signal. A harmonic mixer circuit characterized by being a terminal. The commonly connected emitters of the commonly connected emitters and said third and fourth transistors of said first and second transistors is connected to the current source unit having said first and second terminals Rutotomoni, the fifth and the commonly connected emitters of the commonly connected emitters and transistors of the seventh and eighth of the sixth transistor is a current source unit having said third and fourth current terminal The harmonic mixer circuit according to claim 1, further comprising: Harmonic mixer circuit according to claim 1 or 2, wherein that the carrier frequency of the upper Symbol first signal at twice the frequency and the second signal frequency is equal. Eight transistors from the first transistor to the transistor of the eighth harmonic mixer circuit according to claim 1 or 2, wherein the respective emitter region area is an equal correct ones.

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