JP4023231B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a dummy pattern.
[0002]
[Prior art]
When forming a wiring pattern of a semiconductor device, the formation of a dummy pattern is important in order to suppress variations in the proximity effect on exposure, reduce pattern dependency in the pattern etching process, and planarize in the CMP process. It is coming. An example of this dummy pattern is shown in JP-A-11-95406. In this example, as shown in FIG. 8, the dummy pattern has a dot pattern arranged at the end of the normal pattern. 1 is a normal pattern and 2 is a dummy pattern.
[0003]
[Problems to be solved by the invention]
Thus, since the conventional semiconductor device having a dummy pattern is a dot pattern, there is a problem that if the dot pattern is too small, the pattern may fly off and peel off.
[0004]
Also, during pattern etching, the area ratio of the pattern in the entire chip, the peripheral length of the pattern, etc. may have an effect, and it is often preferable to secure this area or peripheral length above a certain level. However, the conventional dot pattern has a problem that the efficiency is low.
[0005]
Conventionally, a dummy pattern is formed for the wiring system, but since a dummy pattern is not formed for the contact hole, there is a problem in processing accuracy when forming the contact hole. is there.
[0006]
In addition, in the conventional dummy pattern, the separation between the normal pattern and the dummy pattern is the same as the separation between the normal patterns, which may cause a decrease in yield such as a short circuit, as well as the wiring system. There is a problem in that the capacity between the contact hole patterns increases and the operation speed decreases.
[0007]
The present invention solves the above-mentioned problems, prevents pattern peeling, secures pattern area ratio and peripheral length, stabilizes pattern processing, stably processes contact holes, and further normal patterns An object of the present invention is to suppress a decrease in yield such as a short circuit between a dummy pattern and a dummy pattern, and to reduce the inter-pattern capacitance of a normal pattern, thereby enabling high speed.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the first semiconductor device of the present invention is formed in a structure in which a hole shape exists in the wiring system dummy pattern by configuring the wiring part of the dummy pattern in a mesh type. Yes.
[0009]
With such a configuration, the pattern is difficult to fly and peel off. Further, when the protruding portion exists in the dummy pattern, it is possible to further reduce defects due to a short circuit between the dummy pattern and the normal pattern.
[0010]
The second semiconductor device of the present invention includes a first dummy pattern formed of the first wiring layer, a second dummy pattern formed of the second wiring layer, a first dummy pattern, and a second dummy pattern. A contact hole dummy pattern for connecting the two.
[0011]
By adopting such a configuration, it is difficult for the pattern to fly and peel off, and the processing accuracy at the time of forming the contact hole can be improved and stable processing can be performed.
[0012]
In the second semiconductor device of the present invention, it is preferable that the first dummy pattern and the second dummy pattern are electrically connected to a floating state or a ground power source.
[0013]
By adopting such a configuration, it becomes difficult for the pattern to fly and peel off, and the processing accuracy at the time of forming the contact hole can be improved and stable processing can be performed. Further, when the first dummy pattern and the second dummy pattern are electrically connected to the ground power supply, it can be avoided that noise is further generated in the dummy pattern and a normal signal line is affected by the noise.
[0014]
In the second semiconductor device of the present invention, the separation of the contact hole dummy pattern is preferably larger than the separation of the normal contact hole pattern.
[0015]
By adopting such a configuration, it is easy to process the contact hole, and manufacturing defects are less likely to occur.
[0016]
In the third semiconductor device of the present invention, in the wiring dummy pattern, the separation between the dummy pattern and the normal pattern is larger than the minimum separation between the normal patterns.
[0017]
By adopting such a configuration, it is possible to suppress a decrease in yield, such as a short circuit between the normal pattern and the dummy pattern, and it is possible to increase the speed by reducing the capacity of the normal pattern.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.
[0019]
FIG. 1 is a configuration diagram of a dummy pattern according to the first embodiment. Here, 1 is a normal pattern and 2 is a dummy pattern. In the conventional example, the dummy pattern has a configuration in which the dot pattern is arranged at the end of the normal pattern. However, in this embodiment, the dummy pattern has a wiring portion configured in a mesh shape and has a hole pattern. It is. There is no protruding portion of the dummy pattern at the boundary with the normal pattern, and the separation is equivalent to that of normal wiring.
[0020]
FIG. 2 is a diagram showing the relationship between the pattern width (wiring width) (line: L) and the interval (space: S) of the dummy pattern. As shown in FIGS. 2A to 2D, the relationship between the wiring width (line: L) and the interval (space: S) is higher in the hole pattern than in the dot pattern in any case. . For this reason, when it is necessary to increase the area ratio, the hole pattern as in the present embodiment is more efficient. As for the peripheral length, the hole pattern is larger when the wiring width is smaller than the interval.
[0021]
As a feature of the first embodiment, the hole pattern has an effect that the pattern jumps and is not easily peeled off.
[0022]
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG.
[0023]
FIG. 3 is a diagram showing a dummy pattern configuration according to the second embodiment. Here, 1 is a normal pattern and 2 is a dummy pattern. Similar to the first embodiment, the dummy pattern is a dummy pattern having a structure in which the wiring portion is formed in a mesh shape and a hole shape exists.
[0024]
The difference from the first embodiment is that it is a dummy pattern having a structure in which a protruding protrusion exists at the end of the pattern. By this protruding portion, separation from the normal pattern can be ensured without reducing the area ratio of the pattern and the peripheral length.
[0025]
As a feature of the second embodiment, as in the first embodiment, the hole pattern has an effect that the pattern jumps and is not easily peeled off. Furthermore, since the separation from the normal pattern can be substantially secured by using a dummy pattern having a projecting protrusion at the pattern end, it is possible to reduce defects due to a short circuit between the dummy pattern and the normal pattern. is there. Further, since the separation from the normal pattern can be substantially secured, the capacity of the normal wiring can be reduced, and there is an effect that the signal can be operated at high speed.
[0026]
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.
[0027]
FIG. 4 is a diagram showing a dummy pattern configuration according to the third embodiment. Here, 1a is a normal pattern of the first wiring layer, 2a is a dummy pattern of the first wiring layer, 3a is a normal pattern of the second wiring layer, 4a is a dummy pattern of the second wiring layer, 5 is a contact of the dummy pattern, Reference numeral 6 denotes a normal pattern contact.
[0028]
In the first and second embodiments, the dummy pattern is formed for the wiring system. In this embodiment, a dummy pattern including the contact hole is formed. The structure has a dummy pattern 2a in the first wiring layer, a dummy pattern 4a in the second wiring layer, and a contact hole dummy pattern 5 that connects the dummy patterns. In the present embodiment, the dummy pattern is in an electrically floating state.
[0029]
As a feature of the third embodiment, with respect to the wiring system pattern, there is an effect that the hole pattern does not easily peel off and peel off similarly to the first embodiment. Further, the contact hole dummy pattern for connecting the dummy pattern of the first wiring layer and the dummy pattern of the second wiring layer between the dummy patterns has an effect of improving the processing accuracy when forming the contact hole and enabling stable processing. There is. In addition, since the first dummy pattern and the second dummy pattern are connected by a contact, there is an effect that the pattern does not fly and peels off.
[0030]
(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram showing a dummy pattern configuration according to the fourth embodiment. 1a is a normal pattern of the first wiring layer, 2a is a dummy pattern of the first wiring layer, 3a is a normal pattern of the second wiring layer, 4a is a dummy pattern of the second wiring layer, 5 is a contact of the dummy pattern, 6 is normal The pattern contact 7 is a signal line connected to the ground power supply VSS to which the dummy pattern 4a of the second wiring layer is connected.
[0031]
Similar to the third embodiment, the dummy pattern 2a of the first wiring layer, the dummy pattern 4a of the second wiring layer, and the contact hole dummy pattern 5 for connecting the dummy patterns are provided.
[0032]
The difference from the third embodiment is that the dummy pattern is electrically connected to a voltage source. In this embodiment, it is connected to a ground voltage source.
[0033]
As a feature of the fourth embodiment, in addition to the effects of the third embodiment, since the dummy pattern is connected to the ground voltage signal line, noise is generated in the dummy pattern, and the normal signal line is There is an effect that it is possible to avoid being affected.
[0034]
(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a dummy pattern configuration according to the fifth embodiment. 1a is a normal pattern of the first wiring layer, 2a is a dummy pattern of the first wiring layer, 3a is a normal pattern of the second wiring layer, 4a is a dummy pattern of the second wiring layer, 5 is a contact of the dummy pattern, 6 is normal It is a contact of the pattern.
[0035]
Similar to the third embodiment, the dummy pattern 2a of the first wiring layer, the dummy pattern 4a of the second wiring layer, and the contact hole dummy pattern 5 for connecting the dummy patterns are provided.
[0036]
A difference from the third embodiment is that the separation of the contact hole dummy pattern is larger than the separation of the normal contact hole pattern. It is laid out with rules that have a margin for processing.
[0037]
As a feature of the fifth embodiment, in addition to the effects of the third embodiment, the separation of the contact hole dummy pattern is larger than the separation of the normal contact hole pattern. There is an effect that it is difficult to occur.
[0038]
(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a dummy pattern configuration diagram of the sixth embodiment. 1 is a normal pattern, 2 is a dummy pattern, 8 is a separation between normal patterns, and 9 is a separation between a normal pattern and a dummy pattern.
[0039]
The present embodiment is characterized in that the separation 9 between the normal pattern and the dummy pattern is larger than the separation 8 between the normal patterns. Here, the configuration of the dummy pattern is a mesh type structure similar to that of the first embodiment.
[0040]
As a feature of the sixth embodiment, by increasing the separation 9 between the normal pattern and the dummy pattern rather than the separation 8 between the normal patterns, it is possible to suppress a decrease in yield such as a short circuit between the normal pattern and the dummy pattern. There is an effect that the speed can be increased by reducing the capacity of the normal pattern.
[0041]
Although the first to sixth embodiments have been described above, the present invention also includes a structure in which these are used in combination.
[0042]
The dummy pattern of the present invention is used as necessary, and it is not necessary to make all the dummy patterns of the product into the main pattern, and a semiconductor product including the pattern in part is included in the present invention.
[0043]
【The invention's effect】
As described above, in the semiconductor device including the dummy pattern according to the present invention, the pattern area ratio and the peripheral length for stabilizing the pattern processing can be efficiently arranged without causing the pattern to fly and peeling, and the contact hole. In addition, there is an effect that stable processing can be performed by configuring the dummy pattern, a decrease in yield such as a short circuit between the normal pattern and the dummy pattern can be suppressed, and the speed can be increased by reducing the capacity of the normal pattern.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a dummy pattern according to a first embodiment of the present invention. FIG. 2 shows a relationship between a pattern width (line: L) and an interval (space: S) of a dummy pattern according to the first embodiment of the present invention. FIG. 3 is a diagram of a dummy pattern according to a second embodiment of the present invention. FIG. 4 is a diagram of a dummy pattern according to a third embodiment of the present invention. FIG. 6 is a diagram of a dummy pattern according to a fifth embodiment of the present invention. FIG. 7 is a diagram of a dummy pattern according to a sixth embodiment of the present invention. Explanation】
DESCRIPTION OF SYMBOLS 1 Normal pattern 1a Normal pattern 2 of 1st wiring layer Dummy pattern 2a Dummy pattern 3a of 1st wiring layer 2nd Normal pattern 4a 2nd wiring layer dummy pattern 5 Dummy pattern contact 6 Normal pattern contact 7 Signal line 8 connected to ground power supply VSS 8 Separation between normal patterns 9 Separation between normal pattern and dummy pattern

Claims (18)

In the dummy pattern of the wiring system, by forming the wiring portion of the dummy pattern in a mesh type, it is formed in a structure in which a hole shape exists ,
The semiconductor device , wherein the dummy pattern is in an electrically floating state .   2. The semiconductor device according to claim 1, wherein there is no protruding protrusion at a pattern end of the wiring portion configured in the mesh type.   2. The semiconductor device according to claim 1, wherein a projecting protrusion is present at a pattern end of the wiring portion configured in the mesh type. The separation between the dummy pattern and the normal pattern is larger than the minimum separation between the normal patterns. 1 The semiconductor device according to any one of? In the dummy pattern of the wiring system, by forming the wiring portion of the dummy pattern in a mesh type, it is formed in a structure in which a hole shape exists,
2. A semiconductor device according to claim 1, wherein a separation between the dummy pattern and the normal pattern is larger than a minimum separation between the normal patterns. 6. The semiconductor device according to claim 5, wherein there is no protruding protrusion at the pattern end of the wiring portion configured in the mesh type. 6. The semiconductor device according to claim 5, wherein a convex protruding portion exists at a pattern end portion of the wiring portion configured in the mesh type. A first dummy pattern formed in the first wiring layer; a second dummy pattern formed in the second wiring layer; and a contact hole dummy pattern connecting the first dummy pattern and the second dummy pattern ,
In the semiconductor device , the first dummy pattern has a wiring portion configured in a mesh type . The semiconductor device according to claim 8, wherein the second dummy pattern has a wiring portion configured in a mesh type. A first dummy pattern formed in the first wiring layer; a second dummy pattern formed in the second wiring layer; and a contact hole dummy pattern connecting the first dummy pattern and the second dummy pattern,
  The semiconductor device according to claim 2, wherein the second dummy pattern has a wiring portion configured in a mesh shape. The semiconductor device according to claim 8, wherein the first dummy pattern and the second dummy pattern are in an electrically floating state. The semiconductor device according to claim 8, wherein the first dummy pattern and the second dummy pattern are electrically connected to a power signal. 13. The semiconductor device according to claim 12, wherein the power signal is a ground power source. 14. The semiconductor device according to claim 8, wherein a separation of the contact hole dummy pattern is larger than a separation of a normal contact hole pattern. A first dummy pattern formed in the first wiring layer; a second dummy pattern formed in the second wiring layer; and a contact hole dummy pattern connecting the first dummy pattern and the second dummy pattern,
2. A semiconductor device according to claim 1, wherein a separation of the contact hole dummy pattern is larger than a separation of a normal contact hole pattern. 16. The semiconductor device according to claim 15, wherein the first dummy pattern and the second dummy pattern are in an electrically floating state. The semiconductor device according to claim 15, wherein the first dummy pattern and the second dummy pattern are electrically connected to a power signal. 18. The semiconductor device according to claim 17, wherein the power signal is a ground power source.

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