JP3942684B2 - Burn-in board - Google Patents
Burn-in board Download PDFInfo
- Publication number
- JP3942684B2 JP3942684B2 JP05861897A JP5861897A JP3942684B2 JP 3942684 B2 JP3942684 B2 JP 3942684B2 JP 05861897 A JP05861897 A JP 05861897A JP 5861897 A JP5861897 A JP 5861897A JP 3942684 B2 JP3942684 B2 JP 3942684B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- board
- burn
- floating
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 20
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
Landscapes
- Structure Of Printed Boards (AREA)
- Protection Of Static Devices (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、バーンインボードに関するもので、特にバーンインボードの寿命を伸ばすことを目的とする。
【０００２】
【従来の技術】
図５（ａ）は従来の新品バーンインボード断面を示す図であり、また、図５（ｂ）は従来のバーンインボードで長期間使用されると外周の絶縁体が摩耗して内部のＶＣＣ，ＧＮＤパターンが露出してくる状態を示した図であり、さらに、図５（ｃ）はトラブルの発生した従来のバーンインボード断面図である。
【０００３】
【発明が解決しようとする課題】
上記のような従来のバーンインボードでは、トラブルはＶＣＣパターンとＧＮＤパターンが露出して剥がれその金属屑がＶＣＣパターンとＧＮＤパターンに接触しショートするに至った。
【０００４】
【課題を解決するための手段】
本発明は従来技術の課題を有利に解決するものであって、請求項１記載のように、基板と、該基板の厚み方向に互いに離間した状態となるように該基板内に埋設されてなるＶＣＣパターン及びＧＮＤパターンと、前記ＶＣＣパターンと前記基板の面方向に互いに離間した状態となるように該基板内であって該基板の外周側に埋設されてなるフローティングＶＣＣパターンと、前記ＧＮＤパターンと前記基板の面方向に互いに離間した状態となるように該基板内であって該基板の外周側に埋設されてなるフローティングＧＮＤパターンと、を備えたことを特徴とするバーンインボードであり、また、請求項２記載のように、ボードの角はスリットを大きくとり配線領域に至らないようにすることを特徴とするバーンインボードである。
【０００５】
【発明の実施の形態】
次に、本発明について図面を参照して説明する。
【０００６】
図１（ａ）は、本発明の新品バーンインボードの断面を示す。ＬＡＹ２（ＶＣＣパターン）はスリットＡを、ＬＡＹ３（ＧＮＤパターン）はスリットＢをそれぞれ外周部に設け、さらに、その外周部にフローティングＶＣＣパターンとフローティングＧＮＤパターンの構造を設ける。更にボードの両面にはフローティングパターンＡとフローティングパターンＢを設ける。
【０００７】
図１（ｂ）は、本発明のバーンインボードで延べの使用回数が多くなるとボードの端の絶縁体が摩耗してフローティングＶＣＣパターン、フローティングＧＮＤパターンが露出してくる。しかし、フローティングパターンＡとフローティングパターンＢを設け強化してある為、絶縁体の摩耗の進行は従来のボードよりは抑制される。
【０００８】
図１（ｃ）は、本発明のバーンインボードで更に摩耗が進行するとフローティングＶＣＣパターン、フローティングＧＮＤパターンが剥がれ金属屑でショートに至る。
【０００９】
しかし、本発明によりＶＣＣパターンとＧＮＤパターンはスリットで電気的に分離されている為、不具合は生じない。更にフローティングパターンＡとフローティングパターンＢ及びフローティングＶＣＣパターン、フローティングＧＮＤパターンにより摩耗は抑制される。
【００１０】
本発明の実施の形態をさらに説明する。
【００１１】
図２は本発明でのバーンインボードの１例を示す。各層信号の組み合わせはこの限りでは無い。
ＬＡＹ１は信号系パターンの層である。
ＬＡＹ２はＶＣＣパターンの層である。ＬＡＹ３はＧＮＤパターンの層である。ＬＡＹ４は信号系パターンの層である。
【００１２】
図３で本発明によるＬＡＹ２（ＶＣＣパターン）とＬＡＹ３（ＧＮＤパターン）を詳細に説明する。バーンインボードは効率を高める為出来る限りの半導体デバイスを実装する。バーンインボードにて多数の半導体デバイスを実動作させるため、ＬＡＹ２（ＶＣＣパターン），ＬＡＹ３（ＧＮＤパターン）は電流容量、ノイズ低減の目的より１層全部を使用してベタパターンの構造をとっている。ＶＣＣ，ＧＮＤのベタパターンはバーンインボードの全領域に渡って最大に設ける。
【００１３】
しかし、本発明によりＶＣＣパターンとＧＮＤパターンはそれぞれスリットで電気的に分離されている為、不具合は生じない。更にフローティングパターンＡとフローティングパターンＢ及びフローティングＶＣＣパターン、フローティングＧＮＤパターンにより摩耗は抑制される。
【００１４】
図４は、本発明の多層バーンインボードの各層にフローティングパターンとスリットを設けた実施の形態である。通常、バーンインボードはアルミ枠を補強のため設ける。フローティングパターンはアルミ枠の外側に設ける。スリットはアルミ枠の内側又は外側に設ける。フローティングパターンは摩耗抑制の為出来る限りバーンインボードの外周に沿って設ける。スリットはボードの直線部分についてはフローティングパターンと平行に設け、ボードの角は摩耗しやすい為スリットの間隔を広く設ける。
【００１５】
本発明の特徴とする所は、バーンインボード基板の外周摩耗抑制の為、全層の外周にフローティングパターンを設けて強化を計りボードの寿命を伸ばすことを目的とする。
【００１６】
又、スリットを設けることにより摩耗による金属屑ショートのトラブル防止を図る。特にボードの角は摩耗しやすい為スリットを大きくとり配線領域に至らないようにする。
【００１７】
【発明の効果】
本発明により、バーンインボード外周を強化することによりバーンインボードの寿命が伸びる。又、ボードの外周のパターンフローティングを設けることにより摩耗による層間ショートのトラブルを防止出来る。
【図面の簡単な説明】
【図１】本発明の一実施の形態を示す断面図である。
【図２】本発明でのバーンインボードの１例を示す図である。
【図３】本発明によるＬＡＹ２（ＶＣＣ）とＬＡＹ３（ＧＮＤ）を詳細に説明した図である。
【図４】本発明の多層バーンインボードの各層にフローティングパターンとスリットの関係を示す詳細図である。
【図５】従来例を示す図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a burn-in board, and particularly aims to extend the life of the burn-in board.
[0002]
[Prior art]
FIG. 5 (a) is a diagram showing a cross section of a conventional new burn-in board. FIG. 5 (b) shows a case where the outer peripheral insulator is worn away when used for a long time with the conventional burn-in board, and the internal VCC, GND FIG. 5 is a view showing a state where a pattern is exposed, and FIG. 5C is a cross-sectional view of a conventional burn-in board in which a trouble has occurred.
[0003]
[Problems to be solved by the invention]
In the conventional burn-in board as described above, the VCC pattern and the GND pattern are exposed and peeled off, and the metal scrap comes into contact with the VCC pattern and the GND pattern to cause a short circuit.
[0004]
[Means for Solving the Problems]
The present invention advantageously solves the problems of the prior art, and as described in claim 1, the substrate and the substrate are embedded in the substrate so as to be separated from each other in the thickness direction of the substrate. A VCC pattern and a GND pattern; a floating VCC pattern embedded in an outer peripheral side of the substrate in the substrate so as to be separated from each other in the surface direction of the VCC pattern and the substrate; and the GND pattern A floating GND pattern embedded in the substrate and embedded on the outer peripheral side of the substrate so as to be separated from each other in the surface direction of the substrate, and a burn-in board, According to a second aspect of the present invention, the corner of the board is a burn-in board characterized in that a slit is made large so as not to reach the wiring area.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0006]
FIG. 1A shows a cross section of a new burn-in board according to the present invention. LAY2 (VCC pattern) is provided with a slit A, and LAY3 (GND pattern) is provided with a slit B on the outer peripheral portion, and further, a floating VCC pattern and a floating GND pattern structure are provided on the outer peripheral portion. Further, a floating pattern A and a floating pattern B are provided on both sides of the board.
[0007]
In FIG. 1B, when the total number of times of use is increased in the burn-in board of the present invention, the insulator at the edge of the board is worn and the floating VCC pattern and the floating GND pattern are exposed. However, since the floating pattern A and the floating pattern B are provided and strengthened, the progress of wear of the insulator is suppressed as compared with the conventional board.
[0008]
In FIG. 1C, when the wear further progresses in the burn-in board of the present invention, the floating VCC pattern and the floating GND pattern are peeled off and short-circuited with metal scraps.
[0009]
However, since the VCC pattern and the GND pattern are electrically separated by the slit according to the present invention, no problem occurs. Further, wear is suppressed by the floating pattern A, the floating pattern B, the floating VCC pattern, and the floating GND pattern.
[0010]
The embodiment of the present invention will be further described.
[0011]
FIG. 2 shows an example of a burn-in board in the present invention. The combination of each layer signal is not limited to this.
LAY1 is a signal system pattern layer.
LAY2 is a VCC pattern layer. LAY3 is a GND pattern layer. LAY4 is a signal system pattern layer.
[0012]
FIG. 3 illustrates LAY2 (VCC pattern) and LAY3 (GND pattern) according to the present invention in detail. The burn-in board mounts as many semiconductor devices as possible to increase efficiency. In order to actually operate a large number of semiconductor devices on the burn-in board, LAY2 (VCC pattern) and LAY3 (GND pattern) have a solid pattern structure using all one layer for the purpose of current capacity and noise reduction. The solid pattern of VCC and GND is provided at the maximum over the entire area of the burn-in board.
[0013]
However, since the VCC pattern and the GND pattern are electrically separated by the slits according to the present invention, there is no problem. Further, wear is suppressed by the floating pattern A, the floating pattern B, the floating VCC pattern, and the floating GND pattern.
[0014]
FIG. 4 shows an embodiment in which a floating pattern and a slit are provided in each layer of the multilayer burn-in board of the present invention. Usually, the burn-in board is provided with an aluminum frame for reinforcement. The floating pattern is provided outside the aluminum frame. The slit is provided inside or outside the aluminum frame. The floating pattern is provided along the outer periphery of the burn-in board as much as possible to suppress wear. The slits are provided in parallel with the floating pattern for the straight part of the board, and the corners of the board are subject to wear, so that the slits are widely spaced.
[0015]
The feature of the present invention is to provide a floating pattern on the outer periphery of all the layers to increase the life of the board by suppressing the wear on the outer periphery of the burn-in board substrate.
[0016]
In addition, by providing a slit, it is possible to prevent troubles caused by metal shorts due to wear. In particular, the corners of the board are subject to wear, so make a large slit so as not to reach the wiring area.
[0017]
【The invention's effect】
According to the present invention, the life of the burn-in board is extended by strengthening the outer periphery of the burn-in board. In addition, by providing a pattern floating on the outer periphery of the board, it is possible to prevent troubles caused by abrasion between layers.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of the present invention.
FIG. 2 is a diagram showing an example of a burn-in board according to the present invention.
FIG. 3 is a diagram illustrating LAY2 (VCC) and LAY3 (GND) in detail according to the present invention.
FIG. 4 is a detailed view showing a relationship between a floating pattern and a slit in each layer of the multilayer burn-in board of the present invention.
FIG. 5 is a diagram illustrating a conventional example.
Claims (2)
該基板の厚み方向に互いに離間した状態となるように該基板内に埋設されてなるＶＣＣパターン及びＧＮＤパターンと、 A VCC pattern and a GND pattern embedded in the substrate so as to be separated from each other in the thickness direction of the substrate;
前記ＶＣＣパターンと前記基板の面方向に互いに離間した状態となるように該基板内であって該基板の外周側に埋設されてなるフローティングＶＣＣパターンと、 A floating VCC pattern embedded in the outer peripheral side of the substrate in the substrate so as to be separated from each other in the plane direction of the VCC pattern and the substrate;
前記ＧＮＤパターンと前記基板の面方向に互いに離間した状態となるように該基板内であって該基板の外周側に埋設されてなるフローティングＧＮＤパターンと、 A floating GND pattern embedded in an outer peripheral side of the substrate in the substrate so as to be separated from each other in the plane direction of the GND pattern and the substrate;
を備えたことを特徴とするバーンインボード。Burn-in board characterized by having
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05861897A JP3942684B2 (en) | 1997-02-27 | 1997-02-27 | Burn-in board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05861897A JP3942684B2 (en) | 1997-02-27 | 1997-02-27 | Burn-in board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242608A JPH10242608A (en) | 1998-09-11 |
| JP3942684B2 true JP3942684B2 (en) | 2007-07-11 |
Family
ID=13089561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05861897A Expired - Fee Related JP3942684B2 (en) | 1997-02-27 | 1997-02-27 | Burn-in board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3942684B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7101021B2 (en) | 2001-07-30 | 2006-09-05 | Seiko Epson Corporation | Connection apparatus for circuit board, ink jet type recording apparatus using the same, IC chip and ink cartridge having IC chip |
| US6597061B1 (en) | 2001-08-03 | 2003-07-22 | Sandisk Corporation | Card manufacturing technique and resulting card |
| JP2010185802A (en) * | 2009-02-13 | 2010-08-26 | Nippon Avionics Co Ltd | Burn-in test board |
| JP5885332B2 (en) | 2011-10-20 | 2016-03-15 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
-
1997
- 1997-02-27 JP JP05861897A patent/JP3942684B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10242608A (en) | 1998-09-11 |
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