JP4023966B2 - Manufacturing method of semiconductor package - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package, and in particular, in manufacturing a package having a film circuit board such as a LGA (Land Grid Array) or a BGA (Ball Grid Array), the number of packages that can be manufactured simultaneously is dramatically improved. And an insulating film used in the method.
[0002]
[Prior art]
With the widespread use of cellular phones, portable computers and other small electronic devices, there is an increasing demand for miniaturization of semiconductor packages mounted on them. A semiconductor package having an LGA or BGA structure is suitable for miniaturization because an external connection terminal as an interface to an external substrate can be two-dimensionally arranged on the bottom surface of the package. On the other hand, these semiconductor packages have a problem that the manufacturing cost per unit package is generally higher than that of a conventional package such as QFP (Quad Flat Package).
[0003]
In manufacturing an LGA or BGA package, a flexible insulating film made of polyimide resin or the like is used. A plurality of identical circuit patterns are formed in the row and column directions of the insulating film, a semiconductor chip is mounted on each circuit pattern, and sealed with a mold to simultaneously manufacture a plurality of semiconductor packages.
[0004]
FIG. 6 shows an example of a flexible insulating film used to manufacture this type of package. The insulating film 60 has sprocket holes 60a on both sides in the longitudinal direction so that the film can be wound and conveyed. A plurality of circuit patterns 61 made of copper or other metal are formed inside the row of the holes 60a of the insulating film 60 (a specific circuit pattern is omitted in the figure and only the region is shown). On the surface of the insulating film 60, together with the circuit pattern 61, a conductor pattern 62 and a bridge 63 that connects the conductor pattern 62 and each circuit pattern 61 are formed. The conductor pattern 62 and the bridge 63 are power supply patterns for plating each circuit pattern 61. A pattern on the insulating film including the circuit pattern 61 is plated by connecting a cathode of a DC power source to the conductor pattern 62 and performing DC electrolysis in a solution containing plating metal ions. Plating each circuit pattern 61 is an essential technique for improving the corrosion resistance and solder wettability of the circuit pattern 61. The circuit pattern 61, the power supply conductor pattern 62 and the bridge 63 are formed on the insulating film 60 by first attaching a metal foil to the entire area of the film, and then using an lithography technique, that is, unnecessary portions, ie, in the circuit pattern and each This is accomplished by removing the area around the circuit pattern.
[0005]
FIG. 7 shows a manufacturing process of a conventional semiconductor package using the insulating film 60. In a conventional semiconductor package manufacturing process, a semiconductor chip 71 is mounted on each circuit pattern 61 of the insulating film 60 plated (FIG. 5A), and the electrode pads and circuit patterns of each chip 71 are mounted. Are connected by wire bonding 72 (FIG. 5B). Next, the insulating film 60 is housed in a mold, and each semiconductor chip 71 is molded 73 (FIG. 3C). Here, the mold has cavities corresponding to the respective semiconductor chips 71, and mold compounds 73 are injected into the respective cavities, whereby the semiconductor chips 71 are sealed, and the mold compounds 73 The outline of the semiconductor package is formed. In the next step shown in FIG. 4D, after a solder bump 74 as an external connection terminal is formed on the back side of the insulating film 60, a punching jig 75 is used as shown in FIG. Thus, each semiconductor package 76 is sequentially punched from the insulating film 60.
[0006]
[Problems to be solved by the invention]
However, in manufacturing a semiconductor package using the conventional insulating film, there are some problems as follows.
(1) In the manufacture of a conventional semiconductor package, resin is molded corresponding to each semiconductor package and cut out individually using a punching jig. It was difficult to make it smaller. As a result, the number of semiconductor packages that can be manufactured from a single insulating film is limited, and there are many regions on the insulating film that are not used as substrates for the semiconductor package. It has been a hindrance to improving sex.
(2) In the process of molding a semiconductor chip, a mold having a cavity corresponding to each semiconductor package is used, so that a long runner is required to guide the mold compound to each cavity. After injecting mold compound into each cavity, a large amount of mold compound remains in the long runner. Such wasteful consumption of the mold compound contributes to an increase in the manufacturing cost of the semiconductor package.
(3) When designing a plurality of types of insulating films having different circuit pattern planar sizes, it is necessary to individually change the shape of the surrounding conductive pattern for plating depending on the size of the circuit pattern. Inefficient.
[0007]
Accordingly, an object of the present invention is to dramatically increase the number of semiconductor packages that can be manufactured from a single insulating film to improve the productivity, and to reduce the area to be discarded on the insulating film and the amount of mold compound to be used. It is to minimize the manufacturing cost by minimizing it.
[0008]
Another object of the present invention is to provide an insulating film having a conductor pattern that facilitates the design of a plurality of types of insulating films.
[0009]
[Means for Solving the Problems]
The present invention relates to an insulating film for providing an insulating substrate for mounting a semiconductor chip in a semiconductor package. The insulating film of the present invention includes a plurality of circuit patterns formed in the row and column directions on the main surface of the insulating film, a main line arranged to surround the plurality of circuit patterns, and the circuit patterns. And a plating power feed conductor pattern of the circuit pattern including a sub-line extending and electrically connecting the circuit pattern and the main line.
[0010]
Preferably, the main line of the conductor pattern is formed for each pattern group including a predetermined number of circuit patterns in the length direction of the insulating film.
[0011]
Preferably, the main line of the conductor pattern is a pair of first lines extending on both sides in the length direction of the insulating film, and a first line extending between the pattern groups and both ends thereof are connected to the pair of first lines. 2 lines.
[0012]
Preferably, the sub-line of the conductor pattern includes a grid-like line arranged so as to surround each circuit pattern in the main line.
[0013]
Further, preferably, the sub-line of the conductor pattern includes a plurality of bridges connecting the lattice-like line and each circuit pattern.
[0014]
In the present invention, the line width of the sub-line of the conductor pattern is preferably at least narrower than the width of the dicing blade for cutting the insulating film, particularly 100 μm or less. On the other hand, the line width of the main line of the conductor pattern is preferably 0.6 mm or more.
[0015]
Preferably, the insulating film includes a via hole for mounting an external connection terminal for electrically connecting the circuit pattern and an external substrate under each circuit pattern.
[0016]
The present invention also relates to a method for manufacturing a semiconductor package. The manufacturing method of the present invention includes a step of preparing an insulating film having the above configuration, a step of plating each circuit pattern using a conductor pattern on the insulating film, and a predetermined region of each circuit pattern of the insulating film. In addition, the step of mounting the semiconductor chip and electrically connecting the circuit pattern and the semiconductor chip, and partitioning into regions surrounded by the main line of the conductor pattern, and injecting mold resin into the mold A step of sealing each semiconductor chip, a step of electrically connecting an external connection terminal for mounting a semiconductor package on an external substrate to each circuit pattern, and the insulating film at the position of the sub-line. And a step of dicing together with the mold resin and separating into individual semiconductor packages.
[0017]
In this case, the step of dicing the insulating film uses at least a dicing blade having a blade width wider than the line width of the sub-line of the conductor pattern so that the sub-line does not remain after the insulating film is cut. To.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a pattern configuration on an insulating film according to an embodiment of the present invention. In the figure, the insulating film 10 is provided with holes 10a for conveying sprockets along both sides thereof. The insulating film 10 is first supplied as a long film, and is cut into a desired dimension as shown in FIG. The insulating film 10 is preferably a polyimide resin film having a thickness of about 50 μm. Although omitted in the drawing, the insulating film 10 has a plurality of via holes for mounting external connection terminals in a circuit pattern region to be described later. The land area in the circuit pattern and the external connection terminal are electrically connected through the via hole.
[0019]
The insulating film 10 includes a plating conductor pattern 14 including a circuit pattern 11 and a relatively thick main line 12 and a relatively narrow sub-line 13 on one surface thereof. These patterns are obtained by once depositing a metal foil (preferably a copper foil) on the entire area of the insulating film 10 and then exposing the lithography technique (that is, after applying a resist, masking necessary or unnecessary parts, It is formed by removing unnecessary metal portions using (etching).
[0020]
A number of circuit patterns 11 are regularly arranged in the row and column directions of the insulating film 10. One circuit pattern 11 is formed in a region defined by a sub-line 13 of a conductor pattern to be described later. In the illustrated example, 270 circuit patterns 11 are formed on the insulating film 10. In the figure, the circuit pattern 11 is omitted by hatching, but actually, each circuit pattern 11 has a plurality of lands 11a corresponding to via holes formed on the insulating film as shown in FIG. A plurality of connection lands 11b for wire bonding from the semiconductor chip and a plurality of line segments 11c connecting the two lands are included.
[0021]
The plating conductor pattern 14 includes the main line 12 and the sub-line 13. The main line 12 of the conductor pattern is a frame-like wiring composed of relatively thick lines formed so as to partition the circuit pattern 11 on the insulating film 10 into a plurality of blocks (three blocks 15A to 15C in the example of FIG. 1). is there. That is, the main line 12 includes a horizontal line 12a formed along both sides of the insulating film 10 and vertical lines 12b formed at predetermined intervals in the longitudinal direction of the insulating film 10, that is, every predetermined number of circuit patterns. In one preferred embodiment, the horizontal line 12a has a line width of 0.6 to 1.0 mm, and the vertical line 12b has a line width of 0.3 to 2.0 mm. In the process of plating the circuit pattern 11, the cathode of the DC power supply is directly connected to the main line 12.
[0022]
The sub-line 13 of the conductor pattern is a grid-like wiring composed of relatively thin lines formed in the respective blocks 15A to 15C surrounded by the main line 12. That is, the sub-line 13 is composed of a vertical line 13a whose both ends are connected to the horizontal line 12a of the main line and a horizontal line 13b whose both ends are connected to the vertical line 12b of the main line. The circuit patterns 11 are arranged in the grid of the lattice formed by the vertical lines 13a and the horizontal lines 13b.
[0023]
The line width of the sub-line 13 is determined by the relationship with the blade width of the dicing blade used in the manufacturing process of the semiconductor package using the insulating film described later. At the time of separating each semiconductor package, the insulating film 10 is cut and separated at the position of the sub-line 13 using a dicing blade. In this manufacturing process, it is necessary to prevent the sub-line 13 from remaining on the insulating film 10 after cutting. The sub line 13 causes a short circuit between the wirings in each circuit pattern 11. The removal of the auxiliary line 13 is achieved by using a dicing blade having a blade width wider than the line width of the auxiliary line 13. FIG. 3 is a view showing the relationship between the auxiliary line 13 and the blade width of the dicing blade used in the present manufacturing process in accordance with such a purpose. The insulating film 10 is cut along the sub-line 13 using a dicing blade having a blade width W2 with respect to the sub-line 13 having the line width W1. As a result, the lines 11a to 11d of the circuit pattern 11 are electrically separated from each other. The width of the insulating film 10 cut by the dicing blade having the blade width W2 is actually wider than the blade width. In one preferred embodiment, when the blade width of the dicing blade is about 150 to 250 μm, the auxiliary line 13 is a fine line of 100 μm or less, more preferably 50 μm.
[0024]
FIG. 2 is an enlarged view of a part of FIG. 1 and shows the connection relationship between the circuit pattern 11 and the conductor pattern 14. As shown in the figure, the vertical lines 13a and the horizontal lines 13b of the sub-lines of the conductor pattern extend around each circuit pattern 11. This figure also shows the specific configuration of the circuit pattern 11, that is, the land 11a, the connection land 11b, and the line segment 11c as described above. In the example of the figure, among the lands 11a of the circuit pattern 11, only the surrounding lands contribute to electrical conduction between the semiconductor chip and the external substrate, and a plurality of inner lands are used for heat dissipation and other purposes. It is a dummy land. In this embodiment, the dummy land is not a target for plating.
[0025]
As will be clarified in this drawing, the conductor pattern 14 further includes a bridge 13c extending from each of the vertical lines 13a and the horizontal lines 13b. Each bridge 13 c is connected to each connection land 11 b of the circuit pattern 11. As a result, the circuit pattern 11 is electrically connected to the sub-line 13 of the conductor pattern (the sub-line 13 is connected to the main line 12). Therefore, the plating process can be performed on all the circuit patterns 11 of the insulating film 10 using the conductor pattern 14. In FIG. 2, a region 16 indicated by a virtual line is a semiconductor chip mounting region.
[0026]
Next, the manufacturing process of the semiconductor package using the said insulating film 10 is demonstrated. FIG. 4 is a flowchart showing the manufacturing process, and FIG. 5 is a schematic side view corresponding to each process of FIG. Prior to this step, the insulating film 10 is prepared, and the circuit pattern 11 is subjected to desired plating. Further, an adhesive made of thermoplastic polyimide or other material is applied on the semiconductor chip mounting region of each circuit pattern 11.
[0027]
In the first step 401 and FIG. 5A, the insulating film 10 is arranged with the surface side on which the circuit pattern is formed facing up, and the semiconductor chip 51 is transferred to the region on the circuit pattern to which the adhesive is applied. In this state, it is passed through a reflow furnace to melt the adhesive and fix the semiconductor chip 51 on the insulating film 10. In the next step 402 and FIG. 5B, wire bonding is performed between the electrode pad of each semiconductor chip 51 and the connection land of the corresponding circuit pattern (conductor wire 52).
[0028]
Next, in step 403 and FIG. 5C, each semiconductor chip 51 is resin-sealed with a mold 53. In the molding process, a mold having cavities (that is, three cavities) corresponding to the regions of the blocks 15A to 15C (see FIG. 1) partitioned by the main line 12 is used. The mold compound supplied to the mold is led into each cavity through runners (in one embodiment, two runners for one cavity), and a plurality of semiconductor chips 51 arranged in the block. Cover at the same time. A region on the insulating film 10 covered with the mold 53 includes the sub-line 13 of the conductor pattern. Moreover, a part or all of the main line 12 of the conductor pattern may be included.
[0029]
In the next step 404 and FIG. 5D, solder bumps 54, that is, lands having an LGA structure as external connection terminals are formed on the back surface side of the insulating film 10. Each solder bump 54 is electrically connected to the land of the circuit pattern 11 through a via hole 55 formed in the insulating film. A metal mask having a hole corresponding to the position of the via hole 55 is arranged along the back surface of the insulating film 10 and the solder paste 54 is filled in the hole using a squeegee, and then the solder bump 54 is formed through a reflow furnace. Can do. However, it will be apparent to those skilled in the art that the process of the present invention can also be applied to the manufacture of a package with a BGA structure in which solder balls are transferred and fixed onto via holes filled with solder.
[0030]
Next, in Step 405 and FIG. 5E, the insulating film 10 and the mold 53 are diced using a dicing blade 56 and separated into individual semiconductor packages 58. Dicing is performed by fixing the insulating film 10 with the mold side down on the dicing tape 57 as shown in the figure, and using a dicing blade having a blade width wider than the line width of the sub-line 13 of the conductor pattern as described above, This is performed at the position of the sub line 13. As a result, the insulating film 10 and the mold 53 are divided into semiconductor package units, and the sub-wires 13 that electrically connect the wirings in the circuit patterns are removed.
[0031]
As described above, a large number of semiconductor packages 58 are simultaneously manufactured using the insulating film 10. In the above manufacturing, the region surrounded by the main line 12 of the conductor pattern on the insulating film 10 is used as a region of the substrate of the semiconductor package (except for the region of the sub-line 13 removed by dicing) and discarded. The area on the insulating film is only a small area outside the main line 12. Conventionally, the area discarded on the insulating film, which was 40 to 50%, has been reduced to about 6% in one embodiment of the present invention.
[0032]
The embodiments of the present invention have been described with reference to the drawings. It is clear that the scope of application of the present invention is not limited to the matters shown in the above embodiment. In the above embodiment, the semiconductor chip is connected to the circuit pattern on the insulating film by wire bonding. However, the insulating film of the present invention and the above manufacturing method are also preferably used in a package by so-called flip chip mounting, which is mounted with the main surface of the semiconductor chip down.
[0033]
【The invention's effect】
As described above, according to the present invention, the number of semiconductor packages that can be manufactured from one insulating film is dramatically increased, and the productivity is improved. In the manufacture of semiconductor packages using the present insulating film, the area discarded on the insulating film and the amount of mold compound used is minimized, which lowers the cost of the semiconductor package.
Further, even when designing a plurality of insulating films having circuit patterns of different planar sizes, it is not necessary to change the basic configuration of the conductor pattern for plating, and the design efficiency is improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a pattern configuration on an insulating film according to an embodiment of the present invention.
2 is an enlarged view of a part of FIG. 1, showing a connection relationship between a circuit pattern and a conductor pattern.
FIG. 3 is a diagram showing a relationship between a sub-line and a blade width of a dicing blade used in the manufacturing process.
FIG. 4 is a flowchart showing a manufacturing process according to the present invention.
5 is a schematic side view corresponding to each step of FIG. 4;
FIG. 6 is a view showing a pattern configuration on a flexible insulating film having a conventional structure used for manufacturing a semiconductor package.
FIG. 7 is a view showing a manufacturing process of a conventional semiconductor package.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Insulating film 10a Hole 11 Circuit pattern 11a Land 11b Connection land 11c Line segment 12 Main line 12a Horizontal line 12b Vertical line 13 Subline 13a Vertical line 13b Horizontal line 13c Bridge 14 Conductor patterns 15A-15C Block 51 Semiconductor chip 52 Conductor wire 53 Mold 54 Solder Bump 55 Via hole 56 Dicing blade 57 Dicing tape 58 Semiconductor package

Claims (12)

A plurality of circuit patterns formed in the row and column directions on the main surface, each corresponding to a mounted semiconductor chip,
The circuit pattern including a main line arranged to surround the plurality of circuit patterns, and a sub-line arranged to surround the circuit patterns and electrically connecting the circuit patterns to the main line. A conductor pattern for plating power supply,
A method of manufacturing a semiconductor package using a flexible insulating film having
Preparing the insulating film;
Mounting a semiconductor chip in a predetermined region of each circuit pattern of the insulating film, and electrically connecting the circuit pattern and the semiconductor chip;
A step of resin-sealing the semiconductor chip by partitioning each region surrounded by the main line of the conductor pattern and injecting a mold resin into the mold ;
The insulating film and the mold resin are diced integrally at the position of the sub-line so that the sub-line does not remain using a dicing blade having a blade width wider than the line width of the sub-line of the conductor pattern. And separating into individual semiconductor packages,
A method of manufacturing a semiconductor package comprising: The said resin is adhere | attached on the dicing tape, the said insulating film is fixed in the said cutting process, Dicing is performed from the surface side opposite to the surface where the said semiconductor chip of the said insulating film is mounted . A method for manufacturing a semiconductor package. The method of manufacturing a semiconductor package according to claim 1, further comprising a step of electrically connecting an external connection terminal for mounting the semiconductor package to an external substrate to each of the circuit patterns after the resin sealing step. . The method of manufacturing a semiconductor package according to any one of claims 1 to 3, further comprising a step of plating each circuit pattern using the conductor pattern on the insulating film before the step of preparing the insulating film.   The manufacturing method of the semiconductor package in any one of Claim 1 thru | or 4 with which the main line of the said conductor pattern is formed for every pattern group which consists of a predetermined number of circuit patterns in the length direction of the said insulating film.   A main line of the conductor pattern has a pair of first lines extending on both sides in the length direction of the insulating film, and a second line extending between the pattern groups and having both ends connected to the pair of first lines. A method for manufacturing a semiconductor package according to claim 5.   The method of manufacturing a semiconductor package according to claim 5 or 6, wherein the sub-line of the conductor pattern includes a grid-like line disposed so as to surround each circuit pattern in the main line.   The method of manufacturing a semiconductor package according to claim 7, wherein the sub-line of the conductor pattern includes a plurality of bridges connecting the lattice-shaped lines and the circuit patterns.   The method of manufacturing a semiconductor package according to claim 5, wherein a line width of the sub-line of the conductor pattern is 100 μm or less.   The method for manufacturing a semiconductor package according to claim 5, wherein a line width of a main line of the conductor pattern is 0.6 mm or more.   The semiconductor package according to any one of claims 5 to 10, wherein the insulating film includes a via hole for mounting an external connection terminal for electrically connecting the circuit pattern and an external substrate under each circuit pattern. Manufacturing method.   The method for manufacturing a semiconductor package according to claim 5, wherein the insulating film is made of a polyimide resin.

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