JP4029259B2 - Semiconductor device, memory system and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a static random access memory (SRAM), a memory system including the semiconductor device, and an electronic apparatus.
[0002]
[Background Art and Problems to be Solved by the Invention]
An SRAM, which is a kind of semiconductor memory device, has the characteristics that the system can be simplified because the refresh operation is not required and the power consumption is low. For this reason, SRAM is used suitably for the memory of electronic devices, such as a mobile phone, for example.
[0003]
An object of the present invention is to provide a semiconductor device that can be highly integrated, a memory system including the semiconductor device, and an electronic apparatus.
[0004]
[Means for Solving the Problems]
(1) A semiconductor device according to the present invention includes:
A semiconductor device comprising a memory cell including a first load transistor, a second load transistor, a first drive transistor, a second drive transistor, a first transfer transistor and a second transfer transistor,
(A) a first active region extending in a first direction and in which the first and second load transistors are formed;
(B) a second active region extending in a first direction and in which the first and second drive transistors and the first and second transfer transistors are formed;
(C) extends in the second direction, is located in the first conductive layer that is an upper layer of the first and second active regions, and intersects the second active region in plan view. A first word line located and including a gate electrode of the first transfer transistor;
(D) extending in the second direction, located in the first conductive layer, and intersecting the second active region in plan view, and of the second transfer transistor A second word line including a gate electrode;
(E) extending in a second direction, located in the first conductive layer, and intersecting the first and second active regions in plan view, and the first A first gate-gate electrode layer located between a word line and the second word line and including a gate electrode of the first load transistor and the first drive transistor;
(F) extends in the second direction, is positioned in the first conductive layer, and is positioned to intersect with the first and second active regions in plan view, and the first A second gate-gate electrode layer positioned between a word line and the second word line and including a gate electrode of the second load transistor and the second drive transistor;
(G) a power supply line extending in the first direction and located on the upper layer of the first conductive layer and connected to the sources of the first and second load transistors;
(H) a bit line extending in the first direction and located in an upper layer of the first conductive layer and connected to the first transfer transistor;
(I) a / bit line that extends in the first direction, is located above the first conductive layer, is connected to the second transfer transistor, and is paired with the bit line; ,
Is provided.
[0005]
Here, the “active region” refers to an element formation region defined by an element isolation region. Specifically, a region where an impurity diffusion layer is formed, a region where a channel under a gate electrode is formed, including.
[0006]
When a defect occurs in a certain bit line or / bit line (hereinafter referred to as a bit line), the defective bit line is replaced with a redundant bit line. For this replacement, processing for disconnecting the defective bit line from the power source and processing for disconnecting the power source lines of the plurality of memory cells connected to the defective bit line from the power source are performed.
[0007]
For this processing, it is necessary to provide a power supply line extending in the same direction as the bit line and connect a plurality of memory cells connected to the bit line to the same power supply line. Therefore, for example, when the bit line extends in the Y direction and the power supply line of the memory cell extends in the X direction, for example, a common power supply line extending in the Y direction is provided for each predetermined number of bit lines. Connect the power line. When a function failure with current such as a defective bit line occurs, the common power supply line is disconnected from the power supply. In this configuration, a space for the common power supply line is required, and the degree of integration of the memory cell array is reduced.
[0008]
According to the present invention, since the bit lines and the power supply lines of the memory cells extend in the same direction, it is not necessary to provide a common power supply line extending in the same direction as the bit lines for every predetermined number of bit lines. Therefore, according to the present invention, the degree of integration of the memory cell array can be improved. The power line is, for example, V _DD Wiring.
[0009]
(2) The semiconductor device according to the present invention can be as follows.
[0010]
There are a plurality of the memory cells,
The bit line and / bit line pair includes a plurality of first bit line / bit line pairs and a plurality of second bit line / bit line pairs,
A set of the first bit line and / bit line pair, the second bit line and / bit line pair, and the memory cell of the first bit line / bit line pair; The memory cell of the second bit line / bit line pair shares the power line.
[0011]
According to the present invention, since the memory cells of the first bit line / bit line pair and the second bit line / bit line pair share the power line, the memory cell array is integrated. You can raise the degree.
[0012]
(3) The semiconductor device according to the present invention can be as follows.
[0013]
There are a plurality of the memory cells,
There are a plurality of pairs of the bit line and the / bit line,
The power line of the memory cell of one bit line and / bit line pair is connected to the power line of the memory cell of another bit line / bit line pair via a disconnection circuit Has been.
[0014]
According to the present invention, since the power line of the memory cell of one bit line and / or a pair of bit lines is isolated from the power line of the memory cell of another bit line and / or a pair of bit lines, When this occurs, only the pair including the defective bit line can be replaced. As described above, according to the present invention, since the bit line defect can be remedied for each pair of bit lines and / or bit lines, the degree of integration of the memory cell array can be improved.
[0015]
(4) The semiconductor device according to the present invention can be as follows.
[0016]
In the memory cell,
The power supply line and the bit line / bit line pair are arranged in different layers.
[0017]
(5) The semiconductor device according to the present invention can be as follows.
[0018]
The memory cell is
(J) extending in the second direction and located in a second conductive layer that is an upper layer of the first conductive layer, and the drain of the first load transistor and the drain of the first drive transistor A first drain-drain connection layer for connecting,
(K) a second drain-drain extending in the second direction, located in the second layer conductive layer, and connecting the drain of the second load transistor and the drain of the second drive transistor A connection layer;
(L) a first drain − located in a third conductive layer, which is an upper layer of the second conductive layer, and connecting the first drain-drain connection layer and the second gate-gate electrode layer; A gate connection layer;
(M) a second drain-gate connection layer located in the third conductive layer and connecting the second drain-drain connection layer and the first gate-gate electrode layer;
Is provided.
[0019]
A flip-flop is configured by making a predetermined connection to the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor. According to the present invention, a flip-flop is configured using three conductive layers (gate-gate electrode layer, drain-drain connection layer, drain-gate connection layer). For this reason, the pattern of each layer can be simplified (for example, a substantially linear pattern) compared with the case where a flip-flop is formed using two conductive layers. As described above, according to the present invention, the pattern of each layer can be simplified. For example, the memory cell size is 2.5 μm. ² The following fine semiconductor device can be obtained.
[0020]
(6) The semiconductor device according to the present invention can be as follows.
[0021]
The memory cell is
(N) a local wiring layer for a ground line, which has a pattern extending in a second direction, is located in the second layer conductive layer, and is connected to the sources of the first and second drive transistors;
(O) a bit line contact pad layer located in the second conductive layer and connected to the first transfer transistor;
(P) a bit line contact pad layer located in the second conductive layer and connected to the second transfer transistor;
(Q) a ground line having a pattern extending in the second direction, located in a fourth conductive layer that is an upper layer of the third conductive layer, and connected to the local wiring layer for the ground line;
(R) a main word line having a pattern extending in the second direction and located in the fourth conductive layer;
(S) a local wiring layer for bit lines that has a pattern extending in the second direction, is located in the fourth conductive layer, and is connected to the contact pad layer for bit lines;
(T) a / bit line local wiring layer having a pattern extending in the second direction, located in the fourth conductive layer, and connected to the / bit line contact pad layer;
With
The power line is located in the second conductive layer,
The bit line is located in a fifth conductive layer, which is an upper layer of the fourth conductive layer, and is connected to the local wiring layer for the bit line;
The / bit line is located in the fifth conductive layer and is connected to the / bit line local wiring layer.
[0022]
According to the present invention, the power supply line, the ground line, the main word line, the bit line, and the / bit line can be arranged in a balanced manner. The local wiring layer for the ground line is used for connection between the sources of the first and second drive transistors and the ground line. The bit line contact pad layer and the bit line local wiring layer are used for connection between the bit line and the first transfer transistor. The / bit line contact pad layer and the / bit line local wiring layer are used to connect the / bit line and the second transfer transistor. The ground wire is, for example, V _SS Wiring. When the main word line is provided, the above word line becomes a sub word line.
[0023]
(7) The semiconductor device according to the present invention can be as follows.
[0024]
The first and second active regions, the first and second gate-gate electrode layers, and the first and second word lines have a substantially linear pattern.
[0025]
These constitute the bulk layer. According to the present invention, since these have a substantially linear pattern, that is, a simple pattern, the bulk layer can be miniaturized.
[0026]
(8) The semiconductor device according to the present invention can be as follows.
[0027]
The size of the memory cell is 2.5 μm ² It is as follows.
[0028]
(9) A memory system according to the present invention includes the semiconductor device according to any one of (1) to (8).
[0029]
(10) An electronic apparatus according to the present invention includes the semiconductor device according to any one of (1) to (8).
[0030]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described. In this embodiment, the semiconductor device according to the present invention is applied to an SRAM. First, an outline of the structure of the SRAM according to the present embodiment will be described, and then the details of the structure will be described.
[0031]
[Outline of SRAM structure]
FIG. 1 is an equivalent circuit diagram of the SRAM according to the present embodiment. The SRAM according to this embodiment is a type in which one memory cell is configured by six MOS field effect transistors. That is, the n-channel type driving transistor Q _Three And p-channel load transistor Q _Five Thus, one CMOS inverter is configured. Further, the n-channel type driving transistor Q _Four And p-channel load transistor Q ₆ Thus, one CMOS inverter is configured. A flip-flop is formed by cross-coupling the two CMOS inverters. The flip-flop and the n-channel transfer transistor Q ₁ , Q ₂ Thus, one memory cell is configured.
[0032]
As shown in FIGS. 2 to 7, the SRAM memory cell according to the present embodiment has a structure having five conductive layers above the field. Hereinafter, FIGS. 2 to 7 will be briefly described with reference to FIG. Note that the symbol R in these drawings indicates a formation region of one memory cell.
[0033]
FIG. 2 is a plan view showing the field, and includes active regions 11 and 13 having a pattern extending substantially linearly in the Y direction. FIG. 3 is a plan view showing the first conductive layer, and the gate-gate electrode layers 21a and 21b having an I-shaped pattern extending in the X direction, and a sub-pattern having a pattern extending substantially linearly in the X direction. It includes word lines 23a and 23b. The gate-gate electrode layer 21a is composed of the drive transistor Q _Three And load transistor Q _Five The gate-gate electrode layer 21b includes the drive transistor Q. _Four And load transistor Q ₆ The sub-word line 23a includes a transfer transistor Q. ₁ The sub-word line 23b includes a transfer transistor Q. ₂ Of the gate electrode. FIG. 4 is a plan view showing the second conductive layer. The drain-drain connection layer 31a has an I-shaped pattern extending in the X direction, and the drain-drain connection layer 31b has an L-shaped pattern. V having a pattern extending substantially linearly in the Y direction _DD Wiring (power supply line) 33 and the like are included. FIG. 5 is a plan view showing the third conductive layer, and includes a drain-gate connection layer 41a having an L-shaped pattern and a drain-gate connection layer 41b having a U-shaped pattern. FIG. 6 is a plan view showing the fourth conductive layer. The bit line local wiring layer 51a, the / bit line local wiring layer 51b, the main word line 53, and V having a pattern extending substantially linearly in the X direction. _SS Wiring (ground wire) 55 is included. FIG. 7 is a plan view showing the fifth conductive layer, and includes a pair of bit line 61a and / or bit line 61b having a pattern extending substantially linearly in the Y direction.
[0034]
[Details of SRAM structure]
Details of the structure of the SRAM according to the present embodiment will be described in order from the lower layer with reference to FIGS. 8 is a plan view showing the field and the first conductive layer, FIG. 9 is a plan view showing the field, the first conductive layer, and the second conductive layer, and FIG. 10 is the second conductive layer and the first conductive layer. FIG. 11 is a plan view showing a three-layer conductive layer, FIG. 11 is a plan view showing a first-layer conductive layer and a third-layer conductive layer, and FIG. 12 is a plan view showing a second-layer conductive layer and a fourth-layer conductive layer. 13 is a plan view showing the fourth layer conductive layer and the fifth layer conductive layer, FIG. 14 is a cross-sectional view taken along line A1-A2 of FIGS. 2 to 13, and FIG. FIG. 14 is a cross-sectional view taken along line B1-B2 of FIG.
[0035]
{Field, first conductive layer}
First, the fields will be described. As shown in FIG. 2, the field has active regions 11 and 13 and an element isolation region 19. The active regions 11 and 13 are formed on the surface of the silicon substrate.
[0036]
The active region 11 has a pattern extending substantially linearly in the Y direction. The active region 11 extends to the formation region of another memory cell positioned above and below in FIG. 2 with respect to the formation region R of the memory cell. The active region 11 has a drive transistor Q _Three , Q _Four 11a and transfer transistor Q ₁ , Q ₂ And a region 11b in which is formed. The width of the region 11a is, for example, 0.22 to 0.33 μm, and the width of the region 11b is, for example, 0.16 to 0.20 μm.
[0037]
The active region 13 has a pattern extending substantially linearly in the Y direction, and is formed at a distance from the active region 11. Both ends of the active region 13 stop extending in the memory cell formation region R. The active region 13 includes a load transistor Q _Five , Q ₆ Is formed. The width of the active region 13 is, for example, 0.16 to 0.20 μm.
[0038]
The active region 11 and the active region 13 are separated from each other by an element isolation region 19 (depth, for example, 0.35 to 0.45 μm). As the element isolation region 19, for example, there is STI (shallow trench isolation). The length of the memory cell formation region R in the X direction is, for example, 1.0 to 1.4 μm, and the length of the Y direction is, for example, 1.6 to 2.0 μm.
[0039]
The A1-A2 cross section and B1-B2 cross section of the field shown in FIG. 2 are as shown in FIGS. 14 and 15, respectively. These cross sections show a p-well 12, an n-well 14 and the like formed in the silicon substrate.
[0040]
Next, the first conductive layer located in the upper layer of the field will be described with reference to FIGS. A set of gate-gate electrode layers 21a and 21b are arranged in parallel in the formation region R of one memory cell. The gate-gate electrode layers 21a and 21b intersect the active regions 11 and 13 when viewed in plan. Since the gate-gate electrode layers 21a and 21b are I-shaped patterns, they are almost linear patterns. The gate-gate electrode layer 21a is composed of the drive transistor Q _Three And load transistor Q _Five These gate electrodes are connected to each other. The gate-gate electrode layer 21b is connected to the driving transistor Q. _Four And load transistor Q ₆ These gate electrodes are connected to each other. Driving transistor Q _Three , Q _Four The gate length is, for example, 0.12 to 0.15 μm. Load transistor Q _Five , Q ₆ The gate length is, for example, 0.14 to 0.17 μm.
[0041]
The sub word lines 23a and 23b are located apart from the active region 13 when viewed in plan, and are positioned so as to intersect with the active region 11 when viewed in plan. Gate-gate electrode layers 21a and 21b are located between the sub word line 23a and the sub word line 23b. The sub word line 23a is connected to the transfer transistor Q. ₁ The sub word line 23b is connected to the transfer transistor Q. ₂ It becomes a gate electrode. Transfer transistor Q ₁ , Q ₂ The gate length is, for example, 0.14 to 0.17 μm.
[0042]
The gate-gate electrode layers 21a and 21b and the sub word lines 23a and 23b have, for example, a structure in which a silicide layer is formed on a polysilicon layer.
[0043]
The A1-A2 cross section and B1-B2 cross section of the first conductive layer shown in FIGS. 3 and 8 are as shown in FIGS. 14 and 15, respectively. In these cross sections, the sub-word line 23a and the gate-gate electrode layer 21a appear.
[0044]
Next, n formed in the active region 11 ⁺ The type impurity regions 15a, 15b, 15c, 15d, and 15e will be described with reference to FIG. N in order to sandwich the sub word line 23a in plan view. ⁺ Type impurity regions 15a and n ⁺ N-type impurity region 15b and n-type electrode region 21a so as to sandwich n-type impurity region 15b. ⁺ Type impurity regions 15b and n ⁺ N-type impurity region 15c is located and n-side so as to sandwich gate-gate electrode layer 21b ⁺ Type impurity regions 15c and n ⁺ N type impurity region 15d is located, and n is arranged so as to sandwich sub word line 23b. ⁺ Type impurity regions 15d and n ⁺ A type impurity region 15e is located.
[0045]
n ⁺ The type impurity region 15a is formed by the transfer transistor Q ₁ Source or drain. n ⁺ The type impurity region 15b is formed by the transfer transistor Q ₁ Source or drain, driving transistor Q _Three It becomes the drain of. n ⁺ The type impurity region 15c is connected to the driving transistor Q. _Three , Q _Four Become a common source. n ⁺ The type impurity region 15d is connected to the driving transistor Q. _Four Drain, transfer transistor Q ₂ Source or drain. n ⁺ The type impurity region 15e is formed by the transfer transistor Q ₂ Source or drain.
[0046]
Next, p formed in the active region 13 is formed. ⁺ The type impurity regions 17a, 17b, and 17c will be described with reference to FIG. As viewed in plan, the gate-gate electrode layer 21a is sandwiched between p ⁺ Type impurity regions 17a and p ⁺ P-type impurity region 17b is located and p-type so as to sandwich gate-gate electrode layer 21b. ⁺ Type impurity regions 17b and p ⁺ A type impurity region 17c is located. p ⁺ The type impurity region 17a is connected to the load transistor Q _Five The drain of p ⁺ The type impurity region 17c is connected to the load transistor Q ₆ The drain of p ⁺ The type impurity region 17b is connected to the load transistor Q _Five , Q ₆ Become a common source. As shown in FIG. ⁺ Type impurity regions 15a, 15b, p ⁺ A type impurity region 17a appears.
[0047]
As shown in FIGS. 14 and 15, an interlayer insulating layer 71 such as a silicon oxide layer is formed so as to cover the field and the first conductive layer. The interlayer insulating layer 71 is planarized by CMP.
[0048]
{Second layer conductive layer}
The second conductive layer will be described with reference to FIGS. The second conductive layer is located above the first conductive layer. The second conductive layer includes drain-drain connection layers 31a, 31b, V _DD Wiring (power line) 33, bit line contact pad layer 35a, bit line contact pad layer 35b, V _SS A local wiring layer for wiring (local wiring layer for grounding line) 37 is included. The second conductive layer is connected to the field n via a contact conductive portion 73 (hereinafter referred to as field / second layer-contact conductive portion 73) which is a conductive portion connecting the second conductive layer and the field. ⁺ Type impurity region and p ⁺ Connected to the type impurity region.
[0049]
Between the drain-drain connection layer 31a and the drain-drain connection layer 31b, the drain-drain connection layers 31a, 31b are positioned so that the gate-gate electrode layers 21a, 21b are positioned in plan view. . The drain-drain connection layer 31a has n ⁺ Type impurity region 15b (drain) and p ⁺ It is located above the type impurity region 17a (drain). The I-shaped drain-drain connection layer 31a has a first end 31a1 with a field / second layer-contact conductive portion 73 interposed therebetween. ⁺ P-type impurity region 15b (drain) is connected to the second end portion 31a2 of the second impurity region 15b via the field / second layer-contact conductive portion 73. ⁺ It is connected to the type impurity region 17a (drain). The drain-drain connection layer 31b has n ⁺ Type impurity region 15d (drain) and p ⁺ It is located above the type impurity region 17c (drain). The L-shaped drain-drain connection layer 31b has n-type n-type contact via the field / second layer-contact conductive portion 73 at the first end 31b1. ⁺ P-type impurity region 15d (drain) is connected to the p-type impurity region 15d (drain) via the field / second-layer contact conductive portion 73 at the corner 31b3. ⁺ It is connected to the type impurity region 17c (drain). The width of the drain-drain connection layers 31a and 31b is, for example, 0.16 to 0.20 μm.
[0050]
V _DD The width of the wiring (power supply line) 33 is, for example, 0.16 to 0.20 μm. V _DD The protrusion 33a of the wiring 33 extends in the X direction, and p ⁺ It is located above the type impurity region 17b (source). The convex portion 33a is connected to p through the field / second layer-contact conductive portion 73. ⁺ It is connected to the type impurity region 17b.
[0051]
V _SS The local wiring layer for wiring (local wiring layer for grounding line) 37 is n ⁺ It is located above the type impurity region 15c (source). V _SS The local wiring layer 37 for wiring is n through the field / second layer-contact conductive portion 73. ⁺ It is connected to the type impurity region 15c. V _SS The local wiring layer 37 for wiring is V _SS Wiring 55 (FIG. 6) and drive transistor Q _Three , Q _Four The source of n ⁺ It functions as a wiring layer for connecting the type impurity region 15c. V _SS The local wiring layer 37 for wiring is shared by the memory cell in the formation region R and the memory cell located on the right side in FIG.
[0052]
The bit line contact pad layer 35a includes n ⁺ It is located above the type impurity region 15a. The bit line contact pad layer 35a is connected to n through the field / second layer-contact conductive portion 73. ⁺ It is connected to the type impurity region 15a. The bit line contact pad layer 35a includes a bit line 61a (FIG. 7) and a transfer transistor Q. ₁ N to become the source and drain of ⁺ It functions as a pad layer for connecting the type impurity region 15a. The bit line contact pad layer 35a is shared by the memory cell in the formation region R and the memory cell located above the formation region R in FIG.
[0053]
/ Bit line contact pad layer 35b has n ⁺ It is located above the type impurity region 15e. / The bit line contact pad layer 35b is connected via the field / second layer-contact conductive portion 73 to n ⁺ It is connected to the type impurity region 15e. The / bit line contact pad layer 35b includes the / bit line 61b (FIG. 7) and the transfer transistor Q. ₂ N to become the source and drain of ⁺ It functions as a pad layer for connecting the type impurity region 15e. The bit line contact pad layer 35b is shared by the memory cells in the formation region R and the memory cells located below the formation region R in FIG.
[0054]
Next, the cross-sectional structure of the second conductive layer will be described with reference to FIG. The second conductive layer can be composed of, for example, only a refractory metal nitride layer. The thickness of the second conductive layer is, for example, 100 to 200 nm. An example of the refractory metal nitride layer is a titanium nitride layer. Further, the second conductive layer may be any one of the following aspects. 1) It may have a structure in which a refractory metal nitride layer 32 is formed on a metal layer 30 made of a refractory metal. In this case, the metal layer 30 made of a refractory metal serves as an underlay, for example, a titanium layer. Examples of the material for the metal layer of the refractory metal include titanium and tungsten. 2) The second conductive layer may be composed only of a refractory metal layer.
[0055]
Next, the cross-sectional structure of the field / second layer-contact conductive portion 73 will be described with reference to FIG. The interlayer insulating layer 71 has n in the field. ⁺ Type impurity region and p ⁺ A plurality of through holes 75 exposing the type impurity region are formed. In these through holes 75, field / second layer-contact conductive portions 73 are embedded. Field / second layer-contact conductive portion 73 includes a plug 77 embedded in through hole 75 and a barrier layer 79 located on the bottom surface and side surface of through hole 75. An example of the material of the plug 77 is tungsten. The barrier layer 79 is preferably composed of a metal layer made of a refractory metal and a refractory metal nitride layer formed on the metal layer. An example of the material for the metal layer made of a refractory metal is titanium. An example of the material of the refractory metal nitride layer is titanium nitride. The diameter of the upper end portion of the through hole 75 is, for example, 0.18 to 0.22 μm, and the diameter of the lower end portion is, for example, 0.14 to 0.18 μm.
[0056]
As shown in FIGS. 14 and 15, an interlayer insulating layer 81 such as a silicon oxide layer is formed so as to cover the second conductive layer. The interlayer insulating layer 81 is planarized by CMP.
[0057]
{Third conductive layer}
The third conductive layer will be described with reference to FIGS. The third conductive layer is located above the second conductive layer. The third conductive layer includes drain-gate connection layers 41a and 41b. The width of the drain-gate connection layers 41a and 41b is, for example, 0.16 to 0.20 μm.
[0058]
The drain-gate connection layer 41a has an L-shaped pattern, and the first end 41a1 is located above the first end 31a1 of the drain-drain connection layer 31a (FIG. 10). The first end portion 41a1 of the drain-gate connection layer 41a is a contact conductive portion 83 (hereinafter referred to as a second layer / third layer-contact conductive layer) which is a conductive portion connecting the third conductive layer and the second conductive layer. 10 and the first end portion 31a1 of the drain-drain connection layer 31a (FIG. 10). The second end 41a2 of the drain-gate connection layer 41a is located above the center of the gate-gate electrode layer 21b (FIG. 11). The second end portion 41a2 of the drain-gate connection layer 41a is a contact conductive portion 93 (hereinafter referred to as a first layer / third layer-contact conductive layer) which is a conductive portion connecting the third conductive layer and the first conductive layer. 11 and the central portion of the gate-gate electrode layer 21b (FIG. 11).
[0059]
The drain-gate connection layer 41b is U-shaped, and the first end 41b1 is located above the second end 31b2 of the drain-drain connection layer 31b (FIG. 10). The first end 41b1 of the drain-gate connection layer 41b is connected to the second end 31b2 of the drain-drain connection layer 31b via the second layer / third layer-contact conductive portion 83 (FIG. 10). ). The second end 41b2 of the drain-gate connection layer 41b is located above the central portion of the gate-gate electrode layer 21a (FIG. 11). The second end 41b2 of the drain-gate connection layer 41b is connected to the center of the gate-gate electrode layer 21a via the first layer / third layer-contact conductive portion 93 (FIG. 11).
[0060]
Next, the cross-sectional structure of the third conductive layer will be described with reference to FIGS. The third conductive layer can have a structure similar to that described for the second conductive layer.
[0061]
Next, the sectional structure of the second layer / third layer-contact conductive portion 83 will be described with reference to FIG. Second and third layer-contact conductive portions 83 are buried in the through holes 85 that penetrate the interlayer insulating layer 81. The second layer / third layer-contact conductive portion 83 can have the same structure as that described in the field / second layer-contact conductive portion 73.
[0062]
Next, the cross-sectional structure of the first layer / third layer-contact conductive portion 93 will be described with reference to FIG. The first layer / third layer-contact conductive portion 93 is buried in a through hole 95 penetrating the two interlayer insulating layers 71 and 81. In this cross section, the first layer / third layer-contact conductive portion 93 is connected to the gate-gate electrode layer 21a. The first layer / third layer-contact conductive portion 93 can have the same structure as that described in the field / second layer-contact conductive portion 73. The diameter of the upper end portion of the through hole 95 is, for example, 0.18 to 0.22 μm, and the diameter of the lower end portion is, for example, 0.14 to 0.18 μm.
[0063]
As shown in FIGS. 14 and 15, an interlayer insulating layer 101 such as a silicon oxide layer is formed so as to cover the third conductive layer. The interlayer insulating layer 101 is planarized by CMP.
[0064]
{Fourth conductive layer}
The fourth conductive layer will be described with reference to FIGS. The fourth conductive layer is located above the third conductive layer. The fourth conductive layer includes a bit line local wiring layer 51a, a / bit line local wiring layer 51b, a main word line 53, V, and a pattern extending substantially linearly in the X direction. _SS Wiring (ground wire) 55 is included. Between the bit line local wiring layer 51a and the bit line local wiring layer 51b, the main word line 53, V _SS The wiring 55 is located.
[0065]
V _SS The wiring 55 is V _SS A contact conductive portion 113 (hereinafter referred to as a second layer / fourth layer-contact conductive portion 113) which is located above the local wiring layer 37 for wiring and connects the fourth conductive layer and the second conductive layer. V) through V _SS It is connected to the local wiring layer 37 for wiring (FIG. 12). V _SS The width of the wiring 55 is, for example, 0.4 to 1.0 μm.
[0066]
The main word line 53 is located above the drain-drain connection layer 31a. By main word line 53, sub word lines 23a and 23b (FIG. 8) are activated and deactivated. The width of the main word line 53 is, for example, 0.18 to 0.24 μm. In the present embodiment, the word line has a structure including a sub word line and a main word line, but a structure in which the main word line is not provided may be used.
[0067]
The bit line local wiring layer 51a is located above the bit line contact pad layer 35a. The bit line local wiring layer 51a includes a bit line 61a (FIG. 7) and a transfer transistor Q. ₁ N to become the source and drain of ⁺ It functions as a wiring layer for connecting the type impurity region 15a (FIG. 8). One end 51a1 of the bit line local wiring layer 51a is connected to the bit line contact pad layer 35a via the second layer / fourth layer-contact conductive portion 113. The local wiring layer 51a for bit lines is shared by the memory cells in the formation region R and the memory cells located above the formation region R in FIG. The width of the bit line local wiring layer 51a is, for example, 0.20 to 0.40 μm.
[0068]
The / bit line local wiring layer 51b is located above the / bit line contact pad layer 35b. / Bit line local wiring layer 51b includes bit line 61b (FIG. 7) and transfer transistor Q. ₂ N to become the source and drain of ⁺ It functions as a wiring layer for connecting the type impurity region 15e (FIG. 8). The first end portion 51b1 of the / bit line local wiring layer 51b is connected to the / bit line contact pad layer 35b via the second layer / fourth layer-contact conductive portion 113. / Bit line local interconnection layer 51b is shared by the memory cell in formation region R and the memory cell located below in FIG. The width of the bit line local wiring layer 51b is, for example, 0.20 to 0.40 μm.
[0069]
Next, the cross-sectional structure of the fourth conductive layer will be described with reference to FIG. The fourth conductive layer has, for example, a structure in which a refractory metal nitride layer 52, a metal layer 54, and a refractory metal nitride layer 56 are stacked in this order from the bottom. Specific examples of each layer are as follows. An example of the refractory metal nitride layer 52 is a titanium nitride layer. Examples of the metal layer 54 include an aluminum layer, a copper layer, or an alloy layer thereof. An example of the refractory metal nitride layer 56 is a titanium nitride layer. Further, the fourth conductive layer may be any one of the following aspects. 1) An embodiment composed only of a refractory metal nitride layer. 2) An embodiment composed only of a metal layer.
[0070]
A hard mask layer 59 made of a silicon oxide layer is formed on the fourth conductive layer. The fourth conductive layer is patterned using the hard mask layer 59 as a mask. This is because it is difficult to pattern the fourth conductive layer using only the resist as a mask due to miniaturization of the memory cell.
[0071]
Next, the cross-sectional structure of the second layer / fourth layer-contact conductive portion 113 will be described with reference to FIG. The second layer / fourth layer-contact conductive portion 113 is buried in a through hole 115 penetrating the two interlayer insulating layers 81 and 101. In this cross section, the second layer / fourth layer-contact conductive portion 113 connects the bit line contact pad layer 35a and the bit line local wiring layer 51a. The second layer / fourth layer-contact conductive portion 113 can have the same structure as that described in the field / second layer-contact conductive portion 73. The diameter of the upper end portion of the through hole 115 is, for example, 0.18 to 0.24 μm, and the diameter of the lower end portion is, for example, 0.14 to 0.18 μm.
[0072]
As shown in FIGS. 14 and 15, an interlayer insulating layer 121 such as a silicon oxide layer is formed so as to cover the fourth conductive layer. The interlayer insulating layer 121 is planarized by CMP.
[0073]
{Fifth conductive layer}
The fifth conductive layer will be described with reference to FIGS. The fifth conductive layer is located above the fourth conductive layer. The fifth conductive layer includes a pair of bit lines 61a and / bit lines 61b having a pattern extending substantially linearly in the Y direction. / A signal complementary to the signal flowing through the bit line 61a flows through the bit line 61b. The width of the bit line 61a and / bit line 61b is, for example, 0.20 to 0.26 μm.
[0074]
The bit line 61a is connected to a bit via a contact conductive portion 133 (hereinafter referred to as a fourth layer / fifth layer-contact conductive portion 133) which is a conductive portion connecting the fifth conductive layer and the fourth conductive layer. It is connected to one end 51a1 of the local wiring wiring layer 51a. The / bit line 61b is connected to the second end portion 51b2 of the / bit line local wiring layer 51b through the fourth layer / fifth layer-contact conductive portion 133.
[0075]
Next, the cross-sectional structure of the fifth conductive layer will be described with reference to FIGS. The fifth conductive layer can have a structure similar to that described for the fourth conductive layer. A hard mask layer 69 made of a silicon oxide layer is formed on the fifth conductive layer. The reason for forming the hard mask layer 69 is the same as that of the hard mask layer 59.
[0076]
Next, the cross-sectional structure of the fourth layer / fifth layer-contact conductive portion 133 will be described with reference to FIG. The fourth layer / fifth layer-contact conductive portion 133 is embedded in a through hole 135 penetrating the interlayer insulating layer 121. In this cross section, the fourth layer / fifth layer-contact conductive portion 133 connects the bit line 61a and the bit line local wiring layer 51a. The fourth layer / fifth layer-contact conductive portion 133 can have the same structure as that described in the field / second layer-contact conductive portion 73. The diameter of the upper end portion of the through hole 135 is, for example, 0.20 to 0.24 μm, and the diameter of the lower end portion is, for example, 0.18 to 0.22 μm.
[0077]
The above is the detailed structure of the SRAM according to the present embodiment.
[0078]
[Main effects of SRAM according to this embodiment]
According to this embodiment, the SRAM memory cell can be reduced in size. Details will be described below. In this embodiment, information is stored in a flip-flop of a memory cell. The flip-flop connects the input terminal (gate electrode) of one inverter to the output terminal (drain) of the other inverter, and the input terminal (gate electrode) of the other inverter to the output terminal (drain) of one inverter. Configured by connecting. That is, the flip-flop is a cross-coupled connection between the first inverter and the second inverter. When a flip-flop is configured by using two conductive layers, for example, a drain-drain connection layer that connects the drains of the inverter and a drain-gate connection layer that connects the gate of the inverter and the drain of the inverter are combined. By using two conductive layers, a cross-couple connection can be made.
[0079]
However, according to this structure, the conductive layer is formed over a region where the drain of one inverter is located, a region where the gate of the other inverter is located, and a region connecting them. Therefore, the conductive layer has a pattern having three ends (for example, a pattern having a branching portion such as a T-shape or an h-shape) or a spiral pattern in which the arm portions enter each other. In addition, as a T-shaped pattern, it is disclosed by FIG. 1 of Unexamined-Japanese-Patent No. 10-41409, for example. The h-shaped pattern is disclosed, for example, in M.Ishida, et.al., IEDM Tech.Digest (1998), FIG. The spiral pattern is disclosed in, for example, M.Ishida, et.al., IEDM Tech.Digest (1998), FIG. When such a complicated pattern is miniaturized, it is difficult to accurately reproduce the shape in the photoetching process, so that a desired pattern cannot be obtained, which hinders downsizing of the memory cell size.
[0080]
According to the present embodiment, as shown in FIGS. 3, 4, and 5, the gate-gate electrode layer (21a, 21b) that becomes the gate of the CMOS inverter, and the drain-drain connection layer that connects the drains of the CMOS inverter. (31a, 31b), drain-gate connection layers (41a, 41b) for connecting the gate of one CMOS inverter and the drain of the other CMOS inverter are formed in different layers. As described above, in the present embodiment, the flip-flop is configured using three conductive layers, so that the pattern of each layer can be simplified as compared with the case where the flip-flop is configured using two conductive layers. For example, an almost linear pattern with two ends, such as an I-shaped pattern, or an almost linear element with two ends, such as an L-shaped or U-shaped pattern Pattern. As described above, according to the present embodiment, the pattern of each layer can be simplified. For example, in the 0.12 μm generation, the memory cell size is 2.5 μm. ² The following fine SRAM can be obtained.
[0081]
[SRAM Memory Cell Array]
As a memory cell array including the SRAM memory cell of the present embodiment, there are a first example and a second example. First, the configuration and effect of the first example will be described.
[0082]
{First example}
(Constitution)
FIG. 16 is a partial plan view of a first example of a memory cell array including the SRAM memory cells of the present embodiment. In the memory cell array 200, a large number of memory cells (MC) 210 are arranged in a matrix. The memory cell (MC) 210 is formed with the memory cell described with reference to FIGS. Bit line 61a, / bit line 61b and V of each memory cell (MC) 210 _DD The wiring 33 (power supply line) extends in the Y direction, and V _SS The wiring 55 (ground line) extends in the X direction. Memory cell array 200 includes a normal memory cell array and a redundant memory cell array.
[0083]
The bit line 61a and / bit line 61b pairs include a first bit line / bit line pair 240 (hereinafter referred to as a first pair), a second bit line / bit line pair 250 (hereinafter referred to as a first bit line / bit line pair 250). A second pair), each with a plurality. The power supply V is connected to the first pair 240 and the second pair 250, that is, every two columns through the power supply disconnecting circuit 230 every two columns. _DD Connected with. By cutting the fuse of the power supply disconnecting circuit 230, the bit line 61a, the bit line 61b, and the V _DD The wiring 33 is a power source V _DD Detached from. In the first example, two columns of the redundant memory cell array are replaced every two columns of the normal memory cell array.
[0084]
In a set of the first pair 240 and the second pair 250, the memory cell (MC) 210 of the first pair 240 and the memory cell (MC) 210 of the second pair 250 are V _DD The wiring 33 (power supply line) is shared. This is connected to the memory cell (MC) 210 and V _DD The relationship with the wiring 33 will be described with reference to FIG. _DD Wiring 33 is used. For this reason, the V shown in FIG. _DD The wiring 33 is arranged so as to be shared by this memory cell and the left adjacent memory cell.
[0085]
Power supply V _DD Supplies a potential to the bit line 61a and the / bit line 61b via the bit line precharge circuit 220. Power supply V _DD Is V _DD A potential is supplied to the memory cell (MC) 210 through the wiring 33.
[0086]
(effect)
According to the first example, the integration degree of the SRAM memory cell array can be improved. Details will be described below.
[0087]
In the first example, when a defect occurs in the bit 61a line or the / bit line 61b (hereinafter sometimes simply referred to as a bit line), two columns including the defective bit line are replaced with two columns of the redundant memory cell array. The For this replacement, two columns including the defective bit line are connected to the power source V. _DD And the V of the two-column memory cell (MC) 210 including the defective bit line _DD Wiring (power line) 33 is power source V _DD The process of detaching from is performed.
[0088]
According to the first example, bit 61a line, / bit line 61b and V _DD Since the wiring 33 extends in the same direction, the common V extending in the same direction as the bit line for every predetermined number of bit lines. _DD There is no need to provide wiring (common power line). That is, for example, the bit 61a line and the / bit line 61b extend in the Y direction, and V _DD When the wiring 33 extends in the X direction, the common V extending in the Y direction for every predetermined number of bit lines. _DD Provide wiring and connect it to V _DD The wiring 33 is connected. If a bad bit line occurs, the common V _DD The wiring is disconnected from the power source. In this structure, common V _DD Space for wiring is required, and the degree of integration of the memory cell array decreases. On the other hand, according to the first example, the common V _DD A space for wiring becomes unnecessary, and the degree of integration of the memory cell array can be improved.
[0089]
{Second example}
(Constitution)
FIG. 18 is a partial plan view of a second example of the memory cell array including the SRAM memory cells of the present embodiment. The same elements as those of the first example are denoted by the same reference numerals. The second example will be described with a focus on differences from the first example.
[0090]
In the memory cell array 300 of the second example, the power supply V is supplied to each pair 260 (hereinafter referred to as a pair) of bit lines 61a and / or bit lines 61b, that is, for each column via the power supply disconnecting circuit 230. _DD Connected with. In the second example, one column of the redundant memory cell array is replaced for each column of the normal memory cell array. In order to be able to replace every column, the V of the memory cell (MC) 210 of a certain pair 260 _DD The wiring 33 (power supply line) is connected to the V of the other pair 260 of memory cells (MC) 210. _DD It is separated from the wiring 33.
This is connected to the memory cell (MC) 210 and V _DD The relationship between the wiring 33 and the wiring 33 will be described as shown in FIG. _DD Wiring 33 is used. For this reason, the V shown in FIG. _DD The wiring 33 is not shared by the memory cell and the left or right adjacent memory cell.
[0091]
(effect)
According to the second example, as in the first example, the bit 61a line, the / bit line 61b, and V _DD Since the wiring 33 extends in the same direction, a common V extending in the same direction as the bit line for every predetermined number of bit lines. _DD There is no need to provide wiring (common power line). Therefore, according to the second example, the degree of integration of the SRAM memory cell array can be improved.
[0092]
Further, the second example can improve the degree of integration of the memory cell array as compared with the first example from the following points. In the first example, for example, if the first pair 240 has a defective bit line, the second pair 250 is replaced with the first pair 240 even if the second pair 250 has no defective bit line. In contrast, in the second example, unlike the first example, only the pair 260 including the defective bit line is replaced, so that the degree of integration of the memory cell array can be increased.
[0093]
In the first example, the degree of integration of the memory cell array can be increased compared to the second example from the following points. The first example is a single V with 2 columns _DD Whereas the wiring 33 is used, the second example uses one V for one column. _DD Wiring 33 is used. Thus, the first example is more V than the second example. _DD Since the number of wirings 33 can be reduced, the degree of integration of the memory cell array can be increased.
[0094]
[Application example of SRAM to electronic equipment]
The SRAM according to the present embodiment can be applied to an electronic device such as a portable device, for example. FIG. 20 is a block diagram of a part of a mobile phone system. The CPU, SRAM, and DRAM are connected to each other by a bus line. Further, the CPU is connected to a keyboard and an LCD driver by a bus line. The LCD driver is connected to the liquid crystal display unit by a bus line. A CPU, SRAM, and DRAM constitute a memory system.
[0095]
FIG. 21 is a perspective view of a mobile phone 600 including the mobile phone system shown in FIG. The cellular phone 600 includes a main body 610 including a keyboard 612, a liquid crystal display 614, a receiver 616 and an antenna 618, and a lid 620 including a transmitter 622.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of an SRAM according to an embodiment.
FIG. 2 is a plan view showing a field of the SRAM memory cell according to the embodiment;
FIG. 3 is a plan view showing a first conductive layer of the SRAM memory cell according to the embodiment;
FIG. 4 is a plan view showing a second conductive layer of the SRAM memory cell according to the embodiment;
FIG. 5 is a plan view showing a third conductive layer of the SRAM memory cell according to the embodiment;
FIG. 6 is a plan view showing a fourth conductive layer of the SRAM memory cell according to the embodiment;
FIG. 7 is a plan view showing a fifth conductive layer of the SRAM memory cell according to the embodiment;
FIG. 8 is a plan view showing a field of the memory cell of the SRAM according to the embodiment and a first conductive layer;
FIG. 9 is a plan view showing a field, a first conductive layer, and a second conductive layer of the SRAM memory cell according to the embodiment;
FIG. 10 is a plan view showing a second conductive layer and a third conductive layer of the SRAM memory cell according to the embodiment;
FIG. 11 is a plan view showing a first conductive layer and a third conductive layer of the SRAM memory cell according to the embodiment;
FIG. 12 is a plan view showing a second conductive layer and a fourth conductive layer of the SRAM memory cell according to the embodiment;
FIG. 13 is a plan view showing a fourth conductive layer and a fifth conductive layer of the SRAM memory cell according to the embodiment;
14 is a cross-sectional view taken along line A1-A2 of FIGS.
15 is a cross-sectional view taken along line B1-B2 of FIGS.
FIG. 16 is a partial plan view of a first example of a memory cell array including SRAM memory cells according to the present embodiment;
FIG. 17 shows a memory cell (MC) and V of the first example. _DD It is a figure which shows the relationship with wiring.
FIG. 18 is a partial plan view of a second example of the memory cell array including the SRAM memory cells according to the embodiment;
FIG. 19 shows a memory cell (MC) and V of the second example. _DD It is a figure which shows the relationship with wiring.
FIG. 20 is a block diagram of a part of a mobile phone system including the SRAM according to the embodiment;
FIG. 21 is a perspective view of a mobile phone including the mobile phone system shown in FIG.
[Explanation of symbols]
11 Active region
11a area
11b area
12 p-well
13 Active region
14 n-well
15a, 15b, 15c, 15d, 15en ⁺ Type impurity region
17a, 17b, 17cp ⁺ Type impurity region
19 Element isolation region
21a, 21b Gate-gate electrode layer
23a, 23b Sub word line
30 Metal layer made of refractory metal
31a, 31b Drain-drain connection layer
31a1, 31b1 first end
31a2, 31b2 second end
31b3 corner
32 Nitride layer of refractory metal
33 V _DD Wiring (power line)
33a Convex
35a Bit line contact pad layer
35b / bit line contact pad layer
37 V _SS Local wiring layer for wiring (Local wiring layer for ground wire)
40 Metal layer made of refractory metal
41a, 41b Drain-gate connection layer
41a1, 41b1 first end
41a2, 41b2 second end
42 Nitride layer of refractory metal
51a Local wiring layer for bit lines
51a1 One end
51b / Local wiring layer for bit line
51b1 first end
51b2 second end
52 Nitride layer of refractory metal
53 Main word line
54 Metal layer
55 V _SS Wiring (ground wire)
56 Nitride layer of refractory metal
59 Hard Mask
61a bit line
61b / bit line
62 Nitride layer of refractory metal
64 metal layers
66 High melting point metal nitride layer
69 hard mask
71 Interlayer insulation layer
73 Field, second layer-contact conductive part
75 Through hole
77 plug
79 Nitride layer of refractory metal
81 Interlayer insulation layer
83 2nd and 3rd layers-Contact conductive part
85 Through hole
87 plug
89 Refractory metal nitride layer
93 1st and 3rd layers-Contact conductive part
95 Through hole
97 plug
99 Nitride layer of refractory metal
101 Interlayer insulation layer
113 2nd and 4th layer-Contact conductive part
115 through hole
117 plug
119 Nitride layer of refractory metal
121 Interlayer insulation layer
133 4th layer, 5th layer-contact conductive part
135 Through hole
137 plug
139 Nitride layer of refractory metal
200 memory cell array
210 memory cells
220 bit line precharge circuit
230 Power supply disconnection circuit
240 First bit line and / or bit line pair (first pair)
250 Second bit line and / or bit line pair (second pair)
260 Bit line and / or bit line pair
300 Memory cell array
R formation region of one memory cell

Claims (7)

A semiconductor device comprising a memory cell including a first load transistor, a second load transistor, a first drive transistor, a second drive transistor, a first transfer transistor and a second transfer transistor,
(A) a first active region extending in a first direction and in which the first and second load transistors are formed;
(B) a second active region extending in a first direction and in which the first and second drive transistors and the first and second transfer transistors are formed;
(C) extends in the second direction, is located in the first conductive layer that is an upper layer of the first and second active regions, and intersects the second active region in plan view. A first word line located and including a gate electrode of the first transfer transistor;
(D) extending in the second direction, located in the first conductive layer, and intersecting the second active region in plan view, and of the second transfer transistor A second word line including a gate electrode;
(E) extending in a second direction, located in the first conductive layer, and intersecting the first and second active regions in plan view, and the first A first gate-gate electrode layer located between a word line and the second word line and including a gate electrode of the first load transistor and the first drive transistor;
(F) extends in the second direction, is positioned in the first conductive layer, and is positioned to intersect with the first and second active regions in plan view, and the first A second gate-gate electrode layer positioned between a word line and the second word line and including a gate electrode of the second load transistor and the second drive transistor;
(G) a power supply line extending in the first direction and located on the upper layer of the first conductive layer and connected to the sources of the first and second load transistors;
(H) a bit line extending in the first direction and located in an upper layer of the first conductive layer and connected to the first transfer transistor;
(I) a / bit line that extends in the first direction, is located above the first conductive layer, is connected to the second transfer transistor, and is paired with the bit line; ,
(J) extending in the second direction and located in a second conductive layer that is an upper layer of the first conductive layer, and the drain of the first load transistor and the drain of the first drive transistor A first drain-drain connection layer for connecting,
(K) a second drain-drain extending in the second direction, located in the second layer conductive layer, and connecting the drain of the second load transistor and the drain of the second drive transistor A connection layer;
(L) a first drain − located in a third conductive layer, which is an upper layer of the second conductive layer, and connecting the first drain-drain connection layer and the second gate-gate electrode layer; A gate connection layer;
(M) a second drain-gate connection layer located in the third conductive layer and connecting the second drain-drain connection layer and the first gate-gate electrode layer;
(N) a local wiring layer for a ground line, which has a pattern extending in a second direction, is located in the second layer conductive layer, and is connected to the sources of the first and second drive transistors;
(O) a bit line contact pad layer located in the second conductive layer and connected to the first transfer transistor;
(P) a bit line contact pad layer located in the second conductive layer and connected to the second transfer transistor;
(Q) a ground line having a pattern extending in the second direction, located in a fourth conductive layer that is an upper layer of the third conductive layer, and connected to the local wiring layer for the ground line;
(R) a main word line having a pattern extending in the second direction and located in the fourth conductive layer;
(S) a local wiring layer for bit lines that has a pattern extending in the second direction, is located in the fourth conductive layer, and is connected to the contact pad layer for bit lines;
(T) a / bit line local wiring layer having a pattern extending in the second direction, located in the fourth conductive layer, and connected to the / bit line contact pad layer. ,
The power line is located in the second conductive layer,
The bit line is located in a fifth conductive layer, which is an upper layer of the fourth conductive layer, and is connected to the local wiring layer for the bit line;
The / bit line is located in the fifth conductive layer and is connected to the / bit line local wiring layer,
There are a plurality of the memory cells,
The bit line and / bit line pair includes a plurality of first bit line / bit line pairs and a plurality of second bit line / bit line pairs,
A set of the first bit line and / bit line pair, the second bit line and / bit line pair, and the memory cell of the first bit line / bit line pair; A semiconductor device in which the power line is shared by the memory cells of the second bit line / bit line pair . A semiconductor device comprising a memory cell including a first load transistor, a second load transistor, a first drive transistor, a second drive transistor, a first transfer transistor and a second transfer transistor,
(A) a first active region extending in a first direction and in which the first and second load transistors are formed;
(B) a second active region extending in a first direction and in which the first and second drive transistors and the first and second transfer transistors are formed;
(C) extends in the second direction, is located in the first conductive layer that is an upper layer of the first and second active regions, and intersects the second active region in plan view. A first word line located and including a gate electrode of the first transfer transistor;
(D) extending in the second direction, located in the first conductive layer, and intersecting the second active region in plan view, and of the second transfer transistor A second word line including a gate electrode;
(E) extending in a second direction, located in the first conductive layer, and intersecting the first and second active regions in plan view, and the first A first gate-gate electrode layer located between a word line and the second word line and including a gate electrode of the first load transistor and the first drive transistor;
(F) extends in the second direction, is positioned in the first conductive layer, and is positioned to intersect with the first and second active regions in plan view, and the first A second gate-gate electrode layer positioned between a word line and the second word line and including a gate electrode of the second load transistor and the second drive transistor;
(G) a power supply line extending in the first direction and located on the upper layer of the first conductive layer and connected to the sources of the first and second load transistors;
(H) a bit line extending in the first direction and located in an upper layer of the first conductive layer and connected to the first transfer transistor;
(I) a / bit line that extends in the first direction, is located above the first conductive layer, is connected to the second transfer transistor, and is paired with the bit line; ,
(J) extending in the second direction and located in a second conductive layer that is an upper layer of the first conductive layer, and the drain of the first load transistor and the drain of the first drive transistor A first drain-drain connection layer for connecting,
(K) a second drain-drain extending in the second direction, located in the second layer conductive layer, and connecting the drain of the second load transistor and the drain of the second drive transistor A connection layer;
(L) a first drain − located in a third conductive layer, which is an upper layer of the second conductive layer, and connecting the first drain-drain connection layer and the second gate-gate electrode layer; A gate connection layer;
(M) a second drain-gate connection layer located in the third conductive layer and connecting the second drain-drain connection layer and the first gate-gate electrode layer;
(N) a local wiring layer for a ground line, which has a pattern extending in a second direction, is located in the second layer conductive layer, and is connected to the sources of the first and second drive transistors;
(O) a bit line contact pad layer located in the second conductive layer and connected to the first transfer transistor;
(P) a bit line contact pad layer located in the second conductive layer and connected to the second transfer transistor;
(Q) a ground line having a pattern extending in the second direction, located in a fourth conductive layer that is an upper layer of the third conductive layer, and connected to the local wiring layer for the ground line;
(R) a main word line having a pattern extending in the second direction and located in the fourth conductive layer;
(S) a local wiring layer for bit lines that has a pattern extending in the second direction, is located in the fourth conductive layer, and is connected to the contact pad layer for bit lines;
(T) a / bit line local wiring layer having a pattern extending in the second direction, located in the fourth conductive layer, and connected to the / bit line contact pad layer. ,
The power line is located in the second conductive layer,
The bit line is located in a fifth conductive layer, which is an upper layer of the fourth conductive layer, and is connected to the local wiring layer for the bit line;
The / bit line is located in the fifth conductive layer and is connected to the / bit line local wiring layer,
There are a plurality of the memory cells,
There are a plurality of pairs of the bit line and the / bit line,
The power line of the memory cell of one bit line and / bit line pair is connected to the power line of the memory cell of another bit line / bit line pair via a disconnection circuit A semiconductor device. In claim 1 or 2 ,
In the memory cell,
The semiconductor device, wherein the power supply line and the bit line / bit line pair are arranged in different layers. In any one of Claims 1-3 ,
The semiconductor device, wherein the first and second active regions, the first and second gate-gate electrode layers, and the first and second word lines have a substantially linear pattern. In any one of Claims 1-4 ,
A semiconductor device, wherein the size of the memory cell is 2.5 μm ² or less. Comprising the semiconductor device according to any one of claims 1 to 5 memory system. Comprising the semiconductor device according to any one of claims 1 to 5 electronic device.

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