JP4036085B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device used for a one-chip microcomputer, and more particularly to a ROM (Read Only Memory).
[0002]
[Prior art]
As a conventional technique related to switching of stored contents of a ROM which is one of semiconductor memory devices, there is a technique using an aluminum mask (for example, see Patent Document 1). FIG. 2 shows an example of the mask pattern of the memory cell. NMOS transistors T1 to T5 are formed at the intersections of the N type diffusion layer F and the polysilicons X1 to X5. Contacts C0 to C5 are connected to the sources and drains of the NMOS transistors T1 to T5 and connected to the aluminum patterns A0 to A5. The aluminum pattern A0 is connected to the negative electrode VSS. Each of the NMOS transistors T1 to T5 can store 1 bit of information, and the method depends on whether the source and drain are connected by an aluminum pattern. In this example, NMOS transistors T1, T4, and T5 are not connected by an aluminum pattern, and T2 and T3 are connected by aluminum patterns A12 and A23, respectively.
[0003]
FIG. 3 is a circuit diagram corresponding to FIG. 2. Based on this, a device realized by the mask pattern diagram of FIG. 2 will be described. In FIG. 3, when reading the information stored in the NMOS transistor T1, only the gate signal X1 is set to L level and the other gate signals X2 to X5 are set to H level. If the drain of the NMOS transistor T5, that is, the potential of C5 is precharged to H level by means not shown, the NMOS transistors T2 to T5 are turned on and the NMOS transistor T1 is turned off, so that the potential of C5 is H level. It becomes. Next, when reading the information stored in the NMOS transistor T2, only the gate signal X2 is set to L level, and the other gate signals X1, X3 to X5 are set to H level. At this time, the NMOS transistors T1, T3 to T5 are turned on, and T2 is turned off. However, since the source and drain of the NMOS transistor T2 are connected by the aluminum pattern A12, the state is the same as when the transistor is turned on. Even if the potential is precharged to H level in advance, it becomes L level during reading.
[0004]
FIG. 4 shows an embodiment of a semiconductor memory device (ROM circuit) using the memory cell structure as shown in FIGS. 2 and 3. The source is connected to the positive electrode VDD, and the charge signal S1 is commonly connected to each gate. A charge transistor circuit 10 comprising a plurality of PMOS transistors, a column decoder circuit 20 and a row decoder circuit 30 for selecting a predetermined column and row from a plurality of columns and rows constituting the memory, and a source connected to the negative electrode VSS. It includes a discharge transistor circuit 40 including a plurality of NMOS transistors having a gate connected to a discharge signal S2, a plurality of NMOS transistors serving as memory cells, and a sense amplifier 50. As memory cells, 16 NMOS transistors per row are connected in series, for example, M1 to M16 are connected in series in the first row. Further, all the parasitic capacitances and stray capacitances connected to the input line to the sense amplifier 50 are collectively shown as a capacitance 51. Further, FIG. 5 shows a timing chart of reading in the ROM circuit of FIG.
[0005]
The read operation of the ROM circuit of FIG. 4 will be described by taking M11 data read as an example. When the charging signal S1 input to the charging transistor circuit 10 becomes L level at time T1, the PMOS transistor in the charging circuit 10 is turned on, and the capacitor 51 is connected to the positive electrode VDD and charged to H level. When the precharge of the capacitor 51 ends and at time T2, the signal S1 becomes H level, the PMOS transistor in the charging transistor circuit is turned off, and the address signal ADDRESS is input. The discharge signal S2 input to the discharge transistor circuit 40 is the same signal as the charge signal S1. However, since the discharge transistor circuit 40 is composed of an NMOS transistor, the on / off operation is performed when the charge transistor circuit 10 is turned on. • The off operation is reversed. If the address signal ADDRESS selects M11, only the switch in the column decoder circuit 20 that is connected to the column where M11 exists is turned on. Further, as shown in FIG. 4, the row decoder circuit 30 outputs a signal L only to a row where M11 exists, and outputs a signal H to the other rows, as shown in FIG. These signals are input to the gates of the NMOS transistors constituting M1 to M16, only the transistor M11 is turned off, and the transistors M1 to M10 and M12 to M16 are turned on. At this time, since the transistor in the discharge transistor circuit 40 is turned on by the discharge signal S2, is the charge precharged in the capacitor 51 discharged through the path of the column decoder 20, M1 to M16, the discharge transistor circuit 40? No depends on whether the source and drain of M11 are short-circuited with an aluminum pattern. That is, if the source and drain of M11 are not short-circuited with aluminum, the charge of the capacitor 51 is not discharged. Therefore, the sense amplifier 50 receives this and outputs H as information stored in M11, and is short-circuited with aluminum. For example, the charge of the capacitor 51 is discharged, and the sense amplifier 50 outputs L as information stored in M11. In the example of FIG. 4, since the source and drain of M11 are short-circuited with aluminum, the sense amplifier 50 outputs L.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-307653
[Problems to be solved by the invention]
In the ROM circuit of FIG. 4, when reading data of M11, a waiting time until the data is stabilized (= delay Td in FIG. 5) is required. When the charge precharged in the capacitor 51 is not discharged, there is no change in the input / output of the sense amplifier 50. Therefore, what defines the waiting time is the discharge time when discharging the charge precharged in the capacitor 51. The discharge time is defined by the capacitance value C of the capacitor 51 and the on-resistance of the entire column to which the element to be read belongs. The on-resistance of the entire column is the sum of the on-resistance of the switch in the column decoder circuit 20, the respective resistances of M 1 to M 16 and the on-resistance of the PMOS transistor in the row decoder circuit 30. Regarding the resistance of the whole M1 to M16, the maximum on-resistance is obtained when the source / drain is short-circuited with an aluminum pattern only in the transistor to be read and all other transistors are not short-circuited. In this case, the maximum on-resistance RMAX is expressed by the following equation.
[0008]
[Expression 1]
RMAX = 15Ron + Rm (1)
Here, Ron is the on-resistance of the NMOS transistors constituting M1 to M16, Rm is the resistance value of the aluminum pattern that short-circuits the source and drain of the transistor, and Ron is much larger than Rm, so if Rm is ignored ( The formula 1) becomes the following formula.
[0009]
[Expression 2]
RMAX = 15Ron (2)
The waiting time or delay Td is defined by this maximum resistance value, and is regulated by the number of transistors in the column and its on-resistance as shown in the formula (1) or (2), and is not suitable for high-speed reading. It is a thing. Further, if the number of memory cells in the column is increased, the on-resistance of the entire column increases accordingly, and there is a problem that access time increases when the storage capacity is increased.
[0010]
Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device that is suitable for high-speed reading and has a smaller increase in accelerator time than conventional devices even when the storage capacity is increased. It is in.
[0011]
[Means for Solving the Problems]
Accordingly, in order to solve the above problem, the invention according to claim 1 is directed to a plurality of memory columns in which a plurality of memory cells storing 1-bit data are connected in series depending on the presence or absence of a short circuit between the source and drain of a MOS transistor. And a semiconductor memory device having a row decoder circuit that decodes an address input from the outside and outputs a selection signal to each gate of the plurality of MOS transistors in the memory column. Are divided into a plurality of groups of memory cells, and when the selection signal from the decoder circuit turns on all the MOS transistors in the group for each group, it is detected and the group is detected. Bypass means for electrically connecting the both ends of each are provided.
[0012]
The invention according to claim 2 is characterized in that the presence or absence of a short circuit between the source and drain of the MOS transistor is realized by the presence or absence of an aluminum pattern connecting the source and drain.
According to a third aspect of the present invention, the MOS transistor is an NMOS transistor, and the bypass means inputs the logical product of the selection signals from all the row decoder circuits input to the group and inputs the gate thereof. The drains are NMOS transistors respectively connected to both ends of the group.
[0013]
According to a fourth aspect of the present invention, the output data of the semiconductor device is determined depending on whether or not the precharged charge is discharged using a memory column including the memory cell corresponding to the address as a discharge path. The output from the previous row decoder circuit turns off only the MOS transistors of the memory cell corresponding to the address in the memory column, and turns on all other transistors in the memory column. To do.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0015]
【Example】
FIG. 1 is a circuit diagram showing an embodiment of the present invention. The charge transistor circuit 10, the column decoder circuit 20, the row decoder circuit 30, the discharge transistor circuit 40, the sense amplifier 50, the capacitor 51, the memory cells M1 to M16, and the signals S1, S2, and ADDRESS are the same as those described in FIG. is there. The circuit shown in FIG. 1 is different from that shown in FIG. 4 in that 4-input AND gates 60, 61, 62, 63 and bypass circuits 70, 71, 72, 73 are added. In the ROM circuit of FIG. 1, the memory cells are grouped every four rows, and the AND gate 60 receives four selection signals output from the row decoder circuit and input to the first group. Similarly, the AND gates 61, 62, 63 receive four selection signals input to the second, third, and fourth groups, respectively. The bypass circuit 70 is composed of a plurality of NMOS transistors each connected to both ends of each column of memory cells in the first group and the source / drain, and the gates of these NMOS transistors are connected to the output of the AND gate 60. It is connected. Similarly, each of the bypass circuits 61, 62, 63 is composed of a plurality of NMOS transistors in which both ends of each column of memory cells in the second, third, and fourth group groups are connected to the source / drain. The gates of the NMOS transistors are connected to the outputs of the AND gates 61, 62, 63 for each bypass circuit.
[0016]
The read operation of the ROM circuit of FIG. 1 will be described by taking M11 read as an example as in FIG. The timing chart is common to FIG. In order to consider the maximum on-resistance, the source and drain of only M11 to be read are short-circuited with an aluminum pattern, and the sources and drains of the other transistors M1 to M10 and M12 to 16 are all short-circuited. Make it not exist. The operation up to time T2 is the same as that in FIG. When the selection signal is output from the row decoder circuit 30 to each row of the memory cells after the time T2, the selection signal becomes L only for the row where M11 to be read exists, and becomes H for the other rows. Therefore, in response to this, the outputs of the AND gates 60, 61, 63 become H, and the output of the AND gate 62 becomes L. Next, all the NMOS transistors in the bypass circuits 70, 71, 73 are turned on by the output signals of the AND gates 60 to 63, and conversely, all the NMOS transistors in the bypass circuit 72 are turned off. When the NMOS transistor in the bypass transistor circuit is turned on, both ends of each column of memory cells in the corresponding group are electrically connected, so that the total on-resistance is reduced. Specifically, taking M1 to M4 as an example, when all the gate inputs of the NMOS transistors M1 to M4 are H, the output of the AND gate 60 becomes H, and the NMOS transistor T20 in the bypass circuit 70 is turned on. Thereby, the drain of the NMOS transistor of M1 and the source of the NMOS transistor of M4 are connected by T20. When there is no T20, the total on-resistance R4 of M1 to M4 is 4Ron, and if the on-resistance of T20 is also Ron, the total on-resistance R4 when T20 is present is a parallel resistance of 4Ron and Ron, and thus .
[0017]
[Equation 3]
R4 = (4Ron × Ron) / (4Ron + Ron) = 0.8 Ron
In FIG. 1, since only the selection signal for M10 is L and all others are H, the groups M5 to M8 and the groups M13 to M16 are similarly short-circuited by the bypass circuit as described above. The total resistance R16 of M1 to M16 is as follows.
[0018]
[Expression 4]
R16 = 3 × 0.8Ron + 3Ron = 5.4Ron
Here, M11 is ignored because the source and drain of the NMOS transistor are short-circuited with an aluminum pattern and the resistance Rm is very small. On the other hand, in the prior art in which no bypass circuit exists, R16 is RMAX = 15 Ron as shown by the equation (2). As described above, the present invention can realize a small on-resistance, that is, a small delay Td as compared with the prior art.
[0019]
Further, consider a case where the number of memory cells per column, that is, the number of NMOS transistors is doubled. When a bypass circuit exists, the total on-resistance R32 is calculated as follows by the same calculation as above.
[0020]
[Equation 5]
R32 = 7 × 0.8Ron + 3Ron = 8.6Ron
This is because the number of memory cells is half that of 16
[0021]
[Formula 6]
8.6Ron / 5.4Ron = 1.6
Increase rate. On the other hand, when there is no bypass circuit, R32 = 31Ron, and the increase rate in this case is
[Expression 7]
31Ron / 15Ron = 2.1
It becomes. That is, according to the present invention, not only the total on-resistance can be reduced as compared with the prior art, but also the increase rate of the total on-resistance with respect to the increase in the number of memory cells can be reduced.
[0023]
【The invention's effect】
As described above, according to the present invention, memory cells in a column are divided into a plurality of groups, and when the output of the row decoder circuit is a signal that turns on all the memory cells in the group, it is detected. By short-circuiting both ends of a plurality of memory cell columns connected in series in the group, a semiconductor memory device having a small total on-resistance and a small rate of increase in the total on-resistance even when the number of memory cells is increased. Can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to the present invention.
FIG. 2 is an example of a mask pattern of a memory cell according to the prior art.
FIG. 3 is a circuit diagram corresponding to the mask pattern of FIG. 2;
4 is a circuit diagram of a semiconductor memory device to which the memory cell of FIGS. 2 and 3 is applied. FIG.
5 is an operation timing chart of the circuits of FIGS. 1 and 5. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Charge transistor circuit 20 Column decoder circuit 30 Row decoder circuit 40 Discharge transistor circuit 50 Sense amplifier 51 Capacity | capacitance 60-63 AND gate 70-73 Bypass circuit M1-M16 Memory cell T20 NMOS transistor

Claims (4)

A plurality of memory cells in which a plurality of memory cells storing 1-bit data are connected in series according to the presence or absence of a short circuit between the source and drain of the MOS transistor, and a plurality of memory cells in the memory column by decoding addresses inputted from the outside In the semiconductor memory device having a row decoder circuit that outputs a selection signal to each gate of the MOS transistor, the memory column is divided into a plurality of groups each including a plurality of continuous memory cells, and the group is divided into the groups. A semiconductor device comprising: bypass means for detecting when the selection signal from the decoder circuit turns on all the memory transistors in the group and electrically connecting both ends of the group Storage device. 2. The semiconductor memory device according to claim 1, wherein the presence or absence of a short circuit between the source and drain of the MOS transistor is realized by the presence or absence of an aluminum pattern connecting the source and drain. The MOS transistor is an NMOS transistor, and the bypass means inputs a logical product of selection signals from all the row decoder circuits input to the group, and has a source and a drain at both ends of the group, respectively. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a connected NMOS transistor. The semiconductor device determines its output data based on whether or not the precharged charge is discharged using a memory column including the memory cell corresponding to the address as a discharge path, and outputs from the previous row decoder circuit 4. The method according to any one of claims 1 to 3, wherein only the MOS transistor of the memory cell corresponding to the address in the memory column is turned off and all the other transistors in the memory column are turned on. A semiconductor memory device according to claim 1.

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