JP4872299B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device used for a one-chip microcomputer, and more particularly to a ROM (Read Only Memory).

As a conventional technique related to switching of stored contents of a ROM which is one of semiconductor memory devices, there is a technique using an aluminum (aluminum) mask (for example, see Patent Document 1). FIG. 2 shows an example of the mask pattern of the memory cell. NMOS transistors T1 to T5 are formed at the intersections of the N type diffusion layer F and the polysilicons X1 to X5. Contacts C0 to C5 are connected to the sources and drains of the NMOS transistors T1 to T5 and connected to aluminum (aluminum) patterns A0 to A5. The aluminum pattern A0 is connected to the negative electrode VSS. Each of the NMOS transistors T1 to T5 can store 1 bit of information, and the method depends on whether the source and drain are connected by an aluminum pattern. In this example, NMOS transistors T1, T4, and T5 are not connected by an aluminum pattern, and T2 and T3 are connected by aluminum patterns A12 and A23, respectively.
FIG. 3 is a circuit diagram corresponding to FIG. 2. Based on this, a device realized by the mask pattern diagram of FIG. 2 will be described. In FIG. 3, when reading the information stored in the NMOS transistor T1, only the gate signal X1 ′ for the gate X1 is set to L level, and the gate signals X2 ′ to X5 ′ for the other gates X2 to X5 are set to H level. If the drain of the NMOS transistor T5, that is, the potential of C5 is precharged to H level by means not shown, the NMOS transistors T2 to T5 are turned on and the NMOS transistor T1 is turned off, so that the potential of C5 is H level. It becomes. Next, when reading the information stored in the NMOS transistor T2, only the gate signal X2 ′ is set to L level, and the other gate signals X1 ′ and X3 ′ to X5 ′ are set to H level. At this time, the NMOS transistors T1, T3 to T5 are turned on, and T2 is turned off. However, since the source and drain of the NMOS transistor T2 are connected by the aluminum pattern A12, the state is the same as when the transistor is turned on. Even if the potential is precharged to H level in advance, it becomes L level during reading.
FIG. 4 shows an embodiment of a semiconductor memory device (ROM circuit) using the memory cell structure as shown in FIGS. 2 and 3. The source is connected to the positive electrode VDD, and the charge signal S1 is commonly connected to each gate. A charge transistor circuit 10 comprising a plurality of PMOS transistors, a column decoder circuit 20 and a row decoder circuit 30 for selecting a predetermined column and row from a plurality of columns and rows constituting the memory, and a source connected to the negative electrode VSS. It includes a discharge transistor circuit 40 including a plurality of NMOS transistors having a gate connected to a discharge signal S2, a plurality of NMOS transistors serving as memory cells, and a sense amplifier 50. As memory cells, 16 NMOS transistors per row are connected in series, for example, M1 to M16 are connected in series in the first row. For convenience, the transistors constituting the memory cells M1 to M16 are also referred to as M1 to M16. Further, all the parasitic capacitances and stray capacitances connected to the input line to the sense amplifier 50 are collectively shown as a capacitance 51. Further, FIG. 5 shows a timing chart of reading in the ROM circuit of FIG.
The read operation of the ROM circuit of FIG. When the charging signal S1 input to the charging transistor circuit 10 becomes L level at time T1, the PMOS transistor in the charging circuit 10 is turned on, and the capacitor 51 is connected to the positive electrode VDD and charged to H level. When the precharge of the capacitor 51 ends and at time T2, the signal S1 becomes H level, the PMOS transistor in the charging transistor circuit is turned off, and the address signal ADDRESS is input. The discharge signal S2 input to the discharge transistor circuit 40 is the same signal as the charge signal S1. However, since the discharge transistor circuit 40 is composed of an NMOS transistor, the on / off operation is performed when the charge transistor circuit 10 is turned on. • The off operation is reversed. If the address signal ADDRESS selects M11, only the switch in the column decoder circuit 20 that is connected to the column where M11 exists is turned on. Further, as shown in FIG. 4, the row decoder circuit 30 outputs a signal L only to a row where M11 exists, and outputs a signal H to the other rows, as shown in FIG. These signals are input to the gates of the NMOS transistors constituting the memory cells M1 to M16, only the transistor M11 is turned off, and the transistors M1 to M10 and M12 to M16 are turned on. At this time, since the transistor in the discharge transistor circuit 40 is turned on by the discharge signal S2, whether the charge precharged in the capacitor 51 is discharged through the path of the column decoder 20, M1 to M16, the discharge transistor circuit 40. No depends on whether the source and drain of M11 are short-circuited with an aluminum pattern. That is, if the source and drain of M11 are not short-circuited with aluminum, the charge of the capacitor 51 is not discharged. Therefore, the sense amplifier 50 receives this and outputs H as information stored in M11, and is short-circuited with aluminum. For example, the charge of the capacitor 51 is discharged, and the sense amplifier 50 outputs L as information stored in M11. In the example of FIG. 4, since the source and drain of M11 are short-circuited with aluminum, the sense amplifier 50 outputs L.

  The ROM circuit of FIG. 4 requires a waiting time (= delay Td in FIG. 5) until the data is stabilized when reading data of M11. When the charge precharged in the capacitor 51 is not discharged, there is no change in the input / output of the sense amplifier 50. Therefore, what defines the waiting time is the discharge time when discharging the charge precharged in the capacitor 51. The discharge time is defined by the capacitance value C of the capacitor 51 and the on-resistance of the entire column to which the element to be read belongs. The on-resistance of the entire column is the sum of the on-resistance of the switch in the column decoder circuit 20, the respective resistances of M 1 to M 16 and the on-resistance of the PMOS transistor in the row decoder circuit 30. Regarding the resistance of the whole M1 to M16, the maximum on-resistance is obtained when the source / drain is short-circuited with an aluminum pattern only in the transistor to be read and all other transistors are not short-circuited. In this case, the maximum on-resistance RMAX is expressed by the following equation.

(Equation 1)
RMAX = 15Ron + Rm (1)
Here, Ron is the on-resistance of the NMOS transistors constituting M1 to M16, Rm is the resistance value of the aluminum pattern that short-circuits the source and drain of the transistor, and Ron is much larger than Rm, so if Rm is ignored ( The formula 1) becomes the following formula.

(Equation 2)
RMAX = 15Ron (2)
The waiting time or delay Td is defined by this maximum on-resistance value, and is regulated by the number of transistors in the column and the on-resistance as shown in the equation (1) or (2), so it is suitable for high-speed reading. It is not something. Further, if the number of memory cells in the column is increased, the on-resistance of the entire column increases accordingly, and there is a problem that access time increases when the storage capacity is increased.
In order to cope with this problem, the present applicant has proposed a semiconductor memory device capable of reducing the total on-resistance RMAX that defines the delay Td in Patent Document 2. The contents will be described below.

  FIG. 6 is a circuit diagram showing an embodiment of a semiconductor memory device disclosed in Patent Document 2. In FIG. The charge transistor circuit 10, the column decoder circuit 20, the row decoder circuit 30, the discharge transistor circuit 40, the sense amplifier 50, the capacitor 51, the memory cells M1 to M16, and the signals S1, S2, and ADDRESS are the same as those described in FIG. is there. The circuit shown in FIG. 6 is different from that shown in FIG. 4 in that 4-input AND gates 60, 61, 62, and 63 and bypass circuits 70, 71, 72, and 73 are added. In the ROM circuit of FIG. 6, the memory cells are grouped every four rows, and the AND gate 60 receives four selection signals output from the row decoder circuit and input to the first group. Similarly, the AND gates 61, 62, 63 receive four selection signals input to the second, third, and fourth groups, respectively. The bypass circuit 70 is composed of a plurality of NMOS transistors each connected to both ends of each column of memory cells in the first group and the source / drain, and the gates of these NMOS transistors are connected to the output of the AND gate 60. It is connected. Similarly, each of the bypass circuits 61, 62, and 63 is composed of a plurality of NMOS transistors in which both ends of each column of memory cells in the second, third, and fourth groups are connected to the source / drain. The gates of the transistors are connected to the outputs of AND gates 61, 62, 63 for each bypass circuit.

  The read operation of the ROM circuit of FIG. 6 will be described by taking M11 read as an example as in FIG. The timing chart is common to FIG. In order to consider the maximum on-resistance, the source and drain of only M11 to be read are short-circuited with an aluminum pattern, and the sources and drains of the other transistors M1 to M10 and M12 to 16 are all short-circuited. Make it not exist. The operation up to time T2 is the same as that in FIG. When the selection signal is output from the row decoder circuit 30 to each row of the memory cells after the time T2, the selection signal becomes L only for the row where M11 to be read exists, and becomes H for the other rows. Therefore, in response to this, the outputs of the AND gates 60, 61, 63 become H, and the output of the AND gate 62 becomes L. Next, all the NMOS transistors in the bypass circuits 70, 71, 73 are turned on by the output signals of the AND gates 60 to 63, and conversely, all the NMOS transistors in the bypass circuit 72 are turned off. When the NMOS transistor in the bypass transistor circuit is turned on, both ends of each column of memory cells in the corresponding group are electrically connected, so that the total on-resistance is reduced. Specifically, taking M1 to M4 as an example, when all the gate inputs of the NMOS transistors M1 to M4 are H, the output of the AND gate 60 becomes H, and the NMOS transistor T20 in the bypass circuit 70 is turned on. Thereby, the drain of the NMOS transistor of M1 and the source of the NMOS transistor of M4 are connected by T20. When there is no T20, the total on-resistance R4 of M1 to M4 is 4Ron, and if the on-resistance of T20 is also Ron, the total on-resistance R4 when T20 is present is a parallel resistance of 4Ron and Ron, and thus .

(Equation 3)
R4 = (4Ron × Ron) / (4Ron + Ron) = 0.8 Ron (3)
In FIG. 6, since only the selection signal for M10 is L and all other signals are H, the groups M5 to M8 and the groups M13 to M16 are similarly short-circuited by the bypass circuit as described above. The total resistance R16 of M1 to M16 is as follows.

(Equation 4)
R16 = 3 × 0.8Ron + 3Ron = 5.4Ron (4)
Here, M11 is ignored because the source and drain of the NMOS transistor are short-circuited with an aluminum pattern and the resistance Rm is very small. On the other hand, in the prior art in which no bypass circuit exists, R16 is RMAX = 15 Ron as shown by the equation (2).
Further, consider a case where the number of memory cells per column, that is, the number of NMOS transistors is doubled. When a bypass circuit exists, the total on-resistance R32 is calculated as follows by the same calculation as above.

(Equation 5)
R32 = 7 × 0.8Ron + 3Ron = 8.6Ron
This is because the number of memory cells is half that of 16

(Equation 6)
8.6Ron / 5.4Ron = 1.6
Increase rate. On the other hand, when there is no bypass circuit, R32 = 31Ron, and the increase rate in this case is

(Expression 7) 31Ron / 15Ron = 2.1. That is, the semiconductor memory device shown in FIG. 5 can be made smaller than that of FIG. 6, the total on-resistance and increase rate thereof.
JP 11-307653 A JP 2004-148567 A [Disclosure of the Invention] [Problems to be Solved by the Invention]

The semiconductor memory device shown in FIG. 6 re-encodes selection signals (gate drive signals of the transistors M1 to M16) for the memory cells M1 to M16 once generated by decoding the address signal ADDRESS by using AND gates 60 to 63 to convert the transistors. It is configured to generate a gate drive signal of T20 to T23. Considering the reliability and operation speed (or delay time) of the semiconductor memory device, it is desirable that the gate drive signal generation circuit be as simple as possible. From this point of view, the semiconductor memory device shown in FIG. 5 still has room for improvement. There is something. Further, it is desirable to further reduce the total on-resistance.
Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device capable of further reducing the total on-resistance with a simpler circuit configuration.
[Means for solving problems]

In order to solve the above problem, the invention according to claim 1 is directed to a plurality of memory columns in which a plurality of memory cells storing 1-bit data are connected in series according to the presence or absence of a short circuit between the source and drain of a MOS transistor. In a semiconductor memory device having a row decoder circuit that decodes an n-bit (n is an integer) address signal input from the outside and outputs a selection signal to each gate of the plurality of MOS transistors in the memory column The plurality of MOS transistors in the memory column are arranged in the memory column in an order such that addresses for selecting the respective MOS transistors are continuous, and the address signal input to the row decoder circuit the relative 1 to the most significant bit to m bits (m is an integer smaller than n), for each bit And equal value from the bits of his own address to the most significant bits along with the address of the lower than the bit to set a plurality of groups comprising a plurality of memory cells continuous in from 0 to the maximum value, the in each group When the bit of the address signal used for grouping is not to select the group, a bypass means for electrically connecting both ends of the group is provided.

The invention according to claim 2 is characterized in that, in the invention according to claim 1, the presence or absence of a short circuit between the source and drain of the MOS transistor is realized by the presence or absence of a wiring pattern connecting the source and drain.
According to a third aspect of the present invention, in the first or second aspect of the invention, the semiconductor device discharges a memory column including a memory cell in which the address signal selects a precharged charge in advance as a discharge path. Whether or not the output data is determined, and the output from the row decoder circuit turns off only the MOS transistors of the memory cells corresponding to the address signal in the memory column, and all the other transistors in the memory column The transistor is turned on.

  In the semiconductor memory device according to the present invention, the bypass means for electrically connecting the both ends of the group of a plurality of memory cells is directly controlled by a predetermined bit of the address signal, so that it is easy to maintain reliability with a simple structure. In addition, a semiconductor memory device that can improve the operation speed can be provided. Further, the total on-resistance can be further reduced by using a plurality of bits of the address signal.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. The same parts as those in FIGS. 4 and 6 are denoted by the same reference numerals, and detailed description thereof is omitted. The following description will be made by taking the leftmost memory cell column of the semiconductor memory device shown in FIG. 1 as an example, but the same applies to the second and subsequent columns.
The semiconductor memory device shown in FIG. 1 has to those arranged bypass transistor M17~M22 instead of the bypass transistor T20~T23 of the semiconductor memory device shown in FIG. The bypass transistors M17 to M22 are NMOS transistors, and are turned on (conducted) when the potential of their gate terminals is H. The connection of the source / drain terminals of the bypass transistors M17, M18, M20, and M22 is the same as that of the bypass transistors T20 to T23, but the connection to the gate terminal is different, and therefore, different signs are given. The source / drain terminal of the bypass transistor M19 is connected to both ends of the memory cell group consisting of the memory cells M1 to M8, respectively, and the source / drain terminal of the bypass transistor M22 is connected to both ends of the memory cell group consisting of the memory cells M9 to M16. Each is connected. The gate terminals of the bypass transistors M17 to M22 have an address signal adrs [2], an inverted signal of the address signal adrs [2], an address signal adrs [3], an address signal adrs [2], and an address signal adrs [2]. And an inverted signal of the address signal adrs [3] are input. Here, adrs [7] to adrs [0] are 8-bit address signals constituting the address bus ADDRESS, where adrs [7] is the most significant bit and adrs [0] is the least significant bit. Further, the notation in FIG. 1 , adrs [X: Y] means an (XY) bit address signal from adrs [X] to adrs [Y].

INV1 and INV2 in FIG. 1 are inverters for obtaining inverted signals of the address signals adrs [2] and adrs [3], respectively.
Next, the operation of the present embodiment, particularly the operation of the bypass transistor transistors M17 to M22, and the total on-resistance obtained from the present embodiment will be described.
Among the address signals, the upper 4 bits adrs [7: 4] are input to the column decoder 20, and the column decoder 20 selects a column from which data is read based on the address signal adrs [7: 4]. Hereinafter, a case where the column decoder 20 selects the leftmost column by the address signal adrs [7: 4] will be described.
Of the address bus, the lower 4 bits adrs [3: 0] are input to the row decoder 30, and the row decoder 30 selects a row from which data is read based on the address signal adrs [3: 0]. In addition, the address signal adrs [3] and the address signal adrs [2] are used for on / off control of the transistors M17 to M21. The transistors M17, M18, M20, and M21 divide the memory cells M1 to M16 into four groups A to D corresponding to the address signal adrs [2]. That is, the own address data corresponding to the address signal adrs [2] is equal (one that becomes active when the address signal adrs [2] is H, or one that becomes active when the address signal adrs [2] is L), and the addresses are continuous. The memory cells formed in each group. Specifically, the address signal adrs [3: 0] = 0000 to 0011 having its own address is group A, the address having 0100 to 0111 is its own address, group B, and 1000 to 1011 is its own address. Those having addresses constitute group C, and those having 1100 to 1111 as their own addresses constitute group D. Similarly, the address signal adrs [3] includes memory cells M1 to M16 in two groups, that is, address signals adrs [3: 0] = 0000 to 0111 as its own addresses (group A + group B) and 1000 to 1111. Are grouped into two groups (group C + group D).

In each group, both ends of the group are short-circuited by the transistors M17 to M21 depending on whether the corresponding address signal is H or L. For example, when the address signal adrs [2] is H, the transistors M17 and M20 are turned on and both ends of the groups A and C are short-circuited. Further, when the address signal adrs [2] is L, the transistors M18 and M21 are turned on and both ends of the groups B and D are short-circuited.
This corresponds to the following. That is, the memory cell groups A and B that become active when the address signal adrs [3] is L do not need to read data when the address signal adrs [3] is H. Therefore, the address signal adrs [3] is connected to the gate terminal of the bypass transistor M19. When the address signal adrs [3] is H, the bypass transistor M19 is turned on, and both ends of the group A + group B are short-circuited to bypass. As a result, the overall on-resistance of the portion of group A + group B that is not related to the read operation is reduced. Similarly, the gate of the bypass transistor M22 for group C + Group D inputs an inverted signal of the address signal adrs [3], address signal adrs [3] is to turn on the bypass transistor M22 when the L, Group C + Group D Bypass by shorting both ends. As a result, the overall on-resistance of the group C + group D, which is not related to the read operation, is reduced.

The memory cells in group A are active when the address signal adrs [2] is L, and are not read when the address signal is H. Therefore, the address signal adrs [2] is connected to the gate terminal of the bypass transistor M17 of the group A, and when the address signal adrs [2] is H, the bypass transistor M17 is turned on, and the group A that is not related to the read operation. Bypass both ends. As a result, the overall on-resistance of group A is reduced. Similarly, an address signal adrs [2] is connected to the gate terminal of the bypass transistor M20, and an inverted signal of the address signal adrs [2] is connected to the gate terminals of the bypass transistors M18 and M21.
Next, how much the total on-resistance decreases due to the effects of the bypass transistors M17 to M22 will be considered. As an example, consider a case where 1001 is input as the address signal adrs [3: 0] and the row of the memory cell (transistor) M10 is selected. The transistors M17 to M22 are the same size as the transistors M1 to M16, and the on-resistance is the same Ron as the transistors M17 to M22.

When the address signal adrs [3: 0] = 1001, the bypass transistors M18, M19, and M21 are turned on, and M17, M20, and M22 are turned off. In this case, the total on resistance of the group A is the resistance 4Ron in which the four on resistances Ron of the transistors M1 to M4 are connected in series. The total on-resistance of group B is a resistance 4Ron in which the four on-resistances Ron of the transistors M5 to M8 are connected in series and an on-resistance Ron of the transistor M18 are connected in parallel. It becomes. The total on-resistance _{RA + B} of group A + group B is 4.8Ron in which the total on-resistance 4Ron of group A and 0.8Ron of group B are connected in series, and the on-resistance Ron of transistor M19 is connected in parallel. Therefore, the following equation is obtained.

(Equation 8)
R _{A + B} = (4.8 Ron × Ron) / (4.8 Ron + Ron) = 0.83 Ron (5)
In addition, since the maximum on-resistance is considered when only the transistor M10 to be read is short-circuited between the source and drain terminals with an aluminum pattern, the total on-resistance of the group C is 3Ron. The total on-resistance of group D is 0.8 Ron as in group B. The total on-resistance _{RC + D} of the group C + group _D is expressed by the following equation.

(Equation 9)
R _{C + D} = 3Ron + 0.8Ron = 3.8Ron (6)
From the equations (5) and (6), the total on-resistance R _{A + B + C + D} of the memory cells M1 to M16 is expressed by the following equation.

(Equation 10)
_{RA + B + C + D} = _{RA + B} + _{RC + D} = 4.63 Ron (7)
This is smaller than the maximum on-resistance RMAX = 15 Ron when there is no bypass transistor described in the background art and the total on-resistance R16 = 5.4 Ron according to the invention disclosed in Patent Document 2 (Equation (4)). It is a value.
The bypass transistors are two transistors M19 and M22 whose on / off is controlled by the address signal adrs [3] and transistors M17, M18, M20 and M21 whose on / off is controlled by the address signal adrs [2]. A set is provided, but is not limited to two sets. Depending on the number of memory cells (transistors) constituting the column, the number of sets (in other words, the number of address signals for performing on / off control of bypass transistors) may be increased or decreased.

  Next, consider a case where the number of transistors constituting the column is 32. In this case, a 5-bit address signal is input to the row decoder 30. The total on-resistance in the case of performing the on / off control of the bypass transistor by grouping by the upper 2 bits among these 5 bits is 8.79 Ron by the same calculation as described above, though details are omitted. Further, when the on / off control of the bypass transistor is performed by grouping by the upper 3 bits of the 5-bit address signal input to the row decoder 30, the total on-resistance is 5.48 Ron. Table 1 shows a summary of the on-resistance increase rate when the total on-resistance and the memory cells are changed from 16 to 32.

表１から明らかなように、列を構成するトランジスタ数に応じて適宜バイパストランジスタのセット数を調整することにより、従来の半導体記憶装置より容易に総合オン抵抗およびその増加率を下げることができる。

As can be seen from Table 1, by adjusting the number of bypass transistors as appropriate according to the number of transistors constituting the column, the total on-resistance and the rate of increase thereof can be reduced more easily than conventional semiconductor memory devices.

1 is a circuit diagram showing a configuration of a semiconductor memory device according to the present invention. It is an example of the mask pattern of the memory cell by a prior art. FIG. 3 is a circuit diagram corresponding to the mask pattern of FIG. 2. FIG. 4 is a circuit diagram of a semiconductor memory device to which the memory cell of FIGS. 2 and 3 is applied. 6 is an operation timing chart of the circuit of FIG. 10 is a circuit diagram showing an embodiment of a semiconductor memory device disclosed in Patent Document 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Charge transistor circuit 20 Column decoder circuit 30 Row decoder circuit 40 Discharge transistor circuit 50 Sense amplifier 51 Capacity | capacitance 60-63 AND gate 70-73 Bypass circuit INV1, INV2 Inverter M1-M16 Memory cell M17-M21 Bypass transistor

Claims (3)

A plurality of memory columns in which a plurality of memory cells storing 1-bit data are connected in series according to the presence or absence of a short circuit between the source and drain of the MOS transistor, and an n-bit (n is an integer) address signal input from the outside. In a semiconductor memory device having a row decoder circuit which decodes and outputs a selection signal to each gate of the plurality of MOS transistors in the memory column,
The plurality of MOS transistors in the memory column are arranged in the memory column in an order such that addresses for selecting each MOS transistor are continuous,
For the most significant 1 to m bits (m is an integer smaller than n) of the address signal input to the row decoder circuit, the value from the bit to the most significant bit of its own address is determined for each bit. A plurality of groups consisting of a plurality of continuous memory cells having the same and lower addresses from 0 to the maximum value are set, and the bits of the address signal used for grouping the group in each group A semiconductor memory device comprising a bypass means for electrically connecting both ends of a group when a group is not selected. 2. The semiconductor memory device according to claim 1, wherein the presence or absence of a short circuit between the source and drain of the MOS transistor is realized by the presence or absence of a wiring pattern connecting the source and drain. The semiconductor device determines the output data depending on whether or not the precharged charge is discharged using a memory column including a memory cell selected by the address signal as a discharge path, and an output from the row decoder circuit 3. The method according to claim 1, wherein only a MOS transistor of a memory cell corresponding to the address signal in the memory column is turned off and all other transistors in the memory column are turned on. The semiconductor memory device described.

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