JP4055901B2 - Phase-locked loop circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase locked loop circuit.
[0002]
[Prior art]
In receivers and the like, a phase-locked loop (PLL) circuit including a DDS (Direct Digital Synthesizer) is known (for example, see Patent Document 1). The DDS includes a memory for storing waveform data, reads waveform data from the memory, and directly synthesizes signals based on the read waveform data. For this reason, the phase locked loop circuit provided with the DDS can output a signal having a desired frequency accurately and quickly.
[0003]
Such DDS sequentially accesses storage locations in the memory based on the frequency of the oscillation signal output from the phase locked loop circuit. Since the waveform data stored in the memory is, for example, for one cycle, the DDS repeatedly accesses the memory and reads the waveform data.
[0004]
Assuming one cycle of access to the memory as one cycle, the frequency Fdds of the signal output from the DDS is expressed by the following equation (1).
[Expression 1]
Fdds = (K / 2 ^N ) × Fout
However, K: DDS setting number (memory read address pitch)
N: number of bits of memory address Fout: output frequency of output signal of PLL circuit (voltage controlled oscillator)
As can be seen from this equation, the output frequency Fdds of the DDS is a frequency divided by 2 ^N / K of the output frequency Fout of the phase locked loop. Here, the DDS setting number K can be set to a divisor other than the divisor of the memory address number ^2N , so that the division value can be set to a value other than an integer, and as a result, the output of the phase locked loop It becomes possible to set the frequency at a frequency pitch equal to or lower than the reference frequency.
[0006]
[Patent Document 1]
Japanese Patent Publication No. 03-07778 (page 2-3, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, in such a phase-locked loop having a DDS, spurious due to the DDS may occur at its output.
That is, when the waveform data is read by repeatedly accessing all addresses (= 2 ^N ) of the memory storing the waveform data at the K pitch which is the DDS setting number, if K is not a divisor of 2 ^N , the first access is performed. in can not access the 2 ^N-th address, it will be access for the first time 2 ^N-th address in what round of the access. That is, this cyclic operation is performed periodically. As a result, the output frequency Fdds of the DDS is in a state where FM modulation is applied by this cyclic frequency, and spurious other than the target frequency is generated.
[0008]
If this spurious frequency is not within the band of the phase locked loop (within the pass frequency band of the loop filter), the spurious is removed by the loop filter, but the frequency close to the output frequency Fdds of the DDS, that is, the phase locked loop. If it is within the band, this spurious cannot be removed by the loop filter, and it will also appear at the output of the phase locked loop, and the signal purity of the output signal will be reduced.
[0009]
The present invention has been made in view of such conventional problems, and an object thereof is to provide a phase-locked loop circuit capable of improving signal purity.
[0010]
[Means for Solving the Problems]
In order to achieve this object, a phase locked loop circuit according to an aspect of the present invention provides:
A reference signal output circuit for outputting a reference signal having a reference frequency;
A phase comparator that compares the phase of the reference signal with the phase of the predetermined signal and outputs a phase difference signal corresponding to the phase difference between the two signals;
A loop filter for filtering the output signal of the phase comparator;
An oscillator that outputs an oscillation signal having a frequency according to the phase difference signal that has passed through the loop filter;
A storage unit for storing waveform data;
A waveform data reading unit that reads the waveform data from the storage unit based on the output frequency of the oscillation signal;
A modulator that ΔΣ modulates the waveform data and outputs quantized data;
A digital-analog converter that converts the quantized data from the modulator into an analog signal and supplies the analog signal as the predetermined signal;
Equipped with a,
The storage unit stores waveform data at a plurality of addresses,
The waveform data reading unit
A read pitch setting unit for setting a pitch of a read address of the storage unit;
Means for generating a read address of the storage unit by accumulating the read pitch set by the read pitch setting unit;
Means for reading the waveform data by accessing the storage unit at the generated address;
With
Including the case where the readout pitch set by the readout pitch setting unit is not a divisor of the total number of addresses of the waveform data stored in the storage unit,
The modulator removes spurious generated within the pass frequency band of the loop filter due to the readout pitch being not a divisor of the total number of addresses in the area storing the waveform data of the storage unit. by modulating the, Ru attenuated.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a phase locked loop circuit according to an embodiment of the present invention will be described with reference to the drawings.
The configuration of the phase-locked loop circuit according to the present embodiment is shown in FIG.
The phase-locked loop circuit according to the present embodiment includes a read pitch setting unit 11, a reference frequency signal output unit 12, a phase comparator 13, a loop filter 14, a voltage controlled oscillator 15, and a DDS 16.
[0013]
The read pitch setting unit 11 sets the pitch (K) of address data indicating the storage position of the waveform data stored in the memory 22 of the DDS 16.
[0014]
The reference frequency signal output unit 12 outputs a frequency signal having a target reference frequency.
[0015]
The phase comparator 13 compares the phase of the frequency signal output from the reference frequency signal output unit 12 with the phase of the signal output from the DDS 16, and as a comparison result, for example, has a pulse width according to the phase difference. A phase difference signal is output.
[0016]
The loop filter 14 is composed of a low-pass filter, that is, an integration circuit, and is a filter that removes a frequency in a high band (a frequency band higher than the cutoff frequency) of the phase difference signal output from the phase comparator 13. The pulse signal output from the phase comparator 13 is smoothed and output.
[0017]
The voltage controlled oscillator 15 outputs an oscillation signal having an oscillation frequency corresponding to the control voltage of the phase difference signal output from the phase comparator 13 via the loop filter 14. The voltage controlled oscillator 15 includes a variable capacitance diode, an oscillator, and the like (not shown) whose capacitance changes according to the applied control voltage, and changes the oscillation frequency according to the change in the capacitance of the variable capacitance diode.
[0018]
The DDS 16 outputs a signal synthesized based on the waveform data. The DDS 16 includes a waveform data reading unit 21, a memory 22, a D / A converter (digital-analog converter) 23, and an LPF 24.
[0019]
The waveform data reading unit 21 generates address data based on the data set by the read pitch setting unit 11, and reads the waveform data stored in the memory 22 based on the generated address data. The waveform data reading unit 21 includes a latch 25 and an adder 26.
[0020]
The latch 25 outputs the output data of the adder 26 to the memory 22 as address data every clock.
[0021]
The adder 26 adds the read pitch set by the read pitch setting unit 11 and the output value of the latch 25 and outputs the result to the latch 25.
With such a configuration, the waveform data reading unit 21 is configured such that, for example, if the reading pitch setting unit 11 specifies the pitch 2 and the initial value of the latch 25 is 0, the address data 0, 2, 4, 6,. . . Is output every time the clock (= the output signal of the voltage controlled oscillator 15) is output.
[0022]
The memory 22 stores waveform data. This waveform data is data for obtaining an output signal having a necessary waveform. For example, if the required waveform is a sine wave as shown in FIG. 2, the memory 22 stores waveform data as shown in FIG.
[0023]
Returning to FIG. 1, the D / A converter 23 reads waveform data from the memory 22 and converts the read waveform data into an analog signal. The D / A converter 23 includes a ΔΣ modulator 27 and a D / A converter 28.
[0024]
The ΔΣ modulator 27 performs ΔΣ modulation. Although the ΔΣ modulation method itself is arbitrary, in this embodiment, in order to facilitate understanding, a basic method of adding waveform data read from the memory 22 and delayed quantized data is added. Then, it is assumed to employ a method of integrating and quantizing the added data.
By performing such processing, the ΔΣ modulator 27 calculates the frequency distribution of spurious and quantization noise included in the waveform (the waveform after D / A conversion) corresponding to the read series of waveform data. Keep away from output frequency of DDS16. That is, the spurious within the pass frequency band of the loop filter 14 is attenuated.
[0025]
As described in the section of the prior art, this spurious is generated when the total number of addresses of the waveform data stored in the memory 22 is not an integral multiple of the read pitch set by the read pitch setting unit 11.
[0026]
In this embodiment, the ΔΣ modulator 27 includes a subtracter 31, an integrator 32, a quantizer 33, and a delay circuit 34, as shown in FIG.
[0027]
The subtractor 31 subtracts the data output from the delay circuit 34 from the waveform data read from the memory 22.
The integrator 32 integrates the difference between the waveform data output from the subtractor 31 and the delay data.
[0028]
For example, the quantizer 33 quantizes the data integrated by the integrator 32. Here, quantization means converting a high-resolution digital value into a low-resolution digital value (for example, 1/0).
The delay circuit 34 delays the data output from the quantizer 33.
[0029]
Returning to FIG. 1, the D / A converter 28 converts the digital data output from the ΔΣ modulator 27 into an analog signal.
[0030]
The LPF 24 is for cutting high-frequency components of the analog signal converted by the D / A converter 23.
[0031]
The DDS 16 supplies the output signal of the LPF 24 to the phase comparator 13.
[0032]
Next, the operation of the phase locked loop circuit according to the present embodiment will be described.
[0033]
The reference frequency signal output unit 12 generates a reference frequency signal having a predetermined reference frequency and outputs the reference frequency signal to the phase comparator 13.
[0034]
The read pitch setting unit 11 supplies the waveform data read unit 21 of the DDS 16 with the address pitch of the memory 22, that is, the DDS set number K shown in Equation 1.
[0035]
The adder 26 of the waveform data reading unit 21 adds the output value of the latch 25 and the DDS setting number K supplied from the reading pitch setting unit 11. Then, the adder 26 supplies the addition data to the latch 25. The latch 25 operates using the output signal of the voltage controlled oscillator 15 as a clock, latches the addition data output from the adder 26 for each clock, and outputs it to the memory 22 as address data. Further, the adder 26 cumulatively adds the DDS setting number K supplied from the read pitch setting unit 11 to the address data output from the latch 25.
Thus, for example, if the initial value of the latch 25 is 2 and the DDS setting number K is 4, the address values output from the latch 25 are 2, 6, 10, 14,. . . And change.
[0036]
The memory 22 outputs the waveform data stored at the storage position indicated by the address data in accordance with the address data output from the latch 25. In this manner, the waveform data is sequentially read from the memory 22 at the address pitch (address interval) specified by the DDS setting number K.
[0037]
The ΔΣ modulator 27 of the D / A converter 23 performs ΔΣ modulation on the waveform data read from the memory 22. First, the subtractor 31 of the ΔΣ modulator 27 subtracts the data output from the delay circuit 34 from the waveform data output from the memory 22 to obtain a difference between the two data. The integrator 32 integrates the difference output from the subtractor 31. The quantizer 33 quantizes the data integrated by the integrator 32. The delay circuit 34 delays the data quantized by the quantizer 33 and outputs the delayed data to the subtractor 31.
[0038]
The ΔΣ modulator 27 attenuates components near the DDS output frequency among the noise components included in the output waveform composed of a series of waveform data by performing such ΔΣ modulation. As a result, the remaining noise components remain mainly only in the frequency band cut by the loop filter 14. The ΔΣ modulator 27 outputs the waveform data subjected to ΔΣ modulation in this way to the D / A converter 28.
[0039]
The D / A converter 28 converts the waveform data output from the ΔΣ modulator 27 into an analog signal. The LPF 24 removes the high frequency component of the analog signal output from the D / A converter 23 and outputs this analog signal to the phase comparator 13.
[0040]
The phase comparator 13 compares the phase of the comparison frequency signal output from the DDS 16 with the reference frequency signal output from the reference frequency signal output unit 12, and corresponds to the phase difference between the two signals, for example, has a pulse width. The phase difference signal is output to the loop filter 14.
[0041]
The loop filter 14 removes high frequency components from the phase difference signal and outputs the phase difference signal to the voltage controlled oscillator 15.
[0042]
The voltage controlled oscillator 15 generates an oscillation signal having an oscillation frequency corresponding to the voltage of the phase difference signal smoothed by removing (ie, integrating) the high frequency component by the loop filter 14 and outputs the generated oscillation signal. To do.
[0043]
In this way, the phase locked loop circuit outputs a transmission signal synchronized with the target reference frequency signal.
[0044]
Next, the operation of the ΔΣ modulator 27 will be further described with reference to FIGS.
As described above, if the DDS setting number K is not a divisor of the address number ^2N of the memory 22, spurious S1, S2,... Of the spurious S1, S2,..., The spurious S1 on the frequency Fdds side of the cut-off frequency fc of the loop filter 14 cannot be removed by the loop filter 14.
[0045]
The ΔΣ modulator 27 attenuates spurious and noise components near the output frequency Fdds of the DDS 16 by performing ΔΣ modulation. Further, a high-frequency component having a cutoff frequency fc that is far from the output frequency Fdds is cut by the loop filter 14.
[0046]
As described above, in the PLL circuit of this embodiment, quantization noise and spurious can be reduced, and the signal purity of the oscillation signal output from the phase locked loop circuit can be improved.
[0047]
In addition, by inserting the ΔΣ modulator 27, a 1-bit D / A converter 28 can be used.
[0048]
In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment.
For example, the ΔΣ modulation method (order, etc.) and the circuit configuration of the ΔΣ modulator 27 are arbitrary. For example, the circuit configuration of the ΔΣ modulator 27 is not limited to that shown in FIG. 4 but may be that shown in FIG. 8 or FIG. The latch 25 does not need to operate using the output signal of the voltage controlled oscillator 15 as a clock. For example, the latch 25 may operate using a signal obtained by dividing the output signal of the voltage controlled oscillator 15 as a clock.
[0049]
In the ΔΣ modulator 27 shown in FIG. 8, the quantizer 33 quantizes the data output from the subtractor 31. The delay circuit 34 delays the data output from the quantizer 33. The integrator 32 integrates the data output from the delay circuit 34 and supplies the integrated data to the subtractor 31.
[0050]
Further, the ΔΣ modulator 27 shown in FIG. 9 further includes an integrator 35 in addition to the configuration of FIG. The integrator 35 integrates the data read from the memory 22 and supplies the integrated data to the subtractor 31.
[0051]
【The invention's effect】
As described above, according to the present invention, signal purity can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a waveform of a sine wave signal as an example of a signal output from the phase locked loop circuit shown in FIG. 1;
3 is an explanatory diagram showing waveform data of a sine wave signal shown in FIG. 2 as an example of waveform data stored in the memory of FIG. 1;
4 is a block diagram showing a configuration of the ΔΣ modulator of FIG. 1. FIG.
FIG. 5 is an explanatory diagram showing an operation of the phase locked loop circuit of FIG. 1;
6 is an explanatory diagram showing an operation of the phase-locked loop circuit of FIG. 1. FIG.
7 is an explanatory diagram showing an operation of the phase-locked loop circuit of FIG. 1. FIG.
FIG. 8 is a block diagram showing another configuration example of the ΔΣ modulator.
FIG. 9 is a block diagram showing still another configuration example of the ΔΣ modulator.
[Explanation of symbols]
11 Reading pitch setting unit 12 Reference frequency signal output unit 13 Phase comparator 14 Loop filter 15 Voltage controlled oscillator 22 Memory 23 D / A converter 24 LPF
27 ΔΣ modulator

Claims (1)

A reference signal output circuit for outputting a reference signal having a reference frequency;
A phase comparator that compares the phase of the reference signal with the phase of the predetermined signal and outputs a phase difference signal corresponding to the phase difference between the two signals;
A loop filter for filtering the output signal of the phase comparator;
An oscillator that outputs an oscillation signal having a frequency according to the phase difference signal that has passed through the loop filter;
A storage unit for storing waveform data;
A waveform data reading unit that reads the waveform data from the storage unit based on the output frequency of the oscillation signal;
A modulator that ΔΣ modulates the waveform data and outputs quantized data;
A digital-analog converter that converts the quantized data from the modulator into an analog signal and supplies the analog signal as the predetermined signal;
Equipped with a,
The storage unit stores waveform data at a plurality of addresses,
The waveform data reading unit
A read pitch setting unit for setting a pitch of a read address of the storage unit;
Means for generating a read address of the storage unit by accumulating the read pitch set by the read pitch setting unit;
Means for reading the waveform data by accessing the storage unit at the generated address;
With
Including the case where the readout pitch set by the readout pitch setting unit is not a divisor of the total number of addresses of the waveform data stored in the storage unit,
The modulator removes spurious generated within the pass frequency band of the loop filter due to the readout pitch being not a divisor of the total number of addresses in the area storing the waveform data of the storage unit. Attenuate by modulating to
A phase locked loop circuit characterized by that.

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