JP4060209B2 - Demodulation method and demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal sequence demodulating method and a demodulating device, and more particularly to a demodulating method and a demodulating device for avoiding the influence of noise in a synchronization portion in a previous stage of a data portion in a signal sequence.
[0002]
[Prior art]
When demodulating the data recorded on the magnetic medium or demodulating the received data in communication, timing is taken in the synchronization portion in the previous stage of the original data portion having information so that deviation and blurring do not occur. For this purpose, a signal (bit) for synchronization is written in the control information at the head of the data in the signal sequence. The signal for this synchronization is such that the same pulse width continues several times. In the demodulation in the synchronous portion, the subsequent data may be different from the original data due to misreading or noise mixed in recorded data or received data. The following explains data modulation and demodulation and points out their problems. Here, modulation / demodulation by the MFM (Modified Frequency Modulation) method will be described.
[0003]
FIG. 4 is a state transition diagram of modulation. One bit 0 and bit 1 in the bit string are set as signal states, and an encoded output is obtained when the state transitions, that is, when the bit changes. Here, the encode output is, for example, a pulse width. When bit 0 continues, it is inverted at the trailing edge of bit 0. When bit 0 changes to bit 1, it is inverted at the center of bit 1. When bit 1 continues, it is inverted at the center of bit 1 and when it changes from bit 1 to bit 0, it is not inverted. For this reason, the output pulse width is either 2, 3, or 4. In the following, it will be seen what pulse width a specific bit string has in accordance with the modulation state transition diagram of FIG. 4 (see FIG. 5).
[0004]
FIG. 5 shows a bit string and a pulse width obtained by modulating the bit string. The first bit of the bit string “0001000110100101” is “0”, and the next bit is also “0”. According to the modulation state transition diagram of FIG. 4, the bit width is 2 because bit 0 continues. When the third “0” in the bit string is changed to “1”, the pulse width is 3 because it is inverted at the center of bit 1. When encoded according to the modulation state transition diagram of FIG. 4 in this way, the pulse width is as shown in the lower digit string of FIG. Next, it will be seen that the numeric string of pulse widths encoded in this way is decoded (demodulated) into a bit string.
[0005]
FIG. 6 is a state transition diagram of demodulation. Since the start can be arbitrarily determined, the state D having a pulse width of 2 is set as the start here. Even if the pulse width is the same, the state may be different. In FIG. 6, the state A has the pulse width 2 as in the state D. The pulse width 3 also has a state B and a state E. Pulse width 4 is in state C. Referring to FIG. 7, it will be seen what bit string is formed by decoding the encoded pulse width.
[0006]
FIG. 7 shows a bit string from the synchronous part to the part entering the data body. Since the encoded first pulse width is “2”, the state becomes D from the start according to FIG. In the pulse width of FIG. 7, since the pulse width is “2”, that is, the state D continues, the bit string becomes “0” when decoded. The pulse width shifts from “2” to “3” when moving from the synchronous portion to the data body. As a result, the state transitions from state D to state B. Referring to the demodulating state transition diagram of FIG. 6, when transitioning from state D to state B, the bit string is “01”. Since the pulse width “3” is next to the pulse width “3”, the state further changes from the state B to the state A. At this time, referring to the demodulation state transition diagram of FIG. 6, the bit string becomes “1”. Next, since the pulse width is 4, the state further moves from state A to state C. At this time, referring to the demodulation state transition diagram of FIG. 6, the bit string becomes “01”. In this way, the pulse width is decoded into a bit string (see Non-Patent Document 1).
[0007]
[Non-Patent Document 1]
Satoshi Hirose, 4 others, “Next Generation Digital Modulation / Demodulation Technology”, Trikes, May 31, 1995, p. 45, 46
[0008]
[Problems to be solved by the invention]
Next, consider the problem when noise enters the synchronous part. FIG. 8 shows an example of decoding when noise enters the third pulse width of the synchronous portion. Since the first and second pulse widths are “2”, the bit string “0” is obtained by continuing the state D as in the case of FIG. 7 described above. When the third one is decoded, the state shifts from state D to state B, so that a bit string “01” is obtained. After this, since there is no noise after the fourth, the pulse width “2” continues. This indicates that the state transitions from state B to state A and state A continues. Thereby, the bit string “1” is continuously obtained. When shifting from the synchronous portion to the data body, the state shifts from state A to state E by changing the pulse width from “2” to “3”. As a result, the bit string “0” is obtained. This is different from the correct bit string obtained in the normal case (see FIG. 7). In FIG. 8, the lowermost bit string indicates the correct bit string (the same as the bit string in FIG. 7).
[0009]
As described above, if noise enters the middle of the synchronization portion, a correct bit string cannot be obtained when the data body is decoded. In particular, the last part “xxx” in the figure has a pulse width that does not change from “2” to “4”, that is, there is no state that goes from state D. It becomes impossible. In this case, it is recorded as an error and the decoding process is stopped, or the state is held until a pulse width that can interpret the state transition comes.
[0010]
In view of the above-described problems, an object of the present invention is to provide a demodulation method and a demodulation device that avoids the influence of noise by returning to a correct state even if noise enters in the middle of the synchronization portion.
[0011]
[Means and Actions for Solving the Problems]
In order to achieve the above object, a demodulation method and a demodulation device according to the present invention are configured as follows.
[0012]
The demodulation method according to the present invention (corresponding to claim 1) detects that a processing state other than the initial processing state that does not transit in the synchronization portion continues in the demodulation method of the signal sequence in the synchronization portion, and performs initial processing. It is characterized by forcibly switching to a state . By forcibly switching to the initial processing state, the bit string obtained by subsequent decoding processing is made correct, and the processing state is processed as the original initial processing state, thereby improving the reliability .
[0014]
A demodulating device according to the present invention (corresponding to claim 2 ) is a demodulating device comprising a signal reading unit, a shaping circuit for shaping the read signal, and a processing arithmetic unit, wherein the processing arithmetic unit is shaped by the shaping circuit. When the processing state determination unit that processes the signal and determines which processing state the signal is in, and when it is detected that the processing state different from the initial processing state first determined by the processing operation unit in the synchronization portion continues, A processing state forcible switching unit that forcibly switches to an initial processing state is provided.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Since the state transition diagram in the process is the same as that in the prior art, the modulation state transition diagram in FIG. 4 and the demodulation state transition diagram in FIG.
[0017]
FIG. 1 is a schematic configuration diagram of a demodulation device. The demodulator 10 includes a signal reading unit 11, an amplifier 12 that amplifies the read signal, a shaping circuit 13 that shapes the amplified signal, and a processing calculation unit 14. The processing calculation unit 14 includes a CPU 15, a processing state determination unit 17, and a memory 16 that stores a processing state forced switching unit 18.
[0018]
The signal read by the signal reading unit 11 is amplified by the amplifier 12, shaped by the shaping circuit 13, and input to the processing calculation unit 14. The processing calculation unit 14 demodulates the input signal. Since the first input signal is a synchronous part, the state D usually continues (see FIG. 6). However, as shown in FIG. 8, if noise enters the synchronization portion where the same state should continue, the read data becomes different from the original data.
[0019]
In the above description of demodulation, it is assumed that the start is from the state D. However, even when the start is from the state E, if noise enters the synchronization portion where the same state should continue, Similarly, the read data is different from the original data. Therefore, the state D and the state E are defined as a processing state T (initial processing state), and the other states A, B, and C are distinguished from the processing state S. By distinguishing in this way, it is possible to discriminate between states A, B, and C, and states D and E, which cannot be synchronized parts.
[0020]
In the processing state determination unit 17 of the processing operation section 14 determines whether a a a or processing state T processing state S. In processing state forced switch unit 18, counts the number of processing state S by processing state S number counter, the count number is a predetermined number, for example, forcing the processing state when continued for 4 times from the processing state S to the processing state T Switch. By forcibly switching the processing state in this way in the synchronous part, it is possible to avoid erroneous reading after switching.
[0021]
FIG. 2 is a diagram illustrating a processing flow performed by the processing calculation unit 14. The state of the signal first read and demodulated at the start of reading by the processing state determination unit 17 is set to state D (step S101). Here, since the state D is the processing state T, the initial processing state is the processing state T. The processing state S count counter is cleared by the processing state forcible switching unit 18 (step S102). Here, since it is a synchronous part of the previous stage of the data body, the head of the data is not detected. Next, it is determined whether or not to end (step S103). If not, the pulse width data is captured (step S104), and it is determined whether the data head has been detected (step S105). If the head of data has been detected, the data body is decoded (step S106), and it is determined whether or not the processing is finished (step S103). If the head of data has not been detected, a decoding process before detecting the data body is performed (step S107). The result of the decoding process performed here is stored as a bit string, and is used to determine the data body pattern in the next step S108. When the pulse pattern of the data head is detected (step S108), the process proceeds to the detection of the data head (step S109).
[0022]
If the decoding process before the data body detection is performed and the pulse pattern at the head of the data is not detected, it is determined whether or not the processing state is the processing state S (step S110). If the process state is not the process state S, it is determined whether or not the process is finished (step S103). When the processing state is the processing state S, one processing state S count counter is counted (step S111). It is determined whether the counted processing state S count counter number (S count counter value) is an arbitrary number N or less (step S112). N is set in advance according to the length of the synchronous part before the data body is detected. In this embodiment, it is 4.
[0023]
If the S count counter value is equal to or less than an arbitrary number N, it is determined whether or not the process is finished (step S103). When the S count counter value is larger than an arbitrary number N, the state is switched to D for correction. That is, the processing state is changed from the processing state S to the processing state T, and the processing state is reset (step S113). The treatment state is changed and the processing state S count counter is cleared (step S114).
[0024]
Next, a bit string in the decoding process before detecting the data body will be specifically shown and described. FIG. 3 shows a pulse width, a bit string obtained by demodulating the pulse width, and a state. FIG. 3 shows a case where noise enters the third bit string in the decoding process of the synchronous part before the data body is detected. Referring to the demodulation state transition diagram of FIG. 6, since the first and second pulse widths are “2”, the bit string continues with “0” and continues with state D. Next, since the third pulse width is “3”, the bit string becomes “1” and the state B is entered. As a result, the processing state changes from the processing state T to the processing state S. Since the pulse width 2 continues after the pulse width 3, the state transition from the state B to the state A continues according to the demodulation state transition diagram of FIG. State B and state A are both processing states S. The processing state is determined by the processing state determination unit 17 of the processing calculation unit 14. When the processing state S continues, the processing state is forcibly switched by the processing state forcible switching unit 18. In FIG. 3, when the pulse width 2 of the pulse width 3 continues, that is, when the processing state S changes from the processing state T to the processing state S and the processing state S continues four times, the processing state is forcibly switched. In FIG. 3, the state is switched from the state A in the processing state S to the state D in the processing state T. By forcibly switching the processing state in this way, the subsequent decoding process is returned to normal, so that a correct bit string can be obtained when the data body is decoded. As described above, the modulation / demodulation by the MFM (Modified Frequency Modulation) method has been described. However, the present invention is not limited to this, and the present invention can be applied to the same problem in the method of performing the same processing.
[0025]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
[0026]
In the demodulation of the signal sequence in the synchronous part, it detects that a specific processing state continues, and the processing state is forcibly switched, so even if noise enters the middle of the synchronous part, the noise is affected by returning to the correct state. And a correct bit string can be obtained in the subsequent decoding process.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a demodulator.
FIG. 2 is a diagram illustrating a processing flow performed in a processing calculation unit.
FIG. 3 shows a pulse width, a bit string obtained by demodulating the pulse width, and a state.
FIG. 4 is a state transition diagram of modulation.
FIG. 5 shows a bit string and a pulse width obtained by modulating the bit string.
FIG. 6 is a state transition diagram of demodulation.
FIG. 7 shows a bit string from a synchronous part to a part entering a data body.
FIG. 8 shows an example of decoding when noise is included in the third pulse width of the synchronous portion.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Demodulator 11 Signal reading part 12 Amplifier 13 Shaping circuit 14 Processing calculating part 15 CPU
16 Memory 17 Processing state discrimination unit 18 Processing state forced switching unit

Claims (2)

In the method of demodulating the signal sequence in the synchronous part,
A demodulation method, comprising: detecting that a processing state other than an initial processing state that does not transit in the synchronous portion continues and forcibly switching the processing state to the initial processing state . In a demodulator comprising a signal reading unit, a shaping circuit for shaping the read signal, and a processing operation unit,
A processing state determination unit that processes the signal shaped by the shaping circuit and determines in which processing state the signal is;
When the processing operation section in synchronization portion and first initial processing state is judged different processing state is detected to continue, the processing state forced switch section for switching to force the processing state to the initial processing state,
A demodulating device comprising:

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