JP4063944B2 - Manufacturing method of three-dimensional semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a three-dimensional semiconductor integrated circuit device by bonding using a micro integration technique.
[0002]
[Prior art]
LSI (Large Scale Integrated Circuit) has been highly integrated and improved in performance due to advances in microfabrication technology. However, with the miniaturization of elements, problems such as an increase in wiring resistance and parasitic capacitance have arisen.
Furthermore, recently, the limit of device miniaturization has started to be discussed, and it is considered difficult to achieve high performance simply by miniaturizing the device.
[0003]
As a solution to such a problem, there is a three-dimensional semiconductor integrated circuit. In this three-dimensional semiconductor integrated circuit, by using vertical interlayer wiring, it is possible to increase the degree of freedom of wiring and shorten the wiring length, thereby enabling parallel data transfer using vertical wiring.
[0004]
[Problems to be solved by the invention]
However, conventionally studied three-dimensional semiconductor integrated circuits employ a method in which an element is formed, an insulating film is formed, and a single crystal is formed on the insulating film.
This method is repeated to fabricate elements and sequentially form integrated circuits. Therefore, the process (steps) is lengthened and the yield is remarkably lowered, so that it has not yet been put into practical use.
[0005]
In addition, in order to solve the problems of the conventional three-dimensional integrated circuit, research on a three-dimensional semiconductor integrated circuit device by bonding is being promoted, but no technically satisfactory one has been produced. It is.
In view of the above situation, an object of the present invention is to provide a method for manufacturing a three-dimensional semiconductor integrated circuit device by bonding, which can reduce the number of steps, can be manufactured quickly and accurately, and can improve reliability.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
[1] In a manufacturing method of a three-dimensional semiconductor integrated circuit device by bonding,
(A) forming a vertical interconnect embedded in a trench and setting an upper wafer on which a semiconductor integrated circuit is formed;
(B) forming bumps on the end faces of the vertical interconnects of the upper wafer;
(C) bonding to a wafer serving as a substrate on which a lower-layer semiconductor integrated circuit is formed via the bump;
(D) A step of injecting an insulating adhesive between the upper and lower two-layered wafers bonded and laminated only with the bumps.
[0007]
[2] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the insulating adhesive may be injected using a pressure difference by sealing a wall other than the insulating adhesive injection port with a wall. It is a thing.
[3] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1] or [2], a plurality of the upper wafers are stacked.
[0008]
[4] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [3], a step of injecting an insulating adhesive at a time between the bumps on which the plurality of laminated wafers are bonded is performed. Is.
[5] The method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], wherein an epoxy adhesive is used as the insulating adhesive.
[0009]
[6] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], in the step (a), the upper and lower two-layer wafers are positioned after being thinned by a chemical mechanical polishing method. Is.
[7] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the bump is a bump made of one kind or two or more kinds of metals.
[0010]
[8] In the method for manufacturing a three-dimensional semiconductor integrated circuit device according to [1], a conductive adhesive layer is formed on all or a part of the surface of the bump.
[9] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the wall and the bump are made of Cu.
[10] In the method of manufacturing a three-dimensional semiconductor integrated circuit device according to [1], the bump is made of Au / In.
[0011]
Here, it should be understood that the wafer includes a large-scale and large-area chip.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is a cross-sectional view of a three-dimensional semiconductor integrated circuit device by bonding showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a manufacturing process of the three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. It is an adhesive injection | pouring process sectional drawing in the manufacturing process of the three-dimensional semiconductor integrated circuit device which shows the Example.
[0013]
In FIG. 1, reference numeral 1 denotes a first layer LSI wafer, 11 denotes a second layer LSI wafer, 21 denotes a third layer LSI wafer, and the LSI wafers 1, 11, and 21 of each layer include silicon substrates 2, 12, MOSFETs 3, 13, 23, etc. are formed in 22.
This three-dimensional semiconductor integrated circuit uses a manufacturing method in which a thin layer is formed by a chemical mechanical polishing (CMP) method from the back surface of a wafer on which an element is manufactured, and then laminated and laminated in multiple layers. . The stacked integrated circuits are electrically connected by pre-made micro bumps and vertical embedded wiring.
[0014]
That is, a vertical interconnect 17 is formed on the field oxide film 16, and micro bumps (Cu or Au / In) 19 are formed on the end surfaces of the vertical interconnect 17 and bonded to the micro bumps of the stacked wafers. Let An insulating adhesive (epoxy adhesive) 20 is injected between the bonded micro bumps 19 to embed the micro bumps 19.
[0015]
This three-dimensional semiconductor integrated circuit uses a manufacturing method in which a thin layer is formed by chemical mechanical polishing (CMP) from the back surface of a wafer on which an element is manufactured, and then laminated and laminated in multiple layers. . The stacked integrated circuits are electrically connected by pre-made micro bumps and vertical embedded wiring.
Here, the formation of buried interconnects, wafer thinning, wafer alignment, and wafer bonding using an adhesive injection method are important techniques.
[0016]
Here, it is necessary to make a deep silicon trench to form a vertical buried interconnect. A silicon trench having a depth exceeding 50 μm can be formed by using a high-speed inductively coupled plasma (ICP) etching apparatus and optimizing the etching conditions. It is also possible to form a deep silicon trench having a depth of 100 μm.
[0017]
The wafer thickness is reduced to 50 μm by grinding and chemical mechanical polishing (CMP). It is easy to make the thickness less than 10 μm.
For wafer alignment, the alignment tolerance can be ± 0.5 μm.
When Cu bumps are used as metal bumps, it is necessary to apply a conductive adhesive such as an epoxy-based silver paste to the bump surfaces in advance in order to bond the upper and lower Cu bumps. A printing method was used to apply the silver paste to the Cu bump surface. In addition, when apply | coating to the surface of a bump of a conductive adhesive, it forms on the surface of all or one part of the bump.
[0018]
Hereinafter, a method for manufacturing a three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIG.
(1) First, as shown in FIG. 2 (a), first, in order to make a vertical interconnection to the second layer LSI wafer 11 which is a thinned two-dimensional LSI wafer, it is buried in a trench. The vertical interconnect 17 is embedded by depositing n ⁺ polysilicon. Needless to say, the buried vertical interconnect 17 is not limited to n ⁺ polysilicon but may be a conductor such as metal.
[0019]
(2) Next, as shown in FIG. 2 (b), a two-dimensional LSI wafer having vertical interconnects 17 is bonded to quartz glass 18, and subjected to grinding and chemical mechanical polishing to a thickness of about 50 μm. Until thin.
(3) Next, as shown in FIG. 2C, micro bumps 19 are formed on the end face of the embedded vertical interconnect 17 of the second-layer LSI wafer 11.
(4) Next, as shown in FIG. 2 (d), the thin second layer LSI wafer 11 is carefully aligned with the first layer LSI wafer substrate 1 via the micro bumps 19, and the thick first layer Bonded to the LSI wafer substrate 1.
[0020]
This procedure is repeated, and several thin wafers are stacked on the first-layer LSI wafer substrate 1.
(5) Finally, as shown in FIG. 2 (e), an insulating adhesive 20 is injected into the gap between the wafers to enhance the bondability of the wafer.
Next, the adhesive injection process in the manufacturing process of the three-dimensional semiconductor integrated circuit device showing the embodiment of the present invention will be described in detail with reference to FIG. Here, Cu bumps were used as the bumps, and an insulating epoxy adhesive was used as the insulating adhesive.
[0021]
(1) First, as shown in FIG. 3A, a Cu wall 43 is formed on each wafer so as to surround the Cu bumps 42. A small inlet 44 is formed in a part of the Cu wall 43. The wafer group 41 on which such wafers are stacked is placed in a vacuum chamber evacuated to about 10 ⁻³ Torr. Here, the Cu wall can be formed simultaneously with the formation of the Cu bump, which is advantageous in the manufacturing process. However, the wall may be formed of an insulator or the like instead of the Cu wall.
[0022]
(2) Next, as shown in FIG. 3B, the portion including the inlet 44 of the Cu wall 43 of the stacked wafer group 41 is immersed in an insulating epoxy adhesive 45 in a vacuum state.
(3) Next, as shown in FIG. 3 (c), the vacuum state is broken. For example, N ₂ gas is leaked.
(4) Then, as shown in FIG. 3D, when the vacuum state is broken and the atmospheric pressure is reached, the pressure in the wafer gap in the Cu bump region is lower than the atmospheric pressure. Insulating epoxy adhesive 45 is injected by capillary action.
[0023]
Therefore, the insulating epoxy adhesive 45 can be injected not only between two wafers but also into a gap between many wafers at the same time (see FIG. 1).
FIG. 4 is a view showing a plane after bonding a glass substrate onto a silicon substrate having a Cu bump using the adhesive injection method, and FIG. 4A is a plan view of the wafer having the Cu bump. 4 (b) is an enlarged view of portion A (in the vicinity of the Cu wall) in FIG. 4 (a), and FIG. 4 (c) is an enlarged view of portion B (inside the Cu wall) in FIG. 4 (a).
[0024]
As is apparent from these drawings, the insulating epoxy adhesive 45 is uniformly filled in the Cu wall 43 except for the Cu bumps 42, and no void is generated as shown in FIG. 4B. On the other hand, the insulating epoxy adhesive 45 is injected into the gap between the outer wafers of the Cu wall 43 by capillary action, but this injection is not uniform. That is, the void 46 was observed in the insulating epoxy adhesive 45.
[0025]
FIG. 5 is a cross-sectional view of FIG.
As is apparent from FIG. 5, an insulating epoxy adhesive 45 is formed between the Cu bumps 42. That is, it can be seen that the insulating epoxy adhesive 45 has entered a place other than the Cu bump.
Insulating epoxy adhesive mixes the main agent and curing agent and cures by chemical reaction, so there is little volume change after curing.
[0026]
For the micro bumps, Au / In may be used instead of Cu.
In the case of Au / In bumps, after bonding the bumps, the temperature is raised to near 150 ° C., which is the melting point of In, so that an alloy can be made by bonding the bumps together. Therefore, it was possible to produce the bump without having to consider the size of the silver filler contained in the adhesive, which was a problem when making the Cu bump.
[0027]
The production method and bonding method of Au / In bumps are described below, and experimental results are shown.
A positive resist is applied on the entire surface by spin coating on a wafer provided with a silicon oxide film, and then the bumps to be formed are patterned. Then, In (3 μm) and Au (3000 Å) are continuously deposited by a vacuum deposition apparatus. Thereafter, the Au / In bump can be produced by placing the silicon wafer on which the Au / In bump is produced in acetone and performing ultrasonic cleaning (lift-off method).
[0028]
FIG. 6 is a view showing a cross section of an Au / In bump (40 μm square, 3 μm high) bonded between two layers by using an adhesive injection method according to another embodiment of the present invention.
In FIG. 6, 61 is an upper layer wafer, 62 is a lower layer wafer, 63 and 64 are Au / In bumps, 71 is an insulating epoxy adhesive, and an insulating epoxy adhesive 71 is provided between the very narrow upper layer wafer 61 and the lower layer wafer 62. Injected without voids. So far, the injection of adhesive using Au / In bumps of 2 μm in height and 5 μm square has been succeeded.
[0029]
Next, in order to examine the electrical characteristics of the Au / In bumps 63 and 64, test chips for the Au / In bumps 63 and 64 were produced. The method and the electrical characteristic results of the Au / In bumps 63 and 64 are shown below.
In order to investigate the electrical characteristics of the Au / In bump, a test chip capable of passing an electric current through an Al wiring and a plurality of bumps was produced. In this test chip, Au / In bumps are formed on the Al wiring, and polyimide is applied as a wiring protective film to a place other than the bumps. Further, the pad for applying the probe is located outside the wafer to be bonded by extending the Al wiring so that the pad can be used when the wafers are bonded to each other. Using this test chip, an experiment was conducted to measure the resistance of the Au / In bump by passing a current through the Al wiring.
[0030]
FIG. 7 is a diagram showing the measurement results.
This is a result of electrical characteristics obtained when current was passed through 42 bonded Au / In bumps (20 μm square, height 3 μm).
From this result, although the resistance per Au / In bump is about 12Ω, the resistance value per Au / In bump calculated from the depth, length, and specific resistance of the Al wiring, Au, and In bump layer is about 1Ω. Therefore, the measured value is higher than the calculated value, but low resistance is sufficiently expected by improving the process.
[0031]
In this manner, a microbump necessary for the three-dimensional integration technique is manufactured, and a three-dimensional semiconductor integrated circuit device using the adhesive injection method can be manufactured.
Using this adhesive injection method, it was confirmed that an insulating adhesive can be injected void-free between wafers bonded by Au / In or Cu bumps.
As a result, an adhesive injection technique could be established as a wafer bonding method.
[0032]
Further, a test chip for measuring the electrical characteristics of the Au / In bump can be produced, and a current can be passed through 42 bumps connected in series.
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0033]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
(1) According to the invention described in claim 1, in the method of manufacturing a three-dimensional semiconductor integrated circuit device, the number of steps can be reduced, the device can be quickly and accurately manufactured, and the reliability can be improved.
[0034]
(2) According to the invention described in claim 2, the assembly of the LSI wafer can be strengthened by injecting the insulating adhesive between the bumps of the wafer.
(3) According to the invention described in claim 3, a plurality of layers of LSI wafers can be easily assembled, and the degree of integration can be improved.
(4) According to the invention described in claim 4, the assembly of a plurality of laminated wafers can be easily and reliably performed at a time.
[0035]
(5) According to the invention described in claim 5, since the epoxy adhesive is mixed with the main agent and the curing agent and cured by a chemical reaction, the volume change after curing is small.
(6) According to the invention described in claim 6, the upper and lower LSI wafers can be positioned accurately because they are positioned after being thinned by a chemical mechanical polishing method.
[0036]
(7) According to the invention described in claim 7, the upper and lower LSI wafers can be firmly bonded.
(8) According to the invention described in claim 8, it is possible to ensure electrical connection between the upper and lower LSI wafers.
(9) According to the invention of claim 9, the process can be simplified using a typical material, and stable walls and bumps can be formed.
[0037]
(10) According to the invention of the tenth aspect, an alloy can be made by bonding bumps, and strong temporary fixing can be performed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a bonded three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is a manufacturing process sectional view of a three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention;
FIG. 3 is a cross-sectional view of an adhesive injection process in a manufacturing process of a three-dimensional semiconductor integrated circuit device showing an embodiment of the present invention.
FIG. 4 is a diagram illustrating a plan view after a glass substrate is bonded onto a silicon substrate having Cu bumps using an adhesive injection method in a manufacturing process of a three-dimensional semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 5 is a diagram showing a cross section of FIG. 4;
FIG. 6 is a view showing a cross section of an Au / In bump bonded between two layers using an adhesive injection method according to another embodiment of the present invention.
FIG. 7 is a view showing a measurement result of resistance of a bonded Au / In bump according to another embodiment of the present invention.
[Explanation of symbols]
1 First layer LSI wafer 2, 12, 22 Silicon substrate 3, 13, 23 MOSFET
4, 14 Wiring 11 Second layer LSI wafer 16 Field oxide film 17 Vertical interconnect 18 Silica glass 19 Micro bump (metal bump: Cu or Au / In)
20 Insulating adhesive (epoxy adhesive)
21 Third layer LSI wafer 41 Wafer group 42 Cu bump 43 Cu wall 44 Entrance 45, 71 Insulating epoxy adhesive 46 Void 61 Upper layer wafer 62 Lower layer wafer 63, 64 Au / In bump

Claims (10)

In a manufacturing method of a three-dimensional semiconductor integrated circuit device by bonding,
(A) forming a vertical interconnect embedded in a trench and setting an upper wafer on which a semiconductor integrated circuit is formed;
(B) forming bumps on the end faces of the vertical interconnects of the upper wafer;
(C) bonding to a wafer serving as a substrate on which a lower-layer semiconductor integrated circuit is formed via the bump;
(D) A method of manufacturing a three-dimensional semiconductor integrated circuit device, comprising: injecting an insulating adhesive between the upper and lower two-layer wafers bonded and laminated only by the bumps. 2. The method of manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein the insulating adhesive is injected using a pressure difference by sealing a wall other than the insulating adhesive inlet with a wall. -Dimensional semiconductor integrated circuit device manufacturing method. 3. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein a plurality of the upper wafers are stacked. 4. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 3, wherein a step of injecting an insulating adhesive at a time between the bumps on which the plurality of laminated wafers are bonded is performed. A method of manufacturing a semiconductor integrated circuit device. 2. The method of manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein an epoxy adhesive is used as the insulating adhesive. 2. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein in the step (a), the upper and lower two-layer wafers are positioned after being thinned by a chemical mechanical polishing method. A method of manufacturing a semiconductor integrated circuit device. 2. The method of manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein the bump is a bump made of one or more kinds of metals. 2. The method for manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein a conductive adhesive layer is formed on the surface of all or part of the bumps. 2. The method of manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein the wall and the bump are made of Cu. 2. The method of manufacturing a three-dimensional semiconductor integrated circuit device according to claim 1, wherein the bump is made of Au / In.

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