JP4075882B2 - Cache memory hit rate measurement circuit, processor and method - Google Patents

Description

  The present invention relates to a cache memory hit rate measuring circuit for measuring a hit rate of a cache memory of a computer, a processor having a cache memory hit rate measuring function, and a cache memory hit rate measuring method.

  As a method of measuring the cache hit rate using hardware resources, there is a method disclosed in Japanese Patent Laid-Open No. 5-20187. In the method of this publication, the cache hit rate is measured from the number of cache hits with respect to an arbitrary number of data replacements. Japanese Patent Laid-Open No. 2-201561 also discloses a similar cache hit rate measuring circuit.

JP-A-5-20187 JP-A-2-2015561

  By the way, there is a demand for knowing in real time the change in the cache memory hit rate within a certain period of time in order to improve the processing capability and performance of the operation of specific software. However, each of the above-described methods has a problem that only the hit rate obtained from the accumulated number of hits of the cache memory can be obtained, and a cache memory hit rate having a high real-time property cannot be obtained. In JP-A-2-2015561, it is said that the hit rate can be continuously monitored, but the hit rate is calculated each time the cache access counter becomes full. It is not enough to grasp the cache access status.

  In addition, if the trend of the cache memory hit rate during the operation of specific software can be known in real time, it can be used to improve performance afterwards by taking measures such as changing the system configuration. Is also expected to spread greatly.

  The present invention has been made in view of the above-described circumstances, and monitors the trend of the hit rate of the cache memory within a certain cycle and can output the hit rate of the cache memory in real time, and the cache memory An object of the present invention is to provide a method for measuring the hit rate.

  According to a first aspect of the present invention that provides means for solving the above-described problems, a hit ratio measurement circuit for a cache memory including the following wiretapping is provided. The cache memory hit rate measurement circuit includes a register circuit, and stores and holds the cache access result a predetermined number of times each time a cache access is performed. The cache memory hit rate measurement circuit includes a counter circuit, and counts the number of cache hits stored in the register circuit in synchronization with the operation of the register circuit. The hit ratio measurement circuit of the cache memory includes an output circuit, and outputs the counted number of cache hits.

  According to a second aspect of the present invention, there is provided a cache memory hit rate measuring circuit comprising an N-bit shift register, a cache hit counter, and an output circuit for outputting a cache hit. The shift register holds cache access results sequentially input in a predetermined cycle. The cache hit counter holds the contents input to the least significant bit of the shift register and the counter value (number of cache hits per N cycles) updated based on the contents output from the most significant bit. The output circuit outputs the counter value of the cache hit counter, and this value represents the cache hit rate per N cycles. The hit ratio measurement circuit of the cache memory includes a timing generation circuit that generates a clock signal for driving the shift register. The timing generation circuit transmits a clock signal as a result of cache access when an upper designated bit of an address requested by a CPU (Central Processing Unit) is changed.

  According to the third aspect of the present invention, the internal cache memory, the cache control circuit for managing the internal cache memory and outputting a signal indicating the result of the cache access, and the hit rate measurement of the cache memory described above And a processor comprising the circuit.

  According to a fourth aspect of the present invention, there is provided a cache memory hit rate measuring method using an N-bit shift register. First, a step of monitoring whether or not the upper designated bit of the address requested by the CPU has been changed and generating a clock signal when the upper designated bit of the address is changed and at least a cache line change is detected is performed. Is called. Then, in synchronization with the clock signal, a step of serially inputting the cache access result to the shift register is performed. Then, based on the content input to the least significant bit of the shift register and the content output from the most significant bit, a step of updating the number of cache hits recorded in the shift register is performed, and then the updated cache A step of sequentially outputting the number of hits is performed.

  According to the present invention, the number of cache hits for the past N cycles can be obtained in real time. The number of cache hits can be considered as a cache hit rate within the past fixed processing cycle of the CPU, and can be used to improve processing capability and performance during operation of specific software.

  Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a processor according to the present embodiment. Referring to FIG. 1, a cache memory hit rate measuring circuit 3 according to the present invention is shown in addition to the basic configuration of a cache mechanism comprising a CPU 2, a cache control circuit 9, a TAG memory 12, a cache memory 4, and an external memory. Has been.

  The CPU 2 is connected to the cache control circuit 9, and the cache control circuit 9 is connected to the cache memory 4 and the TAG memory 12. Data output from the cache memory 4 is connected to the selector 19 for external memory data and transferred to the CPU 2.

  FIG. 2 is a diagram showing a detailed configuration of the hit rate measurement circuit 3 of the cache memory. Referring to FIG. 2, the hit rate measurement circuit 3 of the cache memory is roughly provided with a timing generation circuit 5, a shift register 6, a counter 7, and an output circuit 8.

  The timing generation circuit 5 includes a bus cycle start timing generation circuit 23, an address latch (A) 29, an address latch (A-1) 35, an AND gate 27, frequency dividing circuits 32 and 34, a comparator 33, A flip-flop 37 is provided, and a CPU address 16 and a signal 17 indicating a cache access hit state are input from the cache control circuit 9. Further, the timing generation circuit 5 supplies the shift register 6 with a shift clock signal 1 described later in detail and a (cache hit) signal 18 corresponding to the signal 17 received from the cache control circuit 9.

  The bus cycle start timing generation circuit 23 supplies a clock signal to the address latch (A) 29, the address latch (A-1) 35, and the AND gate 27 at the beginning of the bus cycle.

  The address latch (A) 29 is a circuit that latches the address 16 of the CPU, and the address latch (A-1) 35 is a circuit that latches the address of the address latch (A) 29. The comparator 33 constituted by an exclusive OR gate compares the values of the address latch (A) 29 and the address latch (A-1) 35, and outputs it as a signal 36 indicating that the cache access has been performed.

  The frequency dividing circuit 34 is a circuit that outputs a divided clock to the output circuit 8 side, and the frequency dividing circuit 32 is a circuit that outputs an external output request for serial output to the output circuit 8 side. The serial output timing of the hit ratio of the cache memory can be changed by setting parameters of the frequency dividing circuits 32 and 34 from the CPU 2 via the data bus 30.

  The shift register 6 includes N flip-flops, and can hold the contents of the (cache hit) signal 18 received from the timing generation circuit 5, that is, the history of the past N cache accesses. The shift register 6 supplies a signal for a counter value up / down operation described later to the counter 7.

  The counter 7 holds a counter value that is increased or decreased based on the input and output states of the shift register 6. The counter value 50 of the counter 7 is input to the output circuit 8.

  The output circuit 8 receives the counter value 50 of the counter 7 and serially outputs data to the outside at the timing specified by the frequency dividing circuits 32 and 34.

  Next, the operation of the present embodiment will be described. First, the schematic operation of the cache mechanism will be described with reference to FIG. First, the cache control circuit 9 compares the address 16 output from the CPU 2 with the data in the TAG memory 12 to determine whether or not the cache is hit.

  When the cache is hit, the signal 17 indicating the hit state of the cache access becomes active “1”. When the selector 19 that has received the active signal 17 connects the data bus 13 and the data bus 11 of the cache memory 4, the CPU 2 can acquire the cache data.

  On the other hand, when the cache does not hit, the signal 17 indicating the cache access hit state becomes inactive “0”. The selector 19 that has received the inactive signal 17 selects the data bus 14 of the external memory, so that the data of the external memory is sent to the data bus 11.

  Next, the operation of the cache memory hit rate measurement circuit 3 will be described with reference to the timing charts of FIGS. The address latch (A) 29 latches the address 16 of the CPU 2 at the timing output from the start timing generation circuit 23 of the bus cycle. The address latch 35 latches the value of the address latch 29 at the start timing of the next bus cycle.

  The comparator 33 compares the address latch (A) 29 and the address latch (A-1) 35 and changes the address exceeding the lower n bits (n = number of cache line bits) (in other words, the upper address specifying bit). When the change occurs, a signal 36 with active “1” is output.

  On the other hand, the bus cycle start timing generation circuit 23 transmits a signal 38 which is active “1” at the bus cycle start timing. Therefore, the clock signal 1 supplied to the shift register and the counter via the AND gate 27 and the flip-flop 37, when both the start condition of the bus cycle and the change of the address are satisfied, that is, crosses at least the cache line. When such an access occurs, it becomes active “1”.

  Further, the signal 17 output from the cache control circuit 9 is a signal that becomes active “1” when the cache hits, and in order to match the shift timing of the shift register 6, the flip-flop 37 is the same as the clock signal 1. And (cache hit signal) 18 is input.

  FIG. 4 is a diagram for explaining the operation of the shift register 6 and the counter 7. Referring to FIG. 4, the signal 18 indicating the cache hit state output from the timing generation circuit 5 is supplied to the least significant bit 60 of the shift register 6 at the rising timing of the clock signal 1.

  The input signal 107 ((cache hit) signal 18) to the shift register 6, the signal 103 taken from the most significant bit 6n of the shift register 6, and the enable input to the counter 7 via the exclusive OR gate Depending on the state of the signal 105, the counter 7 is increased or decreased as shown in Table 108. Accordingly, the count value is updated to be the same as the number of “1” held in each of the registers 60 to 6n of the shift register 6. As is clear from Table 108, when the signal input to the shift register 6 and the output signal are the same, the enable signal 105 becomes inactive “0”, the counter does not operate, and the state is maintained. To do.

  The counter value 50 held in the counter 7 in this way is once held in a latch inside the output circuit 8, and the serial output 15 is sent at the timing of the divided clock and the transmission request sent from the frequency dividing circuits 32 and 34. Is done.

  In this way, it is possible to output in real time by holding and counting the number of cache hits for each access cycle of the CPU. Since this output value is the number of cache hits in a fixed N cycle, the change can be used as the cache hit rate.

  Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and it goes without saying that other modifications and detailed specifications can be made by those skilled in the art. It is. For example, the configuration of the bus cycle start timing generation circuit 23 described above is a matter that is appropriately changed according to the type of the CPU 2.

It is a figure showing schematic structure of one embodiment of the present invention. It is a figure showing the detailed structure of the hit rate measurement circuit of the cache memory based on one embodiment of this invention. It is a timing chart for describing one embodiment of the present invention. It is a figure for demonstrating operation | movement of the shift register and counter of one embodiment of this invention.

Explanation of symbols

1 (shift register) clock signal 2 CPU
3 Cache memory hit rate measurement circuit 4 Cache memory 5 Timing generation circuit 6 Shift register 7 (Cache hit) counter 8 Output circuit 9 Cache control circuit 11, 13, 14 Data bus 12 TAG memory 15 Serial output 16 Address 17, 36, 38 signal 18 (cache hit) signal 19 selector 23 bus cycle start timing generation circuit 26, 31 system clock 27 AND gate 29 address latch (A)
32, 34 Frequency divider 33 Comparator 35 Address latch (A-1)
37 Flip-flop 50 Counter value 60 Shift register least significant bit 6n Shift register most significant bit 103, 107 Signal 105 Enable signal 108 Table

Claims (4)

An N-bit shift register that operates in a predetermined cycle and serially inputs a cache access result;
A cache hit counter that counts the number of cache hits recorded in the shift register based on the content input to the least significant bit of the shift register and the content output from the most significant bit;
An output circuit for outputting a counter value of the cache hit counter,
A cache memory hit rate measuring circuit characterized by the above. The hit ratio measurement circuit for a cache memory according to claim 1 , further comprising:
A timing generation circuit that detects whether or not at least an upper designated bit of an address requested from the CPU has been changed and generates a clock signal for driving the shift register;
A cache memory hit rate measuring circuit characterized by the above. Built-in cache memory,
A cache control circuit for managing the internal cache memory and outputting a signal indicating a result of the cache access;
A cache memory hit rate measuring circuit according to claim 1 or 2 ,
Processor. A cache memory hit rate measuring method using a cache memory hit rate measuring circuit having an N-bit shift register,
Cache memory hit rate measurement circuit
Monitoring whether or not the upper designated bit of the address requested by the CPU is changed, and generating a clock signal when the upper designated bit of the address is changed and at least a change in the cache line is detected;
Synchronously with the clock signal, serially inputting a cache access result to the shift register;
Updating the cache hit count recorded in the shift register based on the content input to the least significant bit of the shift register and the content output from the most significant bit;
Sequentially outputting the updated number of cache hits,
A method for measuring a hit rate of a cache memory, characterized by:

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