JP4079766B2 - Digital tv broadcast receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital television broadcast receiver, and more specifically, to a digital television broadcast receiver provided with means for reducing deterioration of reception / reproduction media due to deterioration of a reception state. Here, the reception / reproduction medium means video, audio and data received and reproduced by the receiver.
[0002]
[Prior art]
Digital television broadcasts have higher frequency utilization efficiency than analog broadcasts, and it is possible to improve the quality of reception media and increase the number of channels. However, paying attention to the high quality, the high quality may not be sufficiently maintained depending on the reception state. For example, this is the case where the receiver is an in-vehicle digital television broadcast receiver.
[0003]
In an in-vehicle digital television broadcast receiver (hereinafter also simply referred to as a receiver), the reception state changes from moment to moment as the vehicle moves, and video, audio or data reproduced by the receiver deteriorates. May end up. For example, when the vehicle approaches a radio wave shielding / reflecting object such as a building or a mountain, or its traveling speed changes, the radio wave received from the broadcasting station may fluctuate sharply or cause a momentary interruption. There are things to do.
[0004]
As a known technique related to the receiver of the present invention described later, there is Patent Document 1 below. In this document, when the operation of the digital VTR is being played back and is in a still function state, when a TS (transport stream) signal can be received, the image immediately before the still function state is set as a still image. Is.
[0005]
[Patent Document 1]
JP 2001-339684 A
[0006]
[Problems to be solved by the invention]
In the digital television broadcast receiver, when the reception state is deteriorated, deterioration of video and audio may appear suddenly. Looking at this video, for example, a plurality of rectangular green block noises suddenly appear on the television screen, and in the worst case, the video is completely invisible. If you look at the sound, you suddenly hear a blast.
[0007]
Such a phenomenon is not possible in the case of analog broadcasting so far, and not only can not provide users with high-quality video, audio and data services, but also the user can be uncomfortable. There is a problem of giving.
[0008]
Therefore, in view of the above problems, an object of the present invention is to provide a digital television broadcast receiver that can be viewed without causing discomfort to the user even when the reception state deteriorates.
[0009]
[Means for Solving the Problems]
FIG. 1 is a basic configuration diagram of a digital television broadcast receiver according to the present invention.
[0010]
The digital television broadcast receiver 1 of the present invention basically includes an RF / IF processing unit 3 that uses a digital television broadcast wave from an antenna 2 as an input signal (IN), and an output from the RF / IF processing unit 3. The digital television broadcast receiver includes a demodulation / separation processing unit 4 that demodulates and separates, and a decoder unit 5 that decodes the output from the demodulation / separation processing unit 4.
[0011]
Here, the feature of the present invention is that a freeze control means 6 is introduced. Specifically, the freeze control means 6 includes a decoder unit based on the error signal ER output from the demodulation / separation processing unit 4 or the error signal ER ′ detected by itself when an error is included in the input signal IN. 5 has a function of performing freeze control for stopping or stopping at least one of a video signal, an audio signal, and a data signal transmitted from the output (OUT).
[0012]
Thus, by turning on the freeze control of the video signal, the audio signal, or the data signal based on the error signal ER, these signals can be stopped or stopped at an early stage. In other words, before the block noise described above appears on the TV screen, and before the explosion sound described above is output from the audio section, these can be stopped or stopped, giving the user an uncomfortable feeling. It is prevented.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Various embodiments according to the present invention will be described below.
[0014]
FIG. 2 is a diagram showing a first specific configuration example of the receiver 1 to which the present invention is applied.
FIG. 3 is a diagram showing a second specific configuration example of the receiver 1 to which the present invention is applied. Note that the same reference numerals or symbols are given to the same components throughout the drawings.
[0015]
First, referring to FIG. 2, an RF-baseband processing unit 31 is shown as the core part of the RF / IF processing unit 3 of FIG. In addition to this, the processing unit 3 includes a tuner unit and a filter unit, which are not shown.
[0016]
Next, the demodulation / separation processing unit 4 in FIG. 1 is shown as an OFDM (Orthogonal Frequency Division Multiplex) demodulation processing unit 41 and a TS (Transport Stream) -DEMUX (demultiplex) processing unit 42 in the example of FIG. The reason why the OFDM demodulation processing unit 41 is used is because the OFDM system is mainly used as digital television broadcasting, and the reason why the TS-DEMUX processing unit 42 is used is as a compression technique for the digital television broadcasting signal. This is because the MPEG (Moving Picture Experts Group) -SYSTEM standard has become mainstream.
[0017]
Further, as the decoder unit 5 in FIG. 1, a video decoder 51 and an audio decoder 52 are shown in the example of FIG. These are MPEG video decoders and MPEG audio decoders.
[0018]
A display processing circuit 7 and a D / A converter 8 are connected to the subsequent stages of these decoders 51 and 52, respectively, and a video output signal Sv and an audio output signal Sa are sent to a display unit (not shown).
[0019]
Here, the freeze control means 6 of FIG. 1 which characterizes the present invention is shown as a freeze control unit 61 in FIG.
[0020]
When viewed as the receiver 1 as a whole, the circuit portions (31, 41, 42, 51, 52, 61) are integrated and controlled by the CPU 9 via the common bus 12. The ROM 10 and RAM 11 cooperate with the CPU 9 for this integrated control.
[0021]
Next, referring to FIG. 3, the configuration of this figure is almost the same as that of FIG. The difference is that the freeze control unit 61 is rearranged between the TS-DEMUX processing unit 42 and the decoders 51 and 52. The configuration of FIG. 3 is employed in some embodiments of the present invention (described later).
[0022]
The specific configuration example of the entire receiver 1 has been described above. The freeze control unit 6 (freeze control unit 61) that characterizes the present invention will be described in detail below.
[0023]
[First embodiment]
In the first mode of the freeze control means 6, the means 6 turns on the freeze control immediately after detecting the error signal ER. This is shown in a flowchart.
[0024]
FIG. 4 is a flowchart showing the operation of the freeze control means 6 in the first mode.
[0025]
In this figure,
Step S11: It is determined whether or not the error signal ER is detected.
[0026]
Step S12: If the error signal ER is detected (Yes), the freeze control is immediately turned on.
[0027]
Step S13: If the error signal ER is not detected (No), the freeze control that was turned on is immediately turned off.
[0028]
Here, looking at the error signal ER, the OFDM demodulation processing unit 41 itself has already been marketed as an LSI, and each packet ( There is a configuration in which the error signal ER is output when an error is included in the transport stream TS). When such an LSI is used, the error signal ER can be easily obtained. The error signal ER may be detected when the error signal ER rises to “H” or falls to “L”.
[0029]
[Second embodiment]
Next, as a second mode of the freeze control means 6, in step S12 (also S13) in FIG. 4, the freeze control is executed without distinction on all media such as video signals and audio signals. . This is shown in a flowchart.
[0030]
FIG. 5 is a flowchart showing the operation of the freeze control means 6 in the second mode.
[0031]
In this figure,
Step S21: Same as step S11 (FIG. 4).
[0032]
Step S22: When freeze control is on, screen stillness and audio mute are executed simultaneously.
[0033]
Step S23: The screen still and the audio mute are canceled at the same time.
[0034]
[Third embodiment]
As a third aspect of the freeze control means, the freeze control is turned on (and turned off if necessary), not immediately as in the first and second aspects described above, but only after a predetermined time has elapsed. To. When the freeze control is immediately turned on each time the error signal ER is generated, the user is provided with video / audio that is frequently stopped / stopped, and feels uncomfortable.
[0035]
Therefore, in the third aspect, a predetermined time is waited until the freeze control is actually turned on. Specifically, the freeze control means 6 according to the third aspect is characterized in that the freeze control is executed (ON or OFF) based on the number of occurrences of the error signal ER (ER ′) per predetermined unit. It is. This avoids frequent video / audio pauses / stops and provides the user with the advantage of maintaining normal video and audio for as long as possible. The specific configuration is shown in FIG.
[0036]
Next, the fourth, fifth and sixth aspects will be described. According to these aspects, in addition to the above-described advantages according to the third aspect, further advantages can be obtained.
[0037]
[Fourth aspect]
In the first to third aspects, the freeze control is uniformly executed regardless of the type of the input signal IN. However, the freeze control means 6 according to the fourth aspect is provided in the demodulation / separation processing unit 4. The demodulated signal after the demodulating process is divided into a video signal, an audio signal, and a data signal, and freeze control is executed for each signal. This eliminates the disadvantage that, for example, only the video signal is deteriorated, but the freeze control is turned on even for a normal audio signal. For example, when the TV program being viewed is a “concert”, if the video is degraded, the user can enjoy only the music by stopping only the video. On the other hand, for example, when the TV program being watched is “soccer”, if the sound is degraded, only the sound is stopped (muted) so that it can be enjoyed only by the player of the soccer player. it can.
[0038]
FIG. 6 is a diagram showing a configuration example of the freeze control means 6 in the fourth mode. The freeze control means 6 is a freeze control unit 61 shown in FIG. 2 in detail.
[0039]
The demodulated signal (transport stream signal) from the OFDM demodulation processing unit 41 is first stored in the data buffer 62 and then input to the demultiplexing (DEMUX) preprocessing unit 63. In the processing unit 63, based on the program map table (PMT) included in the transport stream (TS) signal, a video signal (video unit 64), an audio signal (audio unit 65), and a data signal (data broadcasting unit 66). ) And separately. Note that the reason why it is referred to as separation (DEMUX) preprocessing as described above is because a part of the processing that the existing TS-DEMUX processing unit 42 originally should perform is performed in advance.
[0040]
The video signal, audio signal, and data signal thus individually separated are subjected to data analysis in the corresponding data analysis units 67, 68 and 69. By this data analysis, the freeze control unit 61 detects the error signal ER ′ by itself. An example of this detection method is CRC (Cyclic Redundancy Check).
[0041]
Here, if the error signal ER ′ is detected, the freeze ON / OFF control unit 70 executes freeze control. That is, freeze control is turned on. If the error signal ER ′ is no longer detected, the freeze control that was turned on is turned off. This freeze control may be performed directly on the decoder unit 5 (FIG. 1), that is, the TS-DEMUX processing unit 42, or may be performed as a command to the processing unit 42 via the CPU 9 and the common bus 12. good.
[0042]
[Fifth aspect]
In the fourth aspect, the separation (DEMUX) pre-processing unit 63 is introduced into the freeze control unit 61. However, in this fifth aspect, the separation pre-processing is left to the original TS-DEMUX processing unit 42. To. Therefore, the freeze control unit 61 in the fifth mode is arranged as shown in FIG. 3 (not FIG. 2).
[0043]
Eventually, the freeze control means 6 in the fifth mode executes freeze control for each of the video signal, audio signal and data signal after the separation (DEMUX) processing in the demodulation / separation processing unit 4. According to the fifth aspect, as compared with the fourth aspect, it is naturally possible to obtain an advantage that the configuration of the freeze control unit 61 is simplified.
[0044]
[Sixth aspect]
In the fourth and fifth aspects, freeze control is performed for each signal of video and audio and data. In the sixth aspect, freeze control is performed separately for each hierarchy. As is well known, various programs can be provided for each layer.
[0045]
FIG. 7 is a diagram showing a configuration example of the freeze control means 6 in the sixth mode.
[0046]
The freeze control means 6 corresponds to the freeze control unit 61 in FIG. In FIG. 7, the same components as those in FIG. 6 are given the same reference numerals.
[0047]
Therefore, newly shown in FIG. 7 are error count units 72, 73 and 74, an A layer unit 75, a B layer unit 76 and a C layer unit 77, and a counter 78. The counter 78 counts the number of packets for each layer. That is, how many packets are input to the A layer and how many packets are input to the B layer are individually examined.
[0048]
Each of the error count units 72, 73, and 74 receives the error signal output from the OFDM demodulator 41 for each layer (A, B, and C), and performs each error count.
[0049]
Note that the A, B, and C layers 75 to 77 are originally built in the TS-DEMUX processing unit 42.
[0050]
After all, when the input signal IN includes a plurality of hierarchies, the freeze control means 6 in the sixth mode divides the demodulated signal in the demodulation / separation processing unit 4 into each hierarchies. On the other hand, freeze control is executed.
[0051]
[Example 1]
According to the third aspect described above, the freeze control means 6 executes (on or off) the freeze control based on the number of occurrences of the error signal ER (ER ′) per predetermined unit.
[0052]
In order to realize this, the freeze control means 6 (61) according to the first embodiment, when the input signal IN is composed of a series of packets, in order to define the predetermined unit, the number of packets that arrive sequentially A packet counter (80) for counting
[0053]
The freeze control means 6 (61) has an error counter (81) for detecting the presence or absence of an error signal ER for each packet and counting the number of error signals ER.
[0054]
FIG. 8 is a diagram showing the configuration of the first embodiment according to the present invention.
[0055]
The demodulated signal from the OFDM demodulation processing unit 41 (FIG. 2) is input to the packet counter 80, and the error signal ER from the processing unit 41 is input to the error counter 81.
[0056]
The packet counter 80 may be connected to a signal line from the OFDM demodulation processing unit 41 indicating the beginning of each packet, for example, a TS / SYNC line, or a header of one packet (for example, consisting of 204 bytes). A code (for example, 0x47) may be detected.
[0057]
On the other hand, the error counter 81 detects the rising (or falling) or the like of the error signal ER and counts up the error count value.
[0058]
Thus, for example, the error count value is seen every 10 packets, and the freeze control is turned on only when the error count value exceeds 2, for example.
[0059]
[Example 2]
According to the first embodiment (FIG. 8), the time when the freeze control changes from OFF to ON is the same as the time when the freeze control changes from ON to OFF.
[0060]
Then, although the reception state deteriorates, it is not possible to perform fine control such as providing a user with clean video and audio for as long as possible or providing the user with clean video and audio as soon as the reception state is improved.
[0061]
Thus, the second embodiment realizes such fine control.
[0062]
That is, the freeze control means 6 (61) according to the second embodiment uses the on-time packet counter (83) and the packet counter 80 corresponding to when the freeze control is on and when the freeze control is off, respectively. And an off-time packet counter (84).
[0063]
In addition, the freeze control means 6 (61) according to the second embodiment includes an on-time error counter (85) and an error counter 81 corresponding to when the freeze control is on and when the freeze control is off, respectively. An off-time error counter (86) is provided. These are shown in FIG.
[0064]
FIG. 9 is a diagram showing the configuration of the second embodiment according to the present invention.
[0065]
In the figure, the above-mentioned on / off-time packet counters 83 and 84 are shown, and the above-mentioned on / off-time error counters 85 and 86 are shown. Reference numeral 70 denotes a freeze ON / OFF control unit shown in FIGS. The control unit 70 switches the contacts of the switches 87 and 88 up and down depending on whether the control unit 70 is in an on state or an off state.
[0066]
The freeze control operation using the count values of the on / off time packet counter (83, 84) and the on / off time error counter (85, 86) will be described more specifically. However, if all of the four counters of the on / off packet counter and the on / off error counter are focused on, the explanation becomes complicated. Therefore, the packet counter 80 and the error counter 81 represent two counters, respectively. The following explanation will be given.
[0067]
Example 3
FIG. 10 is a diagram showing the configuration of the third embodiment according to the present invention.
[0068]
In this figure, a new component is a packet counter set value holding unit 90. The set value held in advance in the holding unit 90 is compared with the count value of the packet counter 80, and the count values of the counters 80 and 81 are cleared based on the comparison result.
[0069]
FIG. 11 is a flowchart showing the operation of the third embodiment (FIG. 10) according to the present invention.
[0070]
When the count value exceeds a certain value (packet counter set value) (Yes in step S31), the packet counter 80 clears the counter (S32) and newly starts counting the next incoming packet. To do.
[0071]
Further, when the count value of the packet counter 80 exceeds the above certain value (Yes in S31), the error counter 81 is cleared (S32), and the error counter 81 is counted by the error signal ER that comes next. Start anew.
[0072]
If the determination in step S31 is No, the counter is not cleared and the current count value is maintained as it is (S33).
[0073]
For example, if the detected error signal ER is less than 2 up to 10 consecutive packets, both counters (80, 81) are returned to the initial state.
[0074]
Example 4
FIG. 12 is a diagram showing the configuration of the fourth embodiment according to the present invention.
[0075]
In this figure, a new component is an error counter set value holding unit 91. The set value held in advance in the holding unit 91 is compared with the count value of the error counter 81, and the count values of the counters 80 and 81 are cleared based on the comparison result.
[0076]
FIG. 13 is a flowchart showing the operation of the third embodiment (FIG. 12) according to the present invention.
[0077]
When the count value of the error counter 81 exceeds a certain value (error counter set value) (Yes in step S41), the packet counter 80 is cleared (S42). Start counting anew.
[0078]
When the count value of the error counter 81 exceeds the certain value (Yes in S41), the error counter 81 is cleared (S42), and the error counter 81 is counted by the next incoming error signal ER. Start anew.
[0079]
Step S43 is the same as step S33 in FIG.
[0080]
For example, assume that the packet counter set value of the packet counter 80 is 20, and the error counter set value of the error counter 81 is 10. In this case, if the error counter 81 reaches the set value (10) earlier than the packet counter 80, the count value of the packet counter 80 is no longer meaningful to count up any more. The packet counter 80 is immediately cleared.
[0081]
The operation when the error signal ER is detected in the fourth embodiment will be described.
[0082]
FIG. 14 is a flowchart illustrating an operation when an error signal is detected in the fourth embodiment.
[0083]
In this figure, step S51 is the same as S41 described above.
[0084]
If the determination in step S51 is Yes, the error count value has exceeded the set value, so it is returned to 0 again (clearing S55).
[0085]
On the other hand, if the determination in step S51 is No, the presence / absence of the error signal ER is detected (S52). Here, “error signal detection” means that the rising edge (or falling edge) of the error signal is detected as described above.
[0086]
If the error signal is detected (Yes in step S52), the count value in the error counter 81 is further incremented by 1 (S53).
[0087]
On the other hand, if the error signal is not detected, the count value in the error counter 81 is held as it is (S54). That is, when the error signal does not arrive, the count value of the error counter is held as it is until the count value of the packet counter exceeds a certain value.
[0088]
After all, before the count value of the error counter 81 exceeds a certain value, the freeze control state is maintained, and when the count value of the error counter 81 exceeds a certain value, the freeze control is executed. This state is shown in FIGS. 15 and 16.
[0089]
FIG. 15 is a diagram showing a configuration in which the freeze ON / OFF control unit 70 is incorporated in FIG.
FIG. 16 is a flowchart showing the operation in the configuration of FIG.
[0090]
First, referring to FIG. 15, a freeze ON / OFF control unit 70 (see FIGS. 6, 7, and 9) that receives the output of the error counter 81 is provided, and the control unit 70 controls the freeze on the decoder side or the CPU 9 side. ON / OFF command is given.
[0091]
Referring to FIG. 16, step S61 is the same as S41 described above, and when the determination is Yes, the freeze control is turned on. Conversely, when the determination is No, the freeze control state (ON or OFF) is held as it is.
[0092]
Next, a case where the freeze control that has been turned on is turned off will be described. That is, “freeze control release”.
[0093]
Basically, when the error signal ER (ER ′) is not detected, the freeze control means 6 turns off the freeze control that is turned on.
[0094]
In this case, the freeze control means 6 can immediately turn off the above-described freeze control that is turned on. This situation corresponds to steps S11 → S13 in FIG. 4 described above, and the freeze control is immediately turned off.
[0095]
Example 5
Even when the freeze control is canceled, the freeze control means 6 has a packet counter 80 that counts the number of packets that arrive sequentially in order to define the predetermined unit described above, and an error signal ER for each packet. An error counter 81 is provided for detecting the presence or absence of (ER ′) and counting the number of error signals.
[0096]
FIG. 17 is a diagram showing the configuration of the fifth embodiment according to the present invention.
[0097]
FIG. 18 is a flowchart showing the operation of the fifth embodiment (FIG. 17) according to the present invention.
[0098]
Referring to FIG. 18, the count value of the packet counter 80 is equal to or greater than a certain value (packet counter set value) (Yes in step S71), and the count value of the error counter 81 is a certain value (error counter set value). ) If this is the case, freeze control is turned on as described above (S73).
[0099]
On the other hand, if the count value of the packet counter 80 is equal to or greater than the certain value (Yes in step S71) and the count value of the error counter 81 is less than the certain value, the freeze control is turned off. (S74).
[0100]
That is, regarding the release of the freeze control, if the count value of the packet counter 80 exceeds a certain value but does not exceed the certain value, the freeze control that is turned on is turned off.
[0101]
Example 6
The sixth embodiment is characterized in that when the display delay information is included in the packet, the freeze control is executed with a delay by the delay time.
[0102]
Specifically, the display delay information is PTS or DTS.
[0103]
For example, according to the MPEG-SYSTEM standard, PTS and DTS are defined in the transport stream TS. PTS is Presentation Time Stamp, so-called reproduction output time management information, and DST is Decode Time Stamp, so-called decoding time management information. These PTS and DTS are display delay information for instructing the receiver that the display of the video signal should be delayed for a predetermined time.
[0104]
Considering such display delay information, it is preferable to delay the on / off switching timing when the freeze control is executed (on → off or off → on). This will be described using a time chart.
[0105]
FIG. 19 is a diagram illustrating the timing of freeze control on / off in the sixth embodiment.
FIG. 20 is a diagram showing the configuration of the sixth embodiment according to the present invention.
[0106]
First, referring to FIG. 19, 1) is a basic clock CLK in the receiver 1, and timing control is performed based on this.
[0107]
2) shows the switching timing of the freeze control from on to off, and 5) shows the reverse switching timing.
[0108]
What should be noted here is that, in 2), the on-to-off switching timing originally occurs at the timing a in FIG. Also in 5), the switching from OFF to ON occurs at the timing b in the figure.
[0109]
However, in the sixth embodiment, the original ON → OFF and OFF → ON switching is intentionally delayed by the PTS / DTS delay time shown in 4).
[0110]
The effect thus obtained is shown in 3) and 6) in the figure. First, paying attention to 3), the screen was originally provided with a clean screen (hatching) from the time point a, but according to the sixth embodiment, only a clean screen after a ′ can be provided. Become.
[0111]
Next, paying attention to 6), since there is a display delay, it seems to the user that it is not dirty at the time point b. Therefore, it is possible to continue providing a clear video for a long time (until time b ′) using the display delay.
[0112]
Next, referring to FIG. 20, the separation (DEMUX) preprocessing unit 93 extracts the PTS and DST from the transport stream TS, and switches the freeze ON / OFF control unit 70 by the delay time. Delay timing control.
[0113]
Example 7
In the seventh embodiment, the freeze control is executed after a certain period of time instead of the display delay information (PTS / DTS) in the sixth embodiment.
[0114]
FIG. 21 corresponds to FIG. 19 in the sixth embodiment. In 4), “PTS / DTD delay time” is merely changed to “fixed time”.
[0115]
The configuration of the seventh embodiment is almost the same as that of the sixth embodiment (FIG. 20). However, in the seventh embodiment, it is necessary to provide a soft timer (or hard timer) for setting the predetermined time in the freeze ON / OFF control unit 70 instead of the PTS / DTS in FIG.
[0116]
The sixth and seventh embodiments can be applied to all modes other than the mode in which the freeze control is performed immediately.
[0117]
Example 8
In the above description, in FIGS. 1 to 3, (i) the error signal is output from the OFDM demodulation processing unit 4 (ER), and (ii) the error signal is detected by the freeze control means 6 itself (ER ′ However, there is also (iii) what is output from the decoder unit 5 (ER ″) as the error signal. The eighth embodiment corresponds to (iii).
[0118]
That is, the freeze control means 6 (61) of the eighth embodiment uses the error display signal ER ″ 1 output from the control terminal of the decoder unit 5 (51, 52) or the internal register of the decoder unit 5 (51, 52). When the error display signal ER ″ 2 to be written is not detected, the freeze control that is turned on is turned off.
[0119]
Similarly, the freeze control means 6 (61) is an error display signal ER ″ 2 output from the control terminal of the decoder unit (51, 52) or an error display signal written to the internal register of the decoder unit 5 (51, 52). When freeze is detected, freeze control is turned on.
[0120]
FIG. 22 is a flowchart showing the operation of the first mode in the eighth embodiment.
FIG. 23 is a flowchart showing the operation of the second mode in the eighth embodiment.
[0121]
First, referring to FIG. 22, if the existing error signal ER ″ 1 from the decoders 51 and 52 is in an “error display” state, for example, the CPU 9 determines “Yes” (Yes in step S81), freezes are performed. The control is turned on (S82), and if it is “none” (No in S81), the freeze control that was turned on is turned off.
[0122]
Next, referring to FIG. 23, for example, the CPU 9 accesses an existing error display register in the decoders 51 and 52 (step S91), and the register value in the error display register is a value indicating “with error” ( ER ″ 2), for example, if the CPU 9 determines that “there is an error” (Yes in S92), the freeze control is turned on (S93), and if it is “no error” (No in S92), it is on. Turn freeze control off.
[0123]
Example 9
As shown in FIG. 2 and FIG. 3, the digital television broadcast receiver 1 includes a CPU 9 that can control at least the freeze control means 6. The freeze control means 6 can execute freeze control in response to the control signal from the CPU 9. This is Example 9.
[0124]
In this case, the CPU 9 can directly output a command indicating on / off of the freeze control (first form),
The freeze control determination information indicating whether or not the freeze control by the CPU 9 is necessary is written into the freeze control register provided in the CPU 9 or the freeze control register provided in the freeze control means 6, and this is controlled by the freeze control means 6. You can also read it yourself (second form).
[0125]
FIG. 24 is a flowchart showing the operation of the first embodiment.
FIG. 25 is a flowchart showing the operation of the second mode.
[0126]
Referring first to FIG. 24, if the control signal (freeze on / off command) from the CPU 9 indicates that the freeze is on or not, the freeze control means 6 (61) determines that it is “on” (Yes in S101). The freeze control is turned on (S102), and if it is “off” (No in S101), it is turned off (S103).
[0127]
Next, referring to FIG. 25, the freeze control register in the CPU 9 or the freeze control register in the freeze control means 6 (61) is accessed, the freeze control determination information written therein is read, and the freeze control is performed according to the determination. Is turned on (S113) or turned off (S114).
[0128]
Example 10
The freeze control means 6 (61) in the tenth embodiment performs freeze control by supplying or stopping the input signal IN from the demodulation / separation processing unit 4 (41, 42) to the decoder unit 5 (51, 52). It is something to execute.
[0129]
26, 27, and 28 show the first, second, and third modes of the tenth embodiment, respectively.
[0130]
First, referring to FIG. 26, the demodulated signal stored in the data buffer 62 is transmitted or not transmitted to the decoder unit 5 via the output control unit 94 according to the output of the freeze ON / OFF control unit 70.
[0131]
Referring to FIG. 27, in the above-described separation (DEMUX) preprocessing unit 63, the demodulated signal is transmitted or not transmitted to the TS-DEMUX processing unit 42 through the freeze ON / OFF control unit 70. . In this case, transmission or non-transmission can be individually performed for the video decoder and the audio decoder.
[0132]
Referring to FIG. 28, the third form corresponds to a combination of the first form (FIG. 26) and the second form (FIG. 27).
[0133]
29 and 30 are diagrams more specifically showing the second embodiment (FIG. 27) and the third embodiment (FIG. 28).
[0134]
Example 11
The freeze control means 6 (61) according to the eleventh embodiment changes the criterion for determining whether or not to perform freeze control according to the type of video signal.
[0135]
The freeze control means 6 (61) changes a criterion for determining whether or not to execute the freeze control according to the type of the audio signal.
[0136]
Furthermore, each of the above determination criteria may be changed simultaneously according to the type of video signal and the type of audio signal.
[0137]
In order to determine the video and audio types, the video / audio type determination data in the transport stream TS is used (for example, PSI (program specific information / SI (Service Information)) or the like). The counter set value and the error counter set value are stored in the freeze control unit 61, and there are methods such as sending a set value from the CPU, etc. Video types include still images, slow moving videos, and fast moving. If the video / audio type discrimination data of the TS is a genre such as baseball, news, race, etc., it is necessary to determine in advance which video type to distinguish.
[0138]
For example, the screen may be somewhat disturbed for news, but it is noted that it is better to turn on / off the freeze control as soon as possible for a race.
[0139]
The freeze control means 6 (61) can also set a criterion for determining whether or not to perform freeze control in accordance with an instruction from the outside (user).
[0140]
FIG. 31 is a diagram illustrating an example of giving an instruction from the user in the eleventh embodiment.
[0141]
M in the figure is a marker on the display.
[0142]
The user can adjust the level of freeze control, such as performing freeze control even for slight image disturbance (perform fast, high sensitivity), or not for slight image disturbance (perform slow, low sensitivity). , Realized by GUI. For the adjustment of the freeze control level, the packet counter set value and the error counter set value are used as the above determination criteria. For example, if the number of errors is the same, the sensitivity is high if the packet counter set value is small, and the sensitivity is low if the packet counter set value is large. On the other hand, if the packet counter set value is the same, the sensitivity is large if the error counter set value is small, and the sensitivity is small if the error counter set value is large.
[0143]
Note that the packet counter set value and the error counter set value corresponding to the GUI are stored in the freeze control unit 61, and the CPU 9 sends the above set value.
[0144]
Furthermore, the user may be allowed to select whether or not to perform freeze control (naturally) according to preference.
[0145]
FIG. 32 is a diagram showing another example for that purpose. In the example of this figure, it is instructed to perform freeze control.
[0146]
Example 12
In the first form of the twelfth embodiment, the freeze control means is activated or deactivated by an external instruction signal input to the CPU 9.
[0147]
FIG. 33 is a diagram showing an example of the first embodiment.
[0148]
In the first embodiment, when “no freeze control” is written in a register in the CPU 9, the freeze control unit 61 stops the counting operations of the packet counter 80 and the error counter 81.
[0149]
In the second mode of the twelfth embodiment, the freeze control is turned on or off by a logical operation of the output from the freeze ON / OFF control unit and the instruction signal to the CPU 9.
[0150]
FIG. 34 (a) shows an example of the second embodiment, and FIG. 34 (b) shows a timing chart of the main part.
[0151]
The logical operation is performed in the logical operation unit 95. Even if the freeze ON / OFF control unit 70 is “freeze ON” (1), if the external freeze control state R is “control OFF” (2), the output of the logic operation unit 95 becomes “L” (3) ). On the other hand, when the control unit 70 is “freeze OFF” (1), even if the control state R becomes “control ON” (2), the output of the calculation unit 95 remains “L” (3).
[0152]
【The invention's effect】
As described above in detail, according to the present invention, in a digital television broadcast receiver, a situation where the screen suddenly disappears or a sudden sound is heard as the reception state deteriorates is prevented from being given to the user as much as possible. Can provide high-quality media.
[Brief description of the drawings]
FIG. 1 is a basic configuration diagram of a digital television broadcast receiver according to the present invention.
FIG. 2 is a diagram showing a first specific configuration example of a receiver 1 to which the present invention is applied.
FIG. 3 is a diagram illustrating a second specific configuration example of the receiver 1 to which the present invention is applied.
FIG. 4 is a time chart showing the operation of the freeze control means 6 in the first mode.
FIG. 5 is a time chart showing the operation of the freeze control means 6 in the second mode.
FIG. 6 is a diagram showing a configuration example of freeze control means 6 in the fourth mode.
FIG. 7 is a diagram showing a configuration example of freeze control means 6 in the sixth mode.
FIG. 8 is a diagram showing a configuration of Example 1 according to the present invention.
FIG. 9 is a diagram showing a configuration of a second embodiment according to the present invention.
FIG. 10 is a diagram showing a configuration of a third embodiment according to the present invention.
FIG. 11 is a flowchart showing the operation of the third embodiment according to the present invention.
FIG. 12 is a diagram showing a configuration of a fourth embodiment according to the present invention.
FIG. 13 is a flowchart showing the operation of the fourth embodiment according to the present invention.
FIG. 14 is a flowchart illustrating an operation when an error signal is detected in the fourth embodiment.
15 is a diagram showing a configuration in which a freeze ON / OFF control unit 70 is incorporated in FIG.
16 is a flowchart showing an operation in the configuration of FIG.
FIG. 17 is a diagram showing a configuration of a fifth embodiment according to the present invention.
FIG. 18 is a flowchart showing the operation of the fifth embodiment according to the present invention.
FIG. 19 is a diagram illustrating freeze on / off timing in the sixth embodiment.
FIG. 20 is a diagram showing a configuration of a fifth embodiment according to the present invention.
FIG. 21 is a diagram showing freeze on / off timing in the seventh embodiment of the present invention.
FIG. 22 is a flowchart showing the operation of the first mode according to the eighth embodiment of the present invention.
FIG. 23 is a flowchart showing the operation of the second mode according to the eighth embodiment of the present invention.
FIG. 24 is a flowchart showing the operation of the first mode in the ninth embodiment of the present invention.
FIG. 25 is a flowchart showing the operation of the second mode according to the ninth embodiment of the present invention.
FIG. 26 is a diagram showing a first form in the tenth embodiment of the present invention.
FIG. 27 is a diagram showing a second form in the tenth embodiment of the present invention.
FIG. 28 is a diagram showing a third mode in the tenth embodiment of the present invention.
FIG. 29 is a diagram more specifically showing the second embodiment (FIG. 27).
FIG. 30 is a diagram more specifically showing the third embodiment (FIG. 28).
FIG. 31 is a diagram showing an example of a user instruction in Example 11 according to the present invention.
FIG. 32 is a diagram showing another example of a user instruction according to the eleventh embodiment of the present invention.
FIG. 33 is a diagram showing a first form in the twelfth embodiment of the present invention.
FIG. 34 (a) shows a second mode of the twelfth embodiment according to the present invention, and FIG. 34 (b) shows a timing chart of the main part thereof.
[Explanation of symbols]
1 ... Digital TV broadcast receiver
2 ... Antenna
3. RF / IF processing section
4 Demodulation / separation processing unit
5. Decoder part
6 ... Freeze controller
9 ... CPU
31 ... RF-baseband processing unit
41 ... OFDM demodulation processor
42 ... TS-DEMUX processing unit
51. Video decoder
52. Audio decoder
61 ... Freeze controller
70 ... Freeze ON / OFF control unit
80 ... Packet counter
81 ... Error counter
83 ... On-time packet counter
84: Off packet counter
85 ... Error counter when on
86 ... Error counter when off
90: Packet counter set value holding unit
91: Error counter set value holding unit
95: Logic operation section

Claims (23)

An RF / IF processing unit that receives a digital television broadcast wave as an input signal, a demodulation / separation processing unit that demodulates and separates the output from the RF / IF processing unit, and a decoding process that outputs the demodulation / separation processing unit A digital television broadcast receiver comprising a decoder unit;
Based on an error signal generated according to an error condition of the input signal composed of a series of packets , at least one of a video signal, an audio signal, and a data signal sent from the decoder unit is stopped or stopped. Further includes freeze control means for performing freeze control to
Here, when the input signal is composed of a plurality of layers, the freeze control means divides the demodulated signal in the demodulation / separation processing unit for each layer and inputs the signal for each layer. A digital television broadcast receiver characterized in that the number of packets to be transmitted and the number of error signals are counted and the freeze control is executed for each layer .   The freeze control means divides the demodulated signal in the demodulation / separation processing unit into the video signal, the audio signal, and the data signal, and executes the freeze control for each of the signals. The digital television broadcast receiver according to claim 1.   2. The digital television broadcast according to claim 1, wherein the freeze control unit executes the freeze control for each of the video signal, the audio signal, and the data signal after the separation processing in the demodulation / separation processing unit. Receiving machine. 2. The digital television broadcast receiver according to claim 1 , wherein the freeze control means executes the freeze control based on the number of occurrences of the error signal per predetermined unit. The freeze control means in order to define a pre-Symbol predetermined unit, the digital television broadcast receiver according to claim 4, characterized in that it comprises a packet counter for counting the number of Rupa be sequentially incoming packets. The freeze control means detects the presence or absence of the error signal for each said packet, the digital television broadcast receiver according to claim 1, characterized in that it comprises an error counter for counting the number of said error signal.   6. The digital television broadcast reception according to claim 5, wherein the packet counter clears the counter when the count value exceeds a certain value, and newly starts counting the next incoming packet. Machine.   7. The digital television broadcast receiver according to claim 6, wherein when the error signal does not arrive, the count value of the error counter is held as it is until the count value of the packet counter exceeds a certain value.   Before the error counter count value exceeds a certain value, the freeze control state is maintained, and when the error counter count value exceeds a certain value, the freeze control is executed. The digital television broadcast receiver according to claim 6.   2. The digital television broadcast receiver according to claim 1, wherein the freeze control means turns off the freeze control that is turned on when the error signal is not detected. The freeze control means in order to define a pre-Symbol predetermined unit, and has a packet counter for counting the number of packets sequentially arriving, by detecting the presence or absence of the error signal for each said packet, of said error signal The digital television broadcast receiver according to claim 4, further comprising an error counter that counts the number.   The freeze control that is turned on is turned off when the count value of the packet counter exceeds a certain value but does not exceed a certain value. 11. A digital television broadcast receiver according to 11.   13. The digital television broadcast receiver according to claim 10, wherein when the display delay information is included in the packet, the freeze control is executed with a delay by the delay time.   The digital television broadcast receiver according to claim 13, wherein the display delay information is PTS or DTS.   14. The digital television broadcast receiver according to claim 13, wherein the freeze control is executed after a certain time has passed in place of the display delay information.   When the freeze control means does not detect an error display signal output from a control terminal of the decoder unit or an error display signal written to an internal register of the decoder unit, the freeze control unit turns off the freeze control that is turned on. The digital television broadcast receiver according to claim 1.   2. The digital television broadcast receiver according to claim 1, wherein when the display delay information is included in the packet, the freeze control is executed with a delay by the delay time. 3.   The freeze control means turns on the freeze control when detecting an error display signal output from a control terminal of the decoder unit or an error display signal written to an internal register of the decoder unit. Item 4. The digital television broadcast receiver according to Item 1.   A CPU for controlling at least the freeze control means in the digital television broadcast receiver is provided. The freeze control means executes the freeze control in response to a control signal from the CPU and is externally input to the CPU. 2. The digital television broadcast receiver according to claim 1, wherein the freeze control means is activated or deactivated by an instruction signal.   2. The digital television broadcast according to claim 1, wherein the freeze control unit performs the freeze control by supplying or stopping the input signal from the demodulation / separation processing unit to the decoder unit. Receiving machine.   2. The digital television broadcast receiver according to claim 1, wherein the freeze control means changes a criterion for determining whether or not to execute the freeze control according to a type of the video signal.   2. The digital television broadcast receiver according to claim 1, wherein the freeze control means changes a criterion for determining whether or not to execute the freeze control according to a type of the audio signal.   20. The digital television broadcast receiver according to claim 19, wherein the activation or deactivation is determined by a logical operation of the control signal from the CPU and the instruction signal to the CPU.

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