JP4085604B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a silicon carbide semiconductor device provided with a J-FET.SetIt relates to a manufacturing method.
[0002]
[Prior art]
FIG. 13 shows a cross-sectional configuration of a silicon carbide semiconductor device provided with an N-channel type J-FET. As shown in FIG. 13, the N-channel J-FET is an N-channel made of silicon carbide.⁺N on mold substrate J1^-It is formed using the substrate on which the type drift layer J2 is grown. N^-P-type first and second gate regions J3 and J4 are formed in the surface layer portion of the epitaxial layer J2 by ion implantation. Further, between the first and second gate regions J3 and J4, N^-N on the surface layer of the epitaxial layer J2⁺A mold source region J5 is formed. The first and second gate electrodes J6 and J7 are formed on the surfaces of the first and second gate regions J3 and J4, and N⁺A source electrode J8 is formed on the surface of the type source region J5, and N⁺A drain electrode J9 is formed on the back surface side of mold substrate J1, thereby forming a silicon carbide semiconductor device.
[0003]
When the J-FET having such a configuration is a normally-off type, when no voltage is applied to the first and second gate electrodes J6 and J7, the first and second gate regions J3 and J4 The first and second gate regions J3 and J4 are designed to be pinched off by the extending depletion layer. Then, the channel is formed by controlling the width of the depletion layer extending from the first and second gate regions J3 and J4, and the current is passed between the source and the drain through the channel to operate the J-FET.
[0004]
[Problems to be solved by the invention]
In the above-described conventional normally-off J-FET, it is desirable that the gate control bias can be applied to the same level as the built-in potential (gate junction diffusion voltage). However, when the built-in potential becomes smaller than the set value, if the gate applied voltage exceeds the built-in potential, the first and second gate regions J3, J4 to N^-Holes are injected into the type drift layer J2, and control by the gate becomes impossible. As a result, problems such as a decrease in recovery characteristics and an increase in leakage occur.
[0005]
When the substrate material is SiC, the theoretical value of the built-in potential is about 2.9V. There is a problem that the voltage drops to about 1 V, the theoretical value cannot be used as a design value, and desired device characteristics cannot be obtained.
[0006]
  In view of the above points, the present invention provides a silicon carbide semiconductor device capable of preventing a built-in potential from being lowered due to the influence of crystal defects and the like.SetAn object is to provide a manufacturing method.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, in the invention described in claim 1,The step of forming the plurality of recesses (3) includes a step of disposing the Poly-Si layer (45) at a predetermined position on the surface of the drift layer (2), and after thermally oxidizing the surface of the Poly-Si layer (45). The oxidized portion (46) of the Poly-Si layer (45) is removed to reduce the Poly-Si layer (45), and the reduced Poly-Si layer (45) is used as a mask. And a step of forming the recess (3) by etching.
[0018]
In this way, if the Poly-Si layer is thermally oxidized and the oxidized portion is removed, even if the Poly-Si layer cannot be patterned to a sufficiently small size, it is sufficiently small by subsequent thermal oxidation and etching. Can be reduced to size. Accordingly, it is possible to cope with so-called submicron size (0.5 to 0.7 μm), and it is possible to manufacture a finer element.
[0019]
  Claim2In the invention described in the above, in the step of forming the recess (3) and the step of forming the first and second gate regions (4, 5), the mask including the carbon layer (47) at a predetermined position of the drift layer (2). A step of disposing the material (47, 48), a step of forming the recess (3) by etching using the mask material (47, 48) as a mask, and the inside of the recess (3) using the carbon layer (47) as a mask. And a step of selectively epitaxially growing the first and second gate regions (4, 5).
[0020]
In this way, by performing epitaxial growth using the carbon layer as a mask, the first and second gate regions can be selectively epitaxially grown in the recess and not grown on the carbon layer. For this reason, by removing the carbon layer after the epitaxial growth, the first and second gate regions can be formed without performing an etch-back process. Thereby, simplification of a manufacturing process can also be achieved.
[0021]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a cross-sectional configuration of a silicon carbide semiconductor device provided with a J-FET as a first embodiment of the present invention. Hereinafter, the configuration of the silicon carbide semiconductor device will be described with reference to FIG.
[0023]
As shown in FIG. 1, the silicon carbide semiconductor device includes, for example, 1 × 10¹⁹cm^-3N with the above impurity concentration⁺Mold substrate 1, for example 1 × 10¹⁵~ 5x10¹⁶cm^-3N impurity concentration^-A type drift layer 2 is provided. These N⁺Mold substrate 1 and N^-Type drift layer 2 is made of silicon carbide, and a semiconductor substrate is constituted by these.
[0024]
N^-A plurality of recesses 3 formed at a predetermined interval Wch are formed in the surface layer portion of the type drift layer 2.⁺A first gate region 4 and a second gate region 5 made of a mold layer are epitaxially grown. These first and second gate regions 4 and 5 are, for example, 1 × 10 6.¹⁸~ 5x10¹⁹cm^-3Impurity concentration.
[0025]
N^-A portion of the type drift layer 2 located between the first and second gate regions 4 and 5 is defined as a channel region 6, and an N-type source region 7 is epitaxially grown on the surface of the channel region 6. This N-type source region 7 is provided with a gradient so that the impurity concentration increases in order from the surface of the channel region 6, and the portion in contact with the first and second gate regions 4, 5 has a low concentration. Has been. Specifically, the N-type source region 7 is substantially N on the channel region 6 side.^-The impurity concentration is the same as that of the type drift layer 2, and the side opposite to the channel region 6 is, for example, 1 × 10¹⁸~ 5x10²⁰cm^-3Impurity concentration.
[0026]
In addition, first and second gate electrodes 8 and 9 are formed on the surfaces of the first and second gate regions 4 and 5, respectively, and a source electrode 10 is formed on the surface of the N-type source region 7. The second gate electrodes 8 and 9 and the N-type source region 7 are electrically separated by an interlayer insulating film 11. And N⁺A drain electrode 12 is formed on the back surface side of the mold substrate 1 to constitute the silicon carbide semiconductor device shown in FIG.
[0027]
The J-FET configured in this way operates normally off. This operation differs depending on the connection mode of the first and second gate electrodes 8 and 9, and is performed as follows.
[0028]
(1) When the potentials of the first gate electrode 8 and the second gate electrode 9 are controllable, the first and second gate regions 4 are based on the potentials of the first and second gate electrodes 8 and 9. Double gate drive is performed to control the amount of extension of the depletion layer extending from both sides to the channel region 6 side. For example, when no voltage is applied to the first and second gate electrodes 8 and 9, the channel region 6 is pinched off by a depletion layer extending from both the first and second gate regions 4 and 5. Thereby, the source-drain current is turned off. When a forward bias is applied between the first and second gate regions 4 and 5 and the channel region 6, the amount of depletion layer extending to the channel region 6 is reduced. Thereby, a channel is set and a current flows between the source and the drain.
[0029]
(2) In the case where only the potential of the first gate electrode 8 can be controlled independently and the potential of the second gate electrode 9 is the same as that of the source electrode 10, for example, the potential of the first gate electrode 8 Based on the above, single gate driving is performed to control the extension amount of the depletion layer extending from the first gate region 4 side to the channel region 6 side. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the first gate region 4 side.
[0030]
(3) In the case where only the potential of the second gate electrode 9 can be controlled independently and the potential of the first gate electrode 8 is the same potential as the source electrode 10, for example, the potential of the second gate electrode 9 Based on the above, single gate driving is performed to control the amount of extension of the depletion layer extending from the second gate region 5 side to the channel region 6 side. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the second gate region 5 side.
[0031]
Next, a method for manufacturing the silicon carbide semiconductor device shown in FIG. 1 will be described with reference to the manufacturing process of the silicon carbide semiconductor device shown in FIG.
First, in the process shown in FIG.⁺A mold substrate 1 is prepared.⁺N on the surface of the mold substrate 1^-A type drift layer 2 is formed. Thereafter, in the step shown in FIG.^-After the LTO film 20 is formed on the surface of the type drift layer 2, a portion corresponding to the formation position of the first and second gate regions 4 and 5 in the LTO film 20 is opened by photolithography.
[0032]
Next, in the step shown in FIG. 2C, the surface layer portion of the N − -type drift layer 2 is etched using the LTO film 20 as a mask. As a result, the recess 3 is formed at a position where the first and second gate regions 4 and 5 are to be formed. Thereafter, sacrificial oxidation is performed as necessary, and the oxide film formed at the time of sacrificial oxidation together with the LTO film 20 is removed. In the step shown in FIG. 2D, P is formed on the substrate surface so as to embed the recess 3.⁺After the mold layer is epitaxially grown, the etch back is performed by CMP (Chemical Mechanical Polishing), for example.⁺The mold layer is planarized to form first and second gate regions 4 and 5.
[0033]
2E, after removing the mask material 20, the N-type source region 7 is epitaxially grown. At this time, by changing the atmosphere during the epitaxial growth as appropriate, the N-type source region 7 is provided with a gradient so that the impurity concentration becomes higher in order from the surface of the channel region 6. The portion in contact with the regions 4 and 5 is set to have a low concentration. Thereafter, unnecessary portions of the N-type source region 7 are removed by photoetching.
[0034]
Further, in the step shown in FIG. 2F, after forming the interlayer insulating film 11 on the substrate surface, a contact hole is formed in the interlayer insulating film 11 by photoetching. Thereafter, an electrode layer is formed on the interlayer insulating film 11 and then patterned to form the first and second gate electrodes 8 and 9 and the source electrode 10. And N⁺After forming the drain electrode 12 on the back side of the mold substrate 1, a semiconductor device shown in FIG. 1 is completed through a sintering process.
[0035]
As described above, in the present embodiment, the first and second gate regions 4 and 5 and the N-type source region 7 are formed by epitaxial growth. For this reason, it is easy to control the distance between the first and second gate regions 4 and 5. In addition, crystal defects in the first and second gate regions 4 and 5 can be suppressed, and the built-in potential can be prevented from lowering than the theoretical value.
[0036]
In addition, since the impurity concentration of the N-type source region 7 is controlled to be thin at the beginning of growth and to be high at the end of growth, the impurity concentration portion and the first and second gate regions 4 and 5 It can be configured such that a portion with a low impurity concentration is disposed between them. For this reason, the gate breakdown voltage can be improved as compared with the case where a high concentration PN junction is formed.
[0037]
(Second Embodiment)
In FIG. 3, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in 2nd Embodiment of this invention is shown. Hereinafter, the configuration of the silicon carbide semiconductor device of the present embodiment will be described with reference to FIG. 3, but since the basic configuration is the same as that of the first embodiment, only the portions different from the first embodiment will be described.
[0038]
As shown in FIG. 3, in the present embodiment, the N-type source region 7 is not selectively etched for contact with the first and second gate regions 4 and 5, and is provided with a J-FET. In the outer periphery of the cell portion, the first and second gate regions 4 and 5 are configured to be electrically connected to the outside.
[0039]
A method for manufacturing such a silicon carbide semiconductor device will be described with reference to the manufacturing process shown in FIG. In FIG. 4, the left side of the drawing shows the cross-sectional configuration of the J-FET, and the right side of the drawing shows the cross-sectional configuration of the outer peripheral portion of the cell portion. Moreover, since this manufacturing process is basically the same as that of the first embodiment, only the parts different from the first embodiment are shown.
[0040]
First, steps similar to those in FIGS. 2A to 2D in the first embodiment are performed, and N^-First and second gate regions 4 and 5 are formed in the surface layer portion of the type drift layer 2 by epitaxial growth. Then, the process shown in FIG. 4 is performed. First, in the step shown in FIG. 4A, an N-type source region 7 is formed on the substrate surface. The formation conditions of the N-type source region 7 at this time are the same as those in the first embodiment. Then, the part located in the outer peripheral part of a cell part among N type source regions 7 is opened by photoetching. Thereby, the site | part extended to the outer peripheral part of the cell part among the 1st, 2nd gate area | regions 4 and 5 is exposed.
[0041]
4B, after forming an electrode layer on the substrate surface, patterning is performed to form the first and second gate electrodes 8 and 9, and the source electrode 10 is formed. Thereby, the source electrode 10 is formed in the cell part provided with the J-FET, and the first and second gate electrodes 8 and 9 are formed in the outer peripheral part of the cell part. And N⁺After forming the drain electrode 12 on the back side of the mold substrate 1, a semiconductor device shown in FIG. 1 is completed through a sintering process.
[0042]
In this way, the contact between the first and second gate regions 4 and 5 can be made at the outer peripheral portion of the cell portion. In this case, it is not necessary to pattern the N-type source region 7 in the cell portion, and the layout of the first and second gate electrodes 8 and 9 and the source electrode 10 can be simplified. A structure that is advantageous in reducing the element size can be obtained.
[0043]
(Third embodiment)
FIG. 5 shows a cross-sectional configuration of a silicon carbide semiconductor device provided with a J-FET in the third embodiment of the present invention. Hereinafter, the configuration of the silicon carbide semiconductor device of the present embodiment will be described with reference to FIG. 5, but since the basic configuration is the same as that of the second embodiment, only the portions different from the second embodiment will be described.
[0044]
As shown in FIG. 5, in this embodiment, the N-type source region 7 is arranged between the first and second gate regions 4 and 5, and the impurity concentration in the N-type source region 7 is The channel region 6 is formed by the lowered portion. In the portion located between the first and second gate regions 4 and 5, the portion of the N-type source region 7 where the impurity concentration is high is formed deeply.
[0045]
A method for manufacturing such a silicon carbide semiconductor device will be described with reference to the manufacturing process shown in FIG.
[0046]
First, in the process shown in FIG.⁺N on the surface of the mold substrate 1^-Type drift layer 2, P⁺After the epitaxial growth of the mold layer 31 in order, P⁺An LTO film 32 is formed on the surface of the mold layer 31. Then, after depositing a resist 33 on the LTO film 32, the LTO film 32 is patterned by photo-etching to open a position where the channel region 6 is to be formed.
[0047]
Thereafter, in the step shown in FIG. 6B, after the resist 33 is removed, etching using the LTO film 32 as a mask is performed.⁺The mold layer 31 is patterned to form the first and second gate regions 4 and 5. In the step shown in FIG. 6C, sacrificial oxidation is performed as necessary, and then the LTO film 32 is removed, and the N-type source region 7 is epitaxially grown on the substrate surface. The formation conditions of the N-type source region 7 at this time may be the same as those in the first embodiment, and the film-forming conditions are such that the entire region that becomes the channel region 6 in the N-type source region 7 has a low concentration. Also good. Then, after planarizing the N-type source region 7 by CMP etch back, the first and second gate electrodes 8 and 9 are formed in the outer peripheral portion of the cell portion, and the source electrode 10 is formed in the cell portion. N⁺The drain electrode 12 is formed on the back side of the mold substrate 1 and subjected to sintering treatment, thereby completing the silicon carbide semiconductor device of this embodiment shown in FIG.
[0048]
According to such a manufacturing method, since the first and second gate regions 4 and 5 are formed by epitaxial growth, the formation of crystal defects can be prevented, and the same effect as in the first embodiment can be obtained. Can do. Also, epitaxially grown P⁺Since the space between the first and second gate regions 4 and 5 is set by patterning the mold layer 31, it is possible to easily control the space.
[0049]
Furthermore, since the portion where the impurity concentration is high in the N-type source region 7 is formed to a deep position, the resistance value at this portion can be reduced, and as a result, the on-resistance can be reduced. Can do.
[0050]
In the present embodiment, the case where the first and second gate electrodes 8 and 9 are formed on the outer peripheral portion of the cell portion has been described. Of course, the first and second gate electrodes 8 and 9 may be formed on the cell portion as in the first embodiment. good.
[0051]
(Fourth embodiment)
In FIG. 7, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in 4th Embodiment of this invention is shown. Hereinafter, the configuration of the silicon carbide semiconductor device of the present embodiment will be described based on FIG. 7, but the basic configuration is the same as that of the first embodiment, and therefore only the portions different from those of the first embodiment will be described.
[0052]
As shown in FIG. 7, the first and second gate regions 4, 5 and N^-N on the surface of the drift layer 2^-A mold layer (first conductivity type layer) 40 is formed, and this N^-An N-type source region 7 is formed in the surface layer portion of the mold layer 40, and an N-type source region 7 is formed between the N-type source region 7 and the first and second gate regions 4 and 5.^-The mold layer 40 is arranged. And N^-The mold layer 40 includes P that connects the first gate region 4 and the first gate electrode 8.⁺P connecting the first contact region 41 of the mold, the second gate region 5 and the second gate electrode 9⁺The second contact region 42 of the mold is formed.
[0053]
A method for manufacturing such a silicon carbide semiconductor device will be described with reference to the manufacturing process shown in FIG. Since this manufacturing process is basically the same as that of the first embodiment, only the parts different from the first embodiment are shown.
[0054]
First, the steps shown in FIGS. 2A to 2D of the first embodiment are performed, and N^-First and second gate regions 4 and 5 are formed in the surface layer portion of the type drift layer 2. Thereafter, in the step shown in FIG. 8A, N including the first and second gate regions 4 and 5 is formed.^-N on the surface of the type drift layer 2 by epitaxial growth^-A mold layer 40 is formed.
[0055]
Next, in the step shown in FIG.^-After forming the LTO film 43 on the surface of the mold layer 40, the LTO film 43 is patterned by photolithography, and a predetermined position of the LTO film 43 is opened. Thereafter, ion implantation is performed using the LTO film 43 as a mask, and N^-An N-type source region 7 is formed in the surface layer portion of the mold layer 40.
[0056]
8C, after removing the LTO film 43, the LTO film 44 is formed again, and the LTO film 44 is patterned by photolithography to open a predetermined position of the LTO film 44. . Thereafter, ion implantation is performed using the LTO film 44 as a mask, and N^-P connected to the mold layer 40 with the first and second gate regions 4 and 5⁺First and second contact regions 41 and 42 of the mold are formed. Then, in the process shown in FIG. 8D, the same process as in FIG. 2F in the first embodiment is performed to form the interlayer insulating film 11, the first and second gate electrodes 8, 9, and the source electrode 10. At the same time, the drain electrode 12 is formed and through a sintering process, the silicon carbide semiconductor device shown in FIG. 7 is completed.
[0057]
According to such a manufacturing method, since the first and second gate regions 4 and 5 are formed by epitaxial growth, the formation of crystal defects can be prevented, and the same effect as in the first embodiment can be obtained. Can do.
[0058]
Also, N between the N-type source region 7 and the first and second gate regions 4 and 5^-Since the mold layer 40 is sandwiched, the gate breakdown voltage can be improved as compared with the case where a high concentration PN junction is formed. In this way, N^-Since the mold layer 40 is sandwiched, in the case of this embodiment, the N-type source region 7 may be configured to have a high concentration throughout.
[0059]
(Fifth embodiment)
This embodiment employs a manufacturing method different from that in FIG. 8 in the structure of the fourth embodiment. In FIG. 9, the manufacturing process of the silicon carbide semiconductor device in this embodiment is shown. Since this manufacturing process is basically the same as that of the fourth embodiment, only the parts different from the fourth embodiment will be shown with reference to the first and fourth embodiments.
[0060]
First, the same process as in FIG. 2A in the first embodiment is performed, and N⁺N on the surface of the mold substrate 1^-A type drift layer 2 is formed. In the step shown in FIG.^-After forming the Poly-Si layer 45 on the surface of the mold drift layer 2, patterning is performed to leave the Poly-Si layer 45 at a predetermined position.
[0061]
Next, in the step shown in FIG. 9B, after the surface of the Poly-Si layer 45 is thermally oxidized, the oxidized portion 46 is etched. Thereby, the Poly-Si layer 45 is isotropically removed, and the line width of the Poly-Si layer 45 is reduced. In the step shown in FIG. 9C, etching is performed using the Poly-Si layer 45 as a mask to form the recesses 3 at the positions where the first and second gate regions 4 and 5 are to be formed. Thereafter, the first and second gate regions 4 and 5 are epitaxially grown in the recess 3 and then the steps of FIGS. 8A to 8D shown in the fourth embodiment are performed, thereby obtaining a silicon carbide semiconductor. The device is completed.
[0062]
Thus, after the poly-Si layer 45 once patterned is thermally oxidized, the oxidized portion 46 is etched, so that the dimensions of the poly-Si layer 45 can be reduced by the amount of thermal oxidation. For this reason, even if the Poly-Si layer 45 cannot be patterned to a sufficiently small size, it can be reduced to a sufficiently small size by subsequent thermal oxidation and etching. Thereby, not only the same effects as those of the fourth embodiment can be obtained, but also so-called submicron size (0.5 to 0.7 μm) can be handled, and a finer element can be manufactured.
[0063]
This embodiment is applicable not only to the structure of the fourth embodiment but also to the configurations of the first and second embodiments, and can obtain the same effects as those of the first and second embodiments. Is possible.
[0064]
(Sixth embodiment)
This embodiment also employs a manufacturing method different from that in FIG. 8 in the structure of the fourth embodiment. In FIG. 10, the manufacturing process of the silicon carbide semiconductor device in this embodiment is shown. Since this manufacturing process is basically the same as that of the fourth embodiment, only the parts different from the fourth embodiment will be shown with reference to the first and fourth embodiments.
[0065]
  First, the same process as in FIG. 2A in the first embodiment is performed, and N⁺N on the surface of the mold substrate 1^-A type drift layer 2 is formed. In the step shown in FIG.^-After forming the carbon layer 47 on the surface of the type drift layer 2,LTOLayer 48 is deposited. Then, after patterning the LTO film 48 by photolithography and leaving it at a predetermined position, the carbon layer 47 is patterned using the LTO film 48 as a mask.
[0066]
Next, in the step shown in FIG. 9B, etching is performed in a state where the LTO film 48 and the carbon layer 47 are used as a mask to form the recesses 3 at the positions where the first and second gate regions 4 and 5 are to be formed. Further, after removing the LTO film 48, the first and second gate regions 4 and 5 are epitaxially grown in the recess 3 using the carbon layer 47 as a mask. In this way, the first and second gate regions 4 and 5 can be selectively epitaxially grown only in the recess 3. Thereafter, the steps of FIGS. 8A to 8D shown in the fourth embodiment are performed to complete the silicon carbide semiconductor device.
[0067]
As described above, by performing epitaxial growth using the carbon layer 47 as a mask, the first and second gate regions 4 and 5 can be selectively epitaxially grown in the recess 3 and not grown on the carbon layer 47. . For this reason, by removing the carbon layer 47 after epitaxial growth, the first and second gate regions 4 and 5 can be formed without performing an etch-back process. Thereby, not only the same effect as the fourth embodiment can be obtained, but also the manufacturing process can be simplified.
[0068]
This embodiment is applicable not only to the structure of the fourth embodiment but also to the configurations of the first and second embodiments, and can obtain the same effects as those of the first and second embodiments. Is possible.
[0069]
(Seventh embodiment)
In FIG. 11, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in 7th Embodiment of this invention is shown. Hereinafter, the configuration of the silicon carbide semiconductor device of the present embodiment will be described with reference to FIG. 11. However, since the basic configuration is the same as that of the fourth embodiment, only the portions different from the fourth embodiment will be described.
[0070]
As shown in FIG. 11, P constituting the first and second gate regions 4 and 5⁺The mold layer (second conductivity type semiconductor layer) 50 is N^-Formed on the entire surface of the drift layer 2 and P⁺By implanting ions into the mold layer 50, the N-type source region 7 and the P⁺The first and second contact regions 41 and 42 of the mold are formed.
[0071]
A method for manufacturing such a silicon carbide semiconductor device will be described with reference to the manufacturing process shown in FIG. In addition, also about this manufacturing process, 1st Embodiment is referred and only the part different from 1st Embodiment is shown.
[0072]
First, the steps shown in FIGS. 2A to 2C of the first embodiment are performed, and N^-A recess 3 is formed in the mold drift layer 2. Then, in the step shown in FIG.⁺The mold layer 50 is epitaxially grown, and then P is formed by CMP.⁺The surface of the mold layer 50 is flattened. At this time, P also on the channel region 6⁺Planarization is performed so that the mold layer 50 remains.
[0073]
Next, in the step shown in FIG.⁺After forming the LTO film 51 on the surface of the mold layer 50, the LTO film 51 is patterned by photolithography, and a predetermined position of the LTO film 51 is opened. Thereafter, ion implantation is performed using the LTO film 51 as a mask to form the N-type source region 7. As a result, the N-type source region 7 causes P⁺The mold layer 50 is divided to form first and second gate regions 4 and 5. At this time, the N-type source region 7 is in contact with the channel region 6.
[0074]
Subsequently, in the step shown in FIG. 12C, after removing the LTO film 51, the LTO film 52 is formed again, and the LTO film 52 is patterned by photolithography to open a predetermined position of the LTO film 52. . Thereafter, ion implantation is performed using the LTO film 52 as a mask, and P⁺P connected to the mold layer 50 with the first and second gate regions 4 and 5⁺First and second contact regions 41 and 42 of the mold are formed. Then, in the process shown in FIG. 12D, the same process as in FIG. 2F in the first embodiment is performed to form the interlayer insulating film 11, the first and second gate electrodes 8, 9 and the source electrode 10. At the same time, the drain electrode 12 is formed, and through the sintering process, the silicon carbide semiconductor device shown in FIG. 9 is completed.
[0075]
According to such a manufacturing method, since the first and second gate regions 4 and 5 are formed by epitaxial growth, the formation of crystal defects can be prevented, and the same effect as in the first embodiment can be obtained. Can do. P⁺It is only necessary to epitaxially grow the mold layer 50, and P⁺It is not necessary to form another layer on the mold layer 50, and the manufacturing process can be simplified.
[0076]
(Other embodiments)
In each of the above embodiments, N^-Although the silicon carbide semiconductor device provided with the J-FET in which the N-type impurity layer called the channel channel layer 8 serves as a channel has been described, the P-type impurity layer in which the conductivity type of each component of the silicon carbide semiconductor device is inverted The present invention can also be applied to a silicon carbide semiconductor device provided with a J-FET.
[0077]
In the above embodiment, a normally-off type J-FET has been described as an example. However, the present invention is not limited to a normally-off type J-FET, and is also applicable to a normally-on type J-FET. In this case, for example, N^-The impurity concentration of the type channel layer 8 is 5 × 10¹⁶~ 1x10¹⁷cm^-3It can also be a degree.
[Brief description of the drawings]
1 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
2 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 1. FIG.
FIG. 3 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device in a second embodiment of the present invention.
4 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 3. FIG.
FIG. 5 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device in a third embodiment of the present invention.
6 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 5. FIG.
FIG. 7 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device in a fourth embodiment of the present invention.
8 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 7. FIG.
FIG. 9 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the fifth embodiment of the present invention.
FIG. 10 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the sixth embodiment of the present invention.
FIG. 11 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device in a seventh embodiment of the present invention.
12 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 11. FIG.
FIG. 13 is a diagram showing a cross-sectional configuration of a conventional silicon carbide semiconductor device.
[Explanation of symbols]
1 ... N⁺Mold substrate, 2 ... N^-Type drift layer, 3... Recess, 4, 5... First and second gate regions, 6... Channel region, 7... N-type source region, 8 and 9. ... interlayer insulating film, 12 ... drain electrode.

Claims (3)

Preparing a substrate (1) made of silicon carbide of the first conductivity type;
Forming a first conductivity type drift layer (2) made of silicon carbide having a lower concentration than the substrate (1) on the substrate (1);
Forming a plurality of concave portions (3) in the surface layer portion in the drift layer (2) so as to be separated from each other;
After epitaxially growing a second conductivity type semiconductor layer on the drift layer (2) including the inside of the recess (3), the semiconductor layer is planarized to thereby separate the first conductivity type first, Forming a second gate region (4, 5);
Epitaxially growing a first conductivity type layer (40) made of silicon carbide on the drift layer (2) including the first and second gate regions (4, 5);
When a portion sandwiched between the first and second gate regions (4, 5) in the drift layer (2) is a channel region (6), the surface layer portion in the first conductivity type layer (40) Forming a source region (7) of the first conductivity type having a higher concentration than the first conductivity type layer (40) in a portion located on the channel region (6);
A first contact region (41) of a second conductivity type connected to the first gate region (4) and a first contact region (41) connected to the second gate region (5) are connected to the first conductivity type layer (40). Forming a second conductivity type second contact region (42);
A first gate electrode (8) electrically connected to the first gate region (4) via the first contact region (41); and the second gate region via the second contact region (42). Forming a second gate electrode (9) electrically connected to (5) and a source electrode (10) electrically connected to the source region (7);
Possess and forming a drain electrode (12) on the back side of the substrate (1),
In the step of forming the plurality of recesses (3),
Disposing a Poly-Si layer (45) at a predetermined position on the surface of the drift layer (2);
A step of thermally oxidizing the surface of the Poly-Si layer (45), removing an oxidized portion (46) of the Poly-Si layer (45), and reducing the size of the Poly-Si layer (45); ,
And a step of forming the recess (3) by etching using the reduced Poly-Si layer (45) as a mask . Preparing a substrate (1) made of silicon carbide of the first conductivity type;
Forming a first conductivity type drift layer (2) made of silicon carbide having a lower concentration than the substrate (1) on the substrate (1);
Forming a plurality of concave portions (3) in the surface layer portion in the drift layer (2) so as to be separated from each other;
After epitaxially growing a second conductivity type semiconductor layer on the drift layer (2) including the inside of the recess (3), the semiconductor layer is planarized to thereby separate the first conductivity type first, Forming a second gate region (4, 5);
Epitaxially growing a first conductivity type layer (40) made of silicon carbide on the drift layer (2) including the first and second gate regions (4, 5);
When a portion sandwiched between the first and second gate regions (4, 5) in the drift layer (2) is a channel region (6), the surface layer portion in the first conductivity type layer (40) Forming a source region (7) of the first conductivity type having a higher concentration than the first conductivity type layer (40) in a portion located on the channel region (6);
A first contact region (41) of a second conductivity type connected to the first gate region (4) and a first contact region (41) connected to the second gate region (5) are connected to the first conductivity type layer (40). Forming a second conductivity type second contact region (42);
A first gate electrode (8) electrically connected to the first gate region (4) via the first contact region (41); and the second gate region via the second contact region (42). Forming a second gate electrode (9) electrically connected to (5) and a source electrode (10) electrically connected to the source region (7);
Possess and forming a drain electrode (12) on the back side of the substrate (1),
In the step of forming the recess (3) and the step of forming the first and second gate regions (4, 5),
Disposing a carbon layer (47) and a mask material (47) including an LTO film (48) formed on the carbon layer (47) at a predetermined position of the drift layer (2);
Forming the recess (3) by etching using the mask material (47, 48) as a mask;
Removing the LTO film (48);
A step of selectively epitaxially growing the first and second gate regions (4, 5) in the recess (3) using the carbon layer (47) as a mask. Device manufacturing method. Preparing a substrate (1) made of silicon carbide of the first conductivity type;
Forming a first conductivity type drift layer (2) made of silicon carbide having a lower concentration than the substrate (1) on the substrate (1);
Forming a plurality of recesses (3) in the surface layer portion in the drift layer (2) so as to be separated from each other;
Epitaxially growing a second conductivity type semiconductor layer (50) on the drift layer (2) including inside the recess (3);
When a portion of the drift layer (2) sandwiched between the plurality of recesses (3) is defined as a channel region (6), a portion of the semiconductor layer (50) located above the channel region (6) A first conductivity type source region (7) having a concentration higher than that of the drift layer (2) is formed, and the semiconductor layer (50) is divided by the source region (7), so that a second conductivity type first region is formed. Forming the second gate region (4, 5);
A second conductive type first contact region (41) is formed in the first and second gate regions (4, 5), and a second conductive type second contact region (4) is formed in the second gate region (5). 42) forming,
A first gate electrode (8) electrically connected to the first gate region (4) via the first contact region (41); and the second gate region via the second contact region (42). Forming a second gate electrode (9) electrically connected to (5) and a source electrode (10) electrically connected to the source region (7);
Forming a drain electrode (12) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising:

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