JP4089752B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device such as a light emitting diode (LED) using a gallium nitride (GaN) -based compound semiconductor, a semiconductor laser, or a semiconductor device, and particularly to a semiconductor device such as a semiconductor device. The present invention relates to a method for manufacturing a semiconductor device capable of satisfactorily forming a p-type GaN-based compound semiconductor layer with a low resistance.

Blue semiconductor light emitting devices (blue LEDs, blue lasers, etc.) using GaN-based compound semiconductors such as GaN, GaAlN, InGaN, InGaAlN and the like are known. This type of semiconductor light emitting device is generally a GaN-based compound semiconductor represented by Ga _x Al _1-x N (where 0 ≦ x ≦ 1) on an insulating substrate made of sapphire (Al ₂ O ₃ ). The layer is deposited by a known vapor phase epitaxial growth method or the like.

  That is, as shown in FIG. 5, a conventional semiconductor light emitting device of this type has a buffer layer made of a GaN-based compound semiconductor layer on one main surface (upper surface) of an insulating substrate 11 made of sapphire or the like by a vapor phase epitaxial growth method. 12, an n-type cladding layer 63 made of a GaN-based compound semiconductor layer formed on the buffer layer 12, and an active layer made of a GaN-based compound semiconductor layer formed on the n-type cladding layer 63 by a vapor phase epitaxial growth method A semiconductor laminated structure comprising a layer 64 and a p-type cladding layer 65 made of a GaN-based compound semiconductor layer formed on the active layer 64 is deposited. Further, an anode electrode 19 is formed on the p-type cladding layer 65 exposed on one main surface (upper surface) of the semiconductor multilayer structure. As shown in the figure, a notch is formed in part of the p-type cladding layer 65 and the active layer 64, and a part of the upper surface of the n-type cladding layer 63 is exposed at the bottom of the notch. The cathode electrode 18 is electrically connected to the n-type cladding layer 63 exposed at the bottom of the notch.

  A similar semiconductor multilayer structure is deposited on a low-resistance substrate made of silicon carbide (SiC) or the like instead of the sapphire substrate 11, and an anode electrode 19 and a cathode electrode are respectively formed on the uppermost surface and the lowermost surface of the semiconductor multilayer structure. A semiconductor light emitting device in which 18 is formed is also known. According to this semiconductor light emitting device, current can flow in the vertical direction of the semiconductor multilayer structure, and it is not necessary to form a notch in the semiconductor multilayer structure as in the semiconductor light emitting device described above.

  In the semiconductor light emitting device described above, the GaN-based compound semiconductor layer formed on the upper surface of the insulating substrate or the low-resistance substrate is formed by a well-known MOCVD (organic metal compound vapor phase epitaxy) method or MBE (molecular beam epitaxy) method. And so on. In addition, since it is difficult to form a good quality film by the MBE method, it is generally formed by the MOCVD method. Here, in order to make the semiconductor layer have a specific conductivity type (n-type or p-type), it is necessary to introduce an impurity for determining the conductivity type into the semiconductor layer. In a GaN-based compound semiconductor, n Silicon (Si) is usually used as the type impurity, and magnesium (Mg) or zinc (Zn) is usually used as the p-type impurity. Of course, other impurities may be used.

  Conventionally, a problem with this type of semiconductor light emitting device manufacturing method is that a p-type GaN-based compound semiconductor layer cannot be satisfactorily formed even by such MOCVD. That is, in order to form a p-type GaN compound semiconductor layer, Mg or Zn as a p-type impurity is introduced when the semiconductor layer is vapor-phase epitaxially grown by the MOCVD method or the like as described above. Even if a p-type impurity is introduced into the film, it does not become a low-resistance p-type GaN compound semiconductor layer, and the formed film becomes a high-resistance semiconductor layer exhibiting a considerably high resistance value.

  As a means for solving this problem, a method (first prior art) in which the resistance value is lowered by irradiating an electron beam to the high-resistance semiconductor layer formed as described above is publicly known. (See, for example, Non-Patent Document 1).

  Also, a method (second prior art) for reducing the resistance of a semiconductor layer by performing a heat treatment in an atmosphere not containing hydrogen gas instead of irradiating an electron beam to the high resistance semiconductor layer has been announced (second prior art). For example, see Patent Literature or Non-Patent Literature 2). This method is advantageous in terms of productivity as compared with the case of electron beam irradiation, and is expected to be put to practical use.

Further, Patent Document 2, the n-type semiconductor layer on the p-type _Al x _{Ga 1-x} N compound semiconductor layer is formed by vapor phase growth, a p-type in n-type semiconductor layer _Al x _{Ga 1-} A technique for obtaining a low-resistance p-type GaN-based compound semiconductor layer by stopping the gas supply and cooling the substrate from the growth temperature in a state where the _xN- based compound semiconductor layer is covered (third conventional technique) It is shown. The inventors who proposed this third prior art say that the reason for the low resistance of the p-type semiconductor layer is unknown. However, according to the third prior art, it is possible to avoid the need for annealing treatment and electron beam irradiation after vapor phase growth.
JP-A-5-183189 JP-A-8-8460 Amano et al .: Japanese Journal of Applied Physics, Vol. 28, pages L2212 to L2214 Nakamura et al .: Japanese Journal of Applied Physics, Vol. 31, pp. 1258 to 1266

  However, the first conventional technique is not desirable in terms of productivity because it is necessary to scan the entire semiconductor wafer with an electron beam even if the resistance of the semiconductor layer can be reduced.

  In the second prior art, it is necessary to switch the atmosphere in the growth chamber to an atmosphere not containing hydrogen gas, and the valve operation and the like are complicated. Further, compared with hydrogen gas, nitrogen and the like are difficult to be purified in terms of gas purification technology, and there is a problem of contamination from atmospheric gas. Further, when the atmosphere in the growth chamber is switched to nitrogen gas, since nitrogen has a lower thermal conductivity than hydrogen gas, the temperature distribution in the growth chamber changes. For this reason, by switching the gas, the temperature in the growth chamber temporarily rises, and there is a disadvantage that impurities from the deposits inside the growth chamber are re-evaporated and mixed into the semiconductor film formed on the insulating substrate. .

  According to the third prior art, the n-type semiconductor layer that does not contribute to the operation of the target device (semiconductor device) is formed. Therefore, finally, the n-type semiconductor layer that does not contribute to the operation is removed by a technique such as reactive ion etching (RIE) to expose the p-type semiconductor layer, and further, the electrode is formed on the exposed p-type semiconductor layer. The process of providing is necessary. In other words, the process of depositing a semiconductor layer that is not essential as the final structure of the target device (semiconductor device) and the process of removing this non-essential semiconductor layer are added and the number of processes is increased. There was a problem.

  Accordingly, the present invention provides a new method for manufacturing a semiconductor device with good productivity by forming a p-type GaN-based compound semiconductor layer satisfactorily and using the good p-type GaN-based compound semiconductor layer. Objective.

  That is, an object of the present invention is to provide a method for manufacturing a GaN-based compound semiconductor device in which the activation rate of acceptor impurities is high and a high carrier density can be easily obtained.

  Another object of the present invention is to reduce the temperature in the growth chamber while maintaining an atmosphere containing hydrogen gas used as a carrier gas during epitaxial growth, simplify the work procedure, and increase the activation rate of acceptor impurities. Then, it is providing the manufacturing method of the GaN-type compound semiconductor device which can implement | achieve a high carrier density.

  Still another object of the present invention is to provide a GaN-based compound semiconductor device in which hydrogen gas that can be purified with high purity is consistently used for epitaxial growth, impurity contamination is kept low, and the activation rate of acceptor impurities is high. It is to provide a manufacturing method.

  Still another object of the present invention is to avoid a temporary increase in the temperature in the growth chamber by switching the gas, and during the gas switching, deposits (impurities) from the growth chamber are contaminated by re-evaporation. Another object of the present invention is to provide a method of manufacturing a GaN-based compound semiconductor device that prevents the nation and has a high activation rate of acceptor impurities.

  Still another object of the present invention is to provide a method for manufacturing a GaN-based compound semiconductor device having excellent optical characteristics and electrical characteristics.

  Still another object of the present invention is a simple process without adding an extra step of depositing an extra semiconductor layer that is not essential as a final structure of a semiconductor device or an extra step of removing the nonessential semiconductor layer. An object of the present invention is to provide a method for manufacturing a GaN-based compound semiconductor device capable of increasing the acceptor impurity activation rate and realizing a high carrier density.

  Still another object of the present invention is to provide a method for manufacturing a GaN-based compound semiconductor device having a low manufacturing process and a high yield.

In order to achieve the above object, the present invention provides (a) a p-type GaN compound semiconductor layer by epitaxial growth while introducing a p-type dopant gas in an atmosphere containing hydrogen gas at a first substrate temperature. And (b) a forbidden band width by epitaxial growth on the p-type GaN compound semiconductor layer while introducing an n-type dopant gas in an atmosphere containing hydrogen gas at a second substrate temperature. Depositing an n-type GaN-based compound semiconductor layer smaller than the p-type gallium nitride-based compound semiconductor layer, and (c) in an atmosphere containing hydrogen gas, lower than the first and second substrate temperatures and atoms A step of cooling to a third substrate temperature existing in a temperature range in which gaseous hydrogen is dissolved in the p-type GaN-based compound semiconductor layer, and (d) in contact with the n-type GaN-based compound semiconductor layer. Is that it is a manufacturing method of a semiconductor device having at least a step of depositing a metal thin film. Here, the “n-type dopant gas” is a compound gas containing silicon (Si) such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or diethyl selenium (DESe), diethyl tellurium (DETe), or the like. This applies to compound gases containing Group VI elements. The “p-type dopant gas” corresponds to a compound gas containing a Group II element such as dimethylzinc (DMZ) or biscyclopentadienyl magnesium (Cp ₂ Mg). In addition, the “temperature range in which atomic hydrogen is dissolved in the p-type GaN compound semiconductor layer” is a temperature range corresponding to a “dissolution stabilization temperature” described later, and this temperature range is, for example, in the case of GaN. The temperature is about 800 ° C. or lower.

  According to the present invention, in a state where the surface of the p-type GaN-based compound semiconductor layer is covered with the n-type GaN-based compound semiconductor layer, from the second substrate temperature which is a growth temperature higher than the “solution stabilization temperature”, Since the substrate is cooled to a third substrate temperature lower than the “solution stabilization temperature”, even if the substrate is cooled in an atmosphere containing hydrogen gas, atomic hydrogen is converted into p-type GaN in the process of decreasing the substrate temperature. It is possible to effectively prevent the compound compound semiconductor layer from being melted. As a result, the atomic hydrogen is prevented from stably existing in the p-type GaN compound semiconductor layer, the activation rate of the p-type impurity element (acceptor element) is improved, and the resistivity (specific resistance) is low. A p-type GaN-based compound semiconductor layer is obtained.

Further, according to the present invention, the temperature in the growth chamber can be lowered in the atmosphere containing the hydrogen gas used as the carrier gas during the epitaxial growth. That is, it is not necessary to switch the atmosphere gas in the growth chamber to a gas not containing hydrogen gas, and the operation procedure such as valve operation can be simplified. Further, since hydrogen gas can be purified with higher purity than nitrogen (N ₂ ) gas or the like, there is an advantage that contamination with impurities can be suppressed to a lower level. Further, when the atmosphere in the growth chamber is switched to nitrogen gas, since nitrogen has a lower thermal conductivity than hydrogen gas, the temperature distribution in the growth chamber may change. That is, by switching the gas, the temperature in the growth chamber temporarily rises, and the deposits (impurities) from the growth chamber may re-evaporate and enter the epitaxial growth film. According to the present invention, since such a problem does not occur, it is possible to obtain a high-quality epitaxial growth film with a low density of unintended impurities and residual impurities that cause deep levels and crystal defects.

  In addition, according to the present invention, the n-type GaN-based compound semiconductor layer is left as a whole or part of the region contributing to the operation of the semiconductor device, thereby simplifying the process.

In the present invention, the n-type GaN compound semiconductor layer can effectively prevent the dissolution of atomic hydrogen between the n-type GaN compound semiconductor layer and the p-type GaN compound semiconductor layer below. A potential barrier based on a junction or a pn junction (or a pin junction) is formed. That is, this potential barrier constructs a barrier whose potential level increases from the n-type GaN compound semiconductor layer toward the p-type GaN compound semiconductor layer. For this reason, the process in which atomic hydrogen permeates the n-type GaN compound semiconductor layer and dissolves into the p-type GaN compound semiconductor layer is blocked by this potential barrier. Therefore, for the purpose of preventing the dissolution of atomic hydrogen, it is desirable that this potential barrier is higher. Accordingly, the impurity density of the n-type GaN compound semiconductor layer is preferably a high impurity density of 5 × 10 ¹⁸ cm ⁻³ or more.

  In the present invention, by setting the impurity density in the vicinity of the interface between the n-type GaN-based compound semiconductor layer and the p-type GaN-based compound semiconductor layer to a value higher than the solid solubility of the n-type GaN-based compound semiconductor layer, atomic hydrogen Can form a potential barrier that effectively inhibits dissolution into the p-type GaN-based compound semiconductor layer.

  Furthermore, in the present invention, the atomic hydrogen is converted to p by forming 1 to 5 molecular layers consisting only of n-type impurity atoms in the vicinity of the interface between the n-type GaN-based compound semiconductor layer and the p-type GaN-based compound semiconductor layer. A potential barrier that effectively prevents dissolution can be formed in the type GaN compound semiconductor layer.

Furthermore, in the present invention, if the forbidden band width of the n-type GaN-based compound semiconductor layer is made smaller than that of the p-type GaN-based compound semiconductor layer to form a heterojunction, the conduction at the heterojunction interface is achieved. Since the height of the potential barrier due to the band discontinuous amount ΔE _C can be added, a high potential barrier for effectively preventing dissolution of atomic hydrogen into the p-type GaN compound semiconductor layer can be formed.

  Furthermore, in the present invention, the first and second substrate temperatures usually do not belong to a temperature range in which atomic hydrogen is dissolved in the p-type GaN compound semiconductor layer. That is, the substrate temperature at the time of vapor phase epitaxial growth is higher than the “solution stabilization temperature”, and gaseous hydrogen and atomic hydrogen obtained by thermal decomposition of the gaseous hydrogen are each in the semiconductor layer at the time of vapor phase epitaxial growth. It does not bind to the constituent elements. For this reason, gaseous hydrogen and atomic hydrogen do not exist between the lattices of the semiconductor layer or cannot exist stably in the semiconductor layer, and are adsorbed (attached) to the upper surface of the epitaxial growth film.

  In the present invention, additional steps may be added. For example, after the step of depositing the metal thin film in contact with the n-type GaN compound semiconductor layer, the electrode layer is in contact with the n-type GaN compound semiconductor layer by performing heat treatment (sintering) in an atmosphere not containing hydrogen gas. And a step of forming the substrate may be further added. This “electrode layer” is an ohmic electrode layer having a low contact resistance for applying a current or voltage to the semiconductor device. Thus, it is effective that atomic hydrogen is mixed into the p-type GaN-based compound semiconductor layer during processes other than the vapor phase epitaxial growth process by forming an electrode layer by heat treatment in an atmosphere that does not contain hydrogen gas. Can be prevented.

  Similarly, an additional step of removing at least part of the p-type GaN compound semiconductor layer by dry etching in an atmosphere not containing hydrogen gas may be used. The gas used for dry etching such as vapor phase etching, photoexcited etching, plasma etching, ion etching, etc. is an atmosphere that does not contain hydrogen gas, so that atomic hydrogen can be converted into a p-type GaN system in processes other than the vapor phase epitaxial growth process. Mixing into the compound semiconductor layer can be effectively prevented.

  According to the present invention, the activation rate of acceptor impurities is high, and a high carrier density is obtained. That is, a p-type GaN compound semiconductor layer having a low resistivity can be easily formed.

  Further, according to the present invention, the temperature in the growth chamber can be lowered in the atmosphere containing the hydrogen gas used as the carrier gas at the time of epitaxial growth, so that the work procedure can be simplified.

  Furthermore, according to the present invention, since hydrogen gas that can be purified with high purity can be used consistently to complete epitaxial growth, it is possible to keep impurities from mixing in low.

  Furthermore, according to the present invention, since the temperature in the growth chamber does not rise temporarily by switching the gas, deposits (impurities) from the inside of the growth chamber do not re-evaporate when the gas is switched. For this reason, the density of unintended impurities and residual impurities is low. That is, it is possible to obtain a high-quality epitaxially grown film with high controllability of impurity density. Also, the surface morphology of the epitaxially grown film is good.

  Furthermore, according to the present invention, it is possible to provide a method of manufacturing a GaN-based compound semiconductor device that has high emission intensity in application to a semiconductor light emitting element and low power consumption in application to a semiconductor integrated circuit.

  Furthermore, according to the present invention, since the n-type GaN compound semiconductor layer is left as a region contributing to the operation of the semiconductor device, the number of processes is not increased and the process is simplified. Therefore, it is possible to provide a method for manufacturing a GaN-based compound semiconductor device that is low in manufacture and high in yield.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

FIG. 1C is a cross-sectional view showing the structure of the semiconductor light emitting device according to the embodiment of the present invention. As shown in FIG. 1C, the semiconductor light emitting device according to the embodiment of the present invention has a buffer layer 12 and a p-type cladding layer 15 on a sapphire substrate 11 whose main surface is a c-plane as an insulating substrate. The active layer 14 and the n-type cladding layer 13 are sequentially deposited. The thickness of the buffer layer 12 is about 25 nm. The thickness of the p-type cladding layer 15 is about 2 μm, and the impurity density of the p-type cladding layer 15 is about 3 × 10 ¹⁸ cm ⁻³ . The active layer 14 is composed of an intrinsic (i-type) InGaN (indium gallium nitride) semiconductor layer. “Intrinsic (i-type)” means that no impurities are intentionally added (dope), and it is noted that a certain amount of residual impurities are allowed in consideration of the level of actual crystal growth technology. Should. Therefore, the active layer 14 may be a p-type semiconductor layer having an impurity density of about 5 × 10 ¹⁵ cm ⁻³ or less. The thickness of the active layer 14 is about 2 nm. The n-type cladding layer 13 has a thickness of about 0.5 μm and an impurity density of about 5 × 10 ¹⁸ cm ⁻³ .

  Then, as shown in FIG. 1C, the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 are partially removed by etching to form recesses (notches) 81. An anode electrode 19 is formed on the p-type cladding layer 15 exposed on the bottom surface of the recess (notch) 81, and a cathode electrode 18 is formed on the n-type cladding layer 13. The cathode electrode 18 adopts a two-layer structure in which a metal thin film having low resistance ohmic contact with the n-type cladding layer 13, for example, titanium (Ti) having a thickness of 20 nm and gold (Au) having a thickness of about 400 nm is laminated. Has been. On the other hand, as the anode electrode 19, a metal thin film in low resistance ohmic contact with the p-type cladding layer 15, for example, a two-layer structure in which nickel (Ni) is deposited to a thickness of 20 nm and gold (Au) is deposited to a thickness of 400 nm. Is adopted. In addition to the Ni / Au layered structure, the metal thin film in low resistance ohmic contact with the p-type cladding layer 15 may be a single layer of palladium (Pd), Ti, platinum (Pt), indium (In), or Ni It is also possible to use a laminated structure or alloy containing Au or Au. As the metal thin film in low resistance ohmic contact with the n-type cladding layer 13, in addition to Ti and Au, a single layer of Al or In, or a laminated structure or alloy containing Ti or Au is also possible.

  The semiconductor light emitting device according to the embodiment of the present invention shown in FIG. 1C is opposite to the conventional semiconductor light emitting device shown in FIG. 5 in the conductivity type of each semiconductor layer formed on the upper surface of the sapphire substrate. It should be noted that Further, in order to increase the activation rate of acceptor impurities in the p-type cladding layer 15, the process related to the p-type cladding layer 15 is different from the conventional method for manufacturing a semiconductor light emitting device. Hereinafter, a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention will be described in detail with reference to the process cross-sectional view of FIG.

(A) First, a sapphire substrate 11 serving as a starting base material is prepared. This sapphire substrate 11 is subjected to organic cleaning and acid cleaning, and then placed in a chamber (growth chamber) of the MOCVD apparatus, and subjected to heat treatment at 1100 ° C. for about 10 minutes in a hydrogen gas (H ₂ ) atmosphere. The natural oxide film on the surface is removed. An insulating substrate other than the sapphire substrate 11 can be used, but the sapphire substrate 11 is practical in consideration of the difference in lattice constant from the GaN-based compound semiconductor material.

  (B) Next, the sapphire substrate 11 is heated to about 600 ° C., and the buffer layer 12 is formed on one main surface of the sapphire substrate 11. Further, the temperature of the sapphire substrate 11 is raised to 1040 ° C., and as shown in FIG. 1A, the p-type GaN compound semiconductor layer of the present invention is formed on the buffer layer 12 at the first substrate temperature. A p-type cladding layer 15, an active layer 14, and an n-type cladding layer 13 that becomes an n-type GaN-based compound semiconductor layer at the second substrate temperature are sequentially deposited. When the continuous deposition of the buffer layer 12, the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 is completed, the temperature of the sapphire substrate 11 is set to the third substrate temperature (in the atmosphere containing hydrogen gas). Reduce to near room temperature).

(C) Next, when the temperature of the sapphire substrate 11 decreases to near room temperature, the sapphire substrate 11 is taken out from the MOCVD apparatus. In the embodiment of the present invention, the n-type semiconductor layer 13 positioned at the uppermost layer of the semiconductor multilayer structure functions as a cap layer and at the same time functions as the n-type clad layer 13 as it is, so that the prior art (third prior art) Thus, the removal process of the n-type cladding layer 13 is unnecessary. Therefore, as soon as the sapphire substrate 11 is taken out of the MOCVD apparatus, the process proceeds to the step of exposing the p-type cladding layer 15. That is, a mask (not shown) made of a photoresist, a silicon oxide film (SiO ₂ ), or the like is formed on the upper surface of the n-type cladding layer 13 which is the uppermost layer of the semiconductor multilayer structure. This mask has an opening pattern at a position corresponding to a recess (notch) 81 exposing the p-type cladding layer 15. Subsequently, it is placed in a known dry etching apparatus, and through this mask opening pattern, a part of the n-type cladding layer 13, the active layer 14 and the p-type cladding layer 15 is dry-etched by the RIE method or the like to form a recess ( A notch 81) is formed. As a result, as shown in FIG. 1B, a part of the n-type cladding layer 13 and the active layer 14 is removed, and a part of the p-type cladding layer 15 is formed on the bottom surface of the recess (notch) 81. Exposed. In the embodiment of the present invention, the dry etching for forming the recess (notch) 81 is also performed in an atmosphere substantially not containing hydrogen gas. That is, a part of the n-type cladding layer 13, the active layer 14, and the p-type cladding layer 15 is removed by etching using chlorine gas (Cl ₂ ) as an etching gas. By doing so, it is possible to satisfactorily prevent atomic hydrogen from dissolving in the p-type cladding layer 15 during this dry etching step. If the substrate temperature in dry etching is a relatively low temperature of less than 400 ° C., it is considered that atomic hydrogen dissolution in the p-type cladding layer 15 does not occur so much even if etching is performed in an atmosphere containing hydrogen gas. . In such a case, the recess (notch portion) 81 can be formed by etching in an atmosphere containing a little hydrogen gas.

(D) Finally, as a metal thin film in low resistance ohmic contact with the p-type cladding layer 15 at the bottom of the recess (notch) 81, nickel (Ni) is 20 nm, gold (Au) is 400 nm, and well-known vacuum deposition. It is formed using a method or a sputtering method. Further, as a metal thin film in low resistance ohmic contact with the n-type cladding layer 13, titanium (Ti) is formed with a thickness of about 20 nm and gold is formed with a thickness of about 400 nm. When these low resistance ohmic contact metal thin films are patterned using a so-called lift-off method and then subjected to heat treatment (sintering), the anode electrode 19 is formed on the p-type cladding layer 15 and the cathode electrode 18 is formed on the n-type cladding layer 13. Is formed, and the semiconductor light emitting device shown in FIG. 1C is obtained. Sintering for obtaining low-resistance ohmic contact is performed in an atmosphere that does not contain hydrogen gas such as nitrogen (N ₂ ), helium (He) gas, argon (Ar) gas, etc., at a substrate temperature of about 400 ° C.

  In the method for manufacturing a semiconductor light emitting device described above, the buffer layer 12, the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 are formed on the sapphire substrate 11 described in the step (b) by the MOCVD method. The steps of continuous vapor phase epitaxial growth will be described in detail in the following (i) to (v).

(i) After the sapphire substrate 11 is placed in the growth chamber of the MOCVD apparatus, first, trimethylgallium gas (Ga (CH ₃ ) ₃ : hereinafter referred to as “TMG gas”) and NH ₃ (ammonia) gas are supplied into the growth chamber. Then, the buffer layer 12 made of GaN is formed on the upper surface of the sapphire substrate 11. TMG gas and NH ₃ gas are a Ga source and an N source, respectively. The buffer layer 12 is for improving the crystallinity of the epitaxial growth layer laminated on the sapphire insulating substrate 11. That is, the sapphire substrate 11 serving as an insulating substrate and the GaN-based compound semiconductor material formed on the sapphire substrate 11 have greatly different lattice constants. Therefore, a semiconductor layer formed to relieve stress due to the difference in lattice constants. It is. The buffer layer 12 is formed at a lower temperature than the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 formed above this layer. In the embodiment of the present invention, after the heating temperature of the sapphire substrate 11 is about 600 ° C., the flow rate of TMG gas, that is, the supply amount of Ga is about 4.3 μmol / min, and the flow rate of NH ₃ gas, that is, the supply amount of N. Was formed at a rate of about 17.9 mmol / min.

(Ii) Subsequently, the heating temperature of the sapphire substrate 11 is set to about 1040 ° C. (first substrate temperature), TMG gas, NH ₃ gas and Cp ₂ Mg gas are supplied into the growth chamber, and p is applied to the upper surface of the sapphire substrate 11. A clad layer (p-type GaN compound semiconductor layer) 15 made of type GaN is formed. In the embodiment of the present invention, the flow rate of TMG gas is about 4.3 μmol / min, the flow rate of NH ₃ gas is about 53.6 mmol / min, and the flow rate of Cp ₂ Mg gas, that is, the supply amount of Mg is about 0.1. 12 μmol / min. When the p-type cladding layer 15 is formed, the growth chamber contains a large amount of hydrogen gas that hinders the activation of the p-type conductivity impurities, but the atmospheric temperature during the vapor phase epitaxial growth is the dissolution of atomic hydrogen. Since the temperature is considerably higher than the stabilization temperature, it is considered that atomic hydrogen does not dissolve in the vapor phase epitaxial growth layer. That is, the temperature at which a specific impurity is dissolved and stabilized in a semiconductor material (hereinafter referred to as “solution stabilization temperature” for the sake of convenience) is almost determined for each substance, and is a temperature considerably higher than this solution stabilization temperature. At low temperatures, the impurities cannot be present stably in the semiconductor material, and as a result, it is considered that the impurities are adsorbed on the surface of the semiconductor material (which may be called precipitation). Here, it is considered that the dissolution stabilization temperature of atomic hydrogen is considerably lower than 400 ° C to 800 ° C. From this, since the film growth temperature by the above-mentioned MOCVD or the like is about 1040 ° C., atomic hydrogen cannot stably exist in the semiconductor region during the vapor phase epitaxial growth, and is adsorbed on the upper surface of the growth film ( It is thought that it is in an attached state.

(iii) Subsequently, the heating temperature of the sapphire substrate 11 is set to 800 ° C., and TMG gas, NH ₃ gas and trimethylindium gas (In (CH ₃ ) ₃ : hereinafter referred to as “TMI gas”) are supplied into the growth chamber. An active layer 14 made of an InGaN semiconductor layer is formed on the p-type cladding layer 15. In the embodiment of the present invention, the supply amount of TMG gas is about 1.1 μmol / min, the flow rate of NH ₃ gas is about 67 mmol / min, the flow rate of TMI gas, that is, the supply amount of In is about 4.5 μmol / min. Minutes.

(Iv) Subsequently, the heating temperature of the sapphire substrate 11 is set to 1040 ° C. (second substrate temperature), TMG gas, NH ₃ gas, and monosilane gas are supplied into the growth chamber, and as shown in FIG. An n-type cladding layer (n-type GaN compound semiconductor layer) 13 made of n-type GaN is formed on the active layer 14. In the embodiment of the present invention, the flow rate of TMG gas, that is, the supply amount of Ga is about 4.3 μmol / min, the flow rate of NH ₃ gas, that is, the supply amount of N is about 53.6 mmol / min, and the flow rate of monosilane gas, that is, Si. Was supplied at a rate of about 2.5 nmol / min.

  (v) Thus, as shown in FIG. 1A, a semiconductor laminated structure comprising the buffer layer 12, the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 is formed on one main surface of the sapphire substrate 11. After the successive formation, the temperature in the growth chamber is lowered (to the third substrate temperature). In the process of lowering the temperature in the growth chamber, the semiconductor laminated structure is exposed to the atomic hydrogen dissolution stabilization temperature, but the atomic hydrogen dissolution is effectively prevented by the presence of the n-type cladding layer 13 functioning as a cap layer. Is done. In addition, since it is not necessary to make the growth chamber contain no hydrogen gas (for example, a nitrogen atmosphere), the temperature inside the growth chamber can be lowered in the atmosphere containing hydrogen gas as in the embodiment. Therefore, it is possible to effectively prevent impurities from being mixed.

  In this way, continuous epitaxial growth of the buffer layer 12, the p-type cladding layer 15, the active layer 14, and the n-type cladding layer 13 according to the process (b) described above can be realized.

The n-type cladding layer 13 which is the uppermost layer of continuous epitaxial growth prevents the dissolution of atomic hydrogen that hinders the activation of p-type impurities in the p-type cladding layer 15 formed thereunder via the active layer 14. Therefore, the impurity density and thickness are important. That is, the n-type cladding layer 13 can prevent the dissolution of atomic hydrogen because the n-type cladding layer 13, the underlying i-type active layer 14, and the underlying p-type cladding layer 15 have a pin junction. And a potential barrier based on this pin junction is formed (if the active layer 14 is p-type due to the presence of residual impurities, the n-type clad layer 13 and the p-type active layer 14 below Thus, a pn junction is formed, and a potential barrier based on the pn junction is formed). That is, the potential barrier associated with this pin junction (or pn junction) constructs a barrier whose potential level increases from the n-type cladding layer 13 to the p-type cladding layer 15 via the active layer 14. For this reason, the process of atomic hydrogen passing through the n-type cladding layer 13 and dissolving into the p-type cladding layer 15 is prevented by this pin junction (or pn junction). Therefore, in order to prevent atomic hydrogen dissolution, it is desirable that this potential barrier is high. For this purpose, it is preferable that the n-type cladding layer 13 has a high impurity density. On the other hand, the dissolution of atomic hydrogen is blocked by the potential barrier based on this pin junction (or pn junction), but the existence of the n-type cladding layer 13 is considered to contribute to the prevention of atomic hydrogen dissolution to some extent. Even from the viewpoint of satisfactorily forming a pin junction (or pn junction) between the n-type cladding layer 13 and the p-type cladding layer 15, it is not desirable to form the n-type cladding layer 13 so thin. In view of the above, in the embodiment of the present invention, the impurity density of the n-type cladding layer 13 is about 5 × 10 ¹⁸ cm ⁻³ and the thickness of the n-type cladding layer 13 is about 0.5 μm. Furthermore, in order to form a potential barrier that effectively prevents atomic hydrogen from dissolving in the p-type cladding layer 15, the impurity density in the vicinity of the interface between the n-type cladding layer 13 and the p-type cladding layer 15 is set to 5 × 10 5. ^What is necessary is just to be ¹⁹ cm- ³ or more. Alternatively, by making the impurity density in the vicinity of the interface between the n-type cladding layer 13 and the active layer 14 higher than the solid solubility of the n-type cladding layer 13, atomic hydrogen is effectively dissolved in the p-type cladding layer 15. A potential barrier can be formed.

  Further, by forming a 1 to 5 molecular layer consisting of only n-type impurity atoms, such as so-called delta (δ) doping, in the vicinity of the interface between the n-type cladding layer 13 and the active layer 14, atomic hydrogen is converted into p. A potential barrier that effectively prevents dissolution can be formed in the mold cladding layer 15.

On the other hand, the band gap E _g of the n-type cladding layer 13, and smaller than the band gap of the active layer 14 and the p-type cladding layer 15 E _g, by forming a heterojunction, in conducting the heterojunction interface Since the height of the potential barrier due to the band discontinuous amount ΔE _C can be added, a high potential barrier for effectively preventing dissolution of atomic hydrogen into the p-type cladding layer 15 can be formed.

  In the method for manufacturing a semiconductor light emitting device according to the embodiment of the present invention, as described above, the buffer layer 12 is formed on the sapphire substrate 11, the p-type cladding layer 15, the active layer 14, and the second layer at the first substrate temperature. After the n-type cladding layer 13 is successively formed at the substrate temperature, the temperature in the growth chamber is lowered to the third substrate temperature near room temperature. In the process of lowering the temperature in the growth chamber, the semiconductor multilayer structure is exposed to the atomic hydrogen dissolution and stabilization temperature. Therefore, in the conventional manufacturing method in which the n-type cladding layer 13 is not formed, atoms contained in the atmosphere in the growth chamber Hydrogen is dissolved in the p-type cladding layer 15. For this reason, in the conventional manufacturing method, in order to prevent the dissolution of atomic hydrogen, it is necessary to make the growth chamber contain no hydrogen gas in the process of lowering the temperature of the growth chamber.

  On the other hand, in the embodiment of the present invention, since the dissolution of atomic hydrogen is effectively prevented by the presence of the n-type cladding layer 13 as described above, the growth chamber does not contain hydrogen gas (for example, a nitrogen atmosphere). ) Is not necessary. For this reason, in the embodiment of the present invention, the temperature in the growth chamber is lowered in an atmosphere containing hydrogen gas. As a result, it is not necessary to switch the atmosphere in the growth chamber to an atmosphere that does not contain hydrogen gas, and the growth process can be simplified. In addition, since hydrogen gas can be purified with higher purity than nitrogen or the like, there is an advantage that contamination of the semiconductor stacked structure can be suppressed in the chamber at a stage where the temperature in the growth chamber is lowered. . Furthermore, there is no problem of re-evaporation of impurities from the deposits from inside the growth chamber when the atmosphere in the growth chamber is switched to nitrogen gas.

  Further, according to the method for manufacturing a semiconductor light emitting element (blue LED) according to the embodiment of the present invention, the cap layer is constituted by the n-type cladding layer 13 that contributes to the operation of the device (blue LED). The removal process is unnecessary, and there is an advantage that the number of processes is not increased and the process is simplified.

(Other embodiments)
It should not be understood that the description and the drawings, which form part of the disclosure of the above embodiments, limit the present invention. It will be apparent from the above description that various alternative embodiments, examples and operational techniques are possible for those skilled in the art, as shown below.

For example, in the description of the above embodiment, the case where the n-type clad layer 13 made of GaN is used has been described. However, the n-type clad layer can use a GaN-based compound semiconductor layer other than GaN. . For example, In _x Al _y Ga _1-xy N (0 <x ≦ 1, 0 <y ≦ 1, x + y ≦ 1) into which silicon (Si) or selenium (Se) is introduced as an n-type impurity is used. May be. By using In _x Al _y Ga _1-xy N, a barrier having a high potential barrier can be formed at the interface with the p-type cladding layer, and dissolution of atomic hydrogen can be more effectively prevented.

Further, in the description of the above embodiment, the active layer 14 is an intrinsic (i-type) region to which impurities are not intentionally added (doped), and this intrinsic (i-type) region contains a certain amount of residual impurities. Has been described as an acceptable semiconductor region. However, the active layer 14 may be positively doped with impurities. For example, a p-type impurity (acceptor) may be doped and the active layer 14 made of a p-type semiconductor layer having an impurity density of about 8 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁶ cm ⁻³ may be used.

  Furthermore, the following modifications are possible.

(Modification 1)
In the above description of the embodiment, the case of using the sapphire substrate 11 as the insulating substrate has been described. However, a low-resistance substrate made of silicon carbide (SiC) shown in FIG. 21 and 22 may be used. In this case, a semiconductor light emitting element of a type in which a current flows in the vertical direction of the device is obtained.

  FIG. 2 is a schematic cross-sectional view of a semiconductor light emitting device according to a modification of the embodiment of the present invention. A buffer layer 12, a p-type cladding layer 15, an active layer 14, and n are formed on the upper surface of a p-type SiC substrate 22. A mold cladding layer 13 is formed sequentially. An anode electrode 19 is formed on the lower surface of the p-type SiC substrate 22, and a cathode electrode 18 is formed on the upper surface of the n-type cladding layer 13. In the structure shown in FIG. 2, the n-type semiconductor layer 13 positioned at the uppermost layer of the semiconductor multilayer structure functions as a cap layer and at the same time functions as the n-type cladding layer 13 and is removed by etching before electrode formation. The process to do is unnecessary.

(Modification 2: Semiconductor laser)
Furthermore, the present invention can also be applied to a semiconductor laser as shown in FIG. FIG. 3 is a schematic structural example of a GaN blue semiconductor laser formed on an insulating substrate 23 such as a sapphire substrate. As shown in FIG. 3, on the insulating substrate 23 having a thickness of 70 μm, a buffer layer 12 made of n-type GaN having a thickness of 50 nm, an n-type contact layer 33 made of n-type GaN having a thickness of 4 μm, and a thickness of 0. An n _- type cladding layer 34 made of 5 μm n-type Al _x Ga _1-x N, an n-side light guide layer 35 made of intrinsic (i-type) GaN having a thickness of 30 nm, and an active layer having a multiple quantum well (MQW) structure (Hereinafter referred to as “MQW active layer”) 36, p-side light guide layer 37 made of intrinsic (i-type) GaN having a thickness of 30 nm, p having a thickness of 0.5 μm formed at the first substrate temperature A p-type cladding layer 38 made of p _- type Al _x Ga _1-x N and a p-type contact layer 39 made of p-type GaN having a thickness of 1 μm formed at the same first substrate temperature are sequentially formed. is doing. Then, the p-type contact layer 39 formed at the first substrate temperature has a thickness partially at the second substrate temperature so as to have a stripe-shaped opening at the center. An n-type cap layer 40 made of .2 μm n-type GaN is deposited to form the uppermost layer of the semiconductor multilayer structure. In the middle of the manufacturing process, the n-type cap layer 40 is once deposited on the entire upper surface of the p-type contact layer 39 at the second substrate temperature, and is etched before the anode electrode 19 is formed. It is patterned and removed in a stripe shape showing. This n-type cap layer 40 is a layer that functions as a film that prevents the dissolution of atomic hydrogen that hinders the activation of p-type impurities in the p-type cladding layer 15 formed thereunder during the manufacturing process. At the same time, after completion of the manufacturing process, the layer functions as a current confinement layer that limits the current path. As in the example of FIG. 1, after the end of continuous epitaxial growth, the semiconductor substrate is cooled to the third substrate temperature, and then a part of the semiconductor stacked structure is formed by the RIE method using a gas not containing hydrogen gas, etc. Etching until the surface appears on the surface, forming a recess (notch), and laminating titanium (Ti), gold (Au), Ti, Au in this order on the surface of the n-type contact layer 33 exposed at the bottom of the recess Thus, the cathode electrode 18 is formed. The thicknesses of the metal layers constituting the cathode electrode 18 are 20 nm, 400 nm, 20 nm, and 1 μm, respectively. An anode electrode 19 is formed on the p-type contact layer 39 and the n-type cap layer 40 by laminating platinum (Pt), Ti, Pt, and Ti in this order from the bottom. The thickness of each metal layer constituting the anode electrode 19 is 20 nm, 400 nm, 20 nm, and 1 μm, respectively. Alternatively, the anode electrode 19 may be formed by laminating palladium (Pd), Ti, Pt, and Ti in this order from the bottom. The sintering for obtaining the cathode electrode 18 and the anode electrode 19 in low-resistance ohmic contact is performed in an atmosphere not containing hydrogen gas such as N ₂ gas, He gas, Ar gas, etc. at a substrate temperature of about 400 ° C.

The MQW active layer 36 has a superlattice structure using a periodic change in the In composition x of the In _x Ga _1-x N compound semiconductor layer. Specifically, a quantum well layer having a thickness of 2.5 nm and an In composition x = 0.20 and a barrier layer having a thickness of 2.5 nm and an In composition x = 0.05 are alternately stacked for about 20 cycles. ing.

The impurity density of each layer constituting the semiconductor multilayer structure of FIG. 3 is, for example, 2 × 10 ¹⁸ cm ⁻³ for the n-type contact layer 33, 5 × 10 ¹⁷ cm ^{−3 for} the n-type cladding layer 34, and the p-type cladding layer 38. 5 × 10 ¹⁷ cm ⁻³ and the p-type contact layer 39 is 2 × 10 ¹⁹ cm ⁻³ . The impurity density of the n-type cap layer 40 is about 5 × 10 ¹⁸ cm ⁻³ .

(Modification 3: Semiconductor laser)
Furthermore, the present invention can also be applied to a semiconductor laser as shown in FIG. FIG. 4 is a schematic structural example of a GaN-based blue semiconductor laser having an MQW active layer 36 formed on an n-type low-resistance substrate 24 made of an n-type SiC substrate or the like. 3 is different from FIG. 3 in that a low-resistance substrate 24 is used and the cathode electrode 18 is disposed on the lower surface of the low-resistance substrate 24. Others are the same as those in FIG. 3, and the n-type cap layer 40 formed at the second substrate temperature partially remains on the p-type contact layer 39 formed at the first substrate temperature. An anode electrode 19 is formed on the contact layer 39. The anode electrode 19 is cooled to the third substrate temperature after the end of the continuous epitaxial growth, and then a part of the n-type cap layer 40 is partially p-type contact layer 40 by an RIE method using a gas not containing hydrogen gas. Is formed after etching until it appears on the surface. Others are the same as in FIG.

(Modification 4: Transistor)
In addition to these semiconductor light emitting elements, the present invention can also manufacture semiconductor devices such as transistors and semiconductor integrated circuits. For example, in an insulated gate type SIT and an insulated gate type FET, a p-type semiconductor layer having a predetermined thickness is formed on an insulating substrate such as a sapphire substrate or a low resistance substrate such as an SiC substrate via a buffer layer. And it is realizable by the process of forming the n-type cap layer of this invention on this p-type semiconductor layer. That is, the insulated gate type SIT can be manufactured as follows.

(A) First, a sapphire substrate is prepared, and the buffer layer 12 is formed on the upper surface of the sapphire substrate. In addition, a first p-type semiconductor layer made of GaN having a thickness of 0.5 μm to 1 μm is formed on the buffer layer 12. In _0.2 Ga _{0. 5 having} a thickness of 0.5 μm to 1 μm at the first substrate temperature _{. A} second p-type semiconductor layer made of ₈ N and an n-type cap layer made of In _0.3 Al _0.3 Ga _0.4 N having a thickness of 0.2 μm to 0.5 μm at the second substrate temperature; , Continuously deposited by low pressure MOCVD to form a semiconductor stacked structure. When the formation of the semiconductor multilayer structure is completed, the temperature of the sapphire substrate is lowered to around room temperature (third substrate temperature) in an atmosphere containing hydrogen gas.

  (B) Then, by using the photolithography technique and RIE, the n-type cap layer portion to be the drain region and the source region is selectively left, and the other n-type cap layers are removed by etching to become the channel region. The second p-type semiconductor layer is exposed. Further, the second p-type semiconductor layer may be etched by 0.2 μm to 0.5 μm to form a recessed gate structure.

  (D) A gate insulating film is deposited on the second p-type semiconductor layer to be the exposed channel region. A metal film such as aluminum (Al) is deposited on the entire surface of the gate insulating film by a vacuum evaporation method or a sputtering method. Then, using a photolithography technique and reactive ion etching (RIE) so that the metal such as aluminum is selectively left only on the gate insulating film between the n-type drain region and the n-type source region, A gate electrode is formed by patterning.

(E) Then, a metal such as Ti / Au / Ti / Au is deposited on the surfaces of the n-type drain region and the n-type source region by a lift-off method using a vacuum evaporation method or a sputtering method. If a source electrode is formed, an insulated gate type SIT is completed. The sintering for obtaining the drain electrode and the source electrode in low resistance ohmic contact is performed in an atmosphere not containing hydrogen gas such as N ₂ gas, He gas, Ar gas, etc. at a substrate temperature of about 400 ° C.

If the forbidden band width of the compound semiconductor layer constituting the n-type drain region and the n-type source region is made smaller than the forbidden band width of the second p-type semiconductor layer to form a heterojunction, the heterojunction interface Since the height of the potential barrier due to the discontinuous amount ΔE _C of the conduction band can be added, a high potential barrier can be formed for effectively preventing dissolution of atomic hydrogen into the second p-type semiconductor layer. At the same time, ohmic electrodes can be formed with lower contact resistance for the n-type drain region and the n-type source region.

In the manufacturing process of the above-described insulated gate type SIT, instead of the gate insulating film, GaN having a larger forbidden band than In _0.2 Ga _0.8 N constituting the second p-type semiconductor layer is formed on the channel region. It may be deposited. In this way, the gate structure of the In _0.2 Ga _0.8 N / GaN heterostructure enables operation similar to that of a high electron mobility transistor (HEMT).

On the other hand, a sapphire substrate is prepared, a buffer layer 12 is formed on the upper surface of the sapphire substrate, and further, the buffer layer 12 is made of In _0.2 Ga _0.8 N having a thickness of 0.5 μm to 1 μm. An n-type collector layer, a p-type base layer made of In _0.2 Ga _0.8 N having a thickness of 0.1 μm to 0.5 μm at the first substrate temperature, and a thickness at the second substrate temperature. If a n-type cap layer made of GaN having a thickness of 0.2 μm to 0.5 μm is continuously deposited by low pressure MOCVD to form a semiconductor multilayer structure, a heterojunction bipolar transistor (HBT) having the n-type cap layer as a wide emitter layer is formed. ) Can also be configured. In this case, when the formation of the semiconductor stacked structure is completed, the temperature of the sapphire substrate is lowered to near room temperature (third substrate temperature) in an atmosphere containing hydrogen gas, and the n-type cap layer becomes a wide emitter layer. And is removed by etching in an atmosphere not containing hydrogen gas. Further, the base layer exposed by etching is further etched in an atmosphere not containing hydrogen gas to expose the n-type collector layer. If the base electrode is taken out from the base layer exposed by etching in an atmosphere not containing hydrogen gas, the emitter electrode is formed on the upper portion of the n-type cap layer, and the collector electrode is formed on the collector layer exposed by etching, an npn bipolar transistor can be obtained. It is also possible to manufacture. This npn type bipolar transistor may be used as a phototransistor for detecting blue light. Similarly, it can be easily understood from the above description that a junction gate type vertical SIT can be manufactured. Further, it is possible to manufacture an image sensor that detects blue light by integrating the vertical SIT and bipolar transistors in a matrix.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is typical process sectional drawing which shows the manufacturing method of the semiconductor light-emitting device concerning embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor light-emitting device which concerns on other embodiment of this invention (modification 1). It is typical sectional drawing which shows the structure of the semiconductor light-emitting device which concerns on other embodiment of this invention (modification 2: semiconductor laser). It is typical sectional drawing which shows the structure of the semiconductor light-emitting device which concerns on other embodiment of this invention (modification 3: semiconductor laser). It is typical sectional drawing which shows the structure of the conventional semiconductor light-emitting device.

Explanation of symbols

11 Sapphire substrate 12 Buffer layer 13, 34 n-type cladding layer 14 active layer 15, 38 p-type cladding layer 18 cathode electrode 19 anode electrode 22 p-type SiC substrate 24 low resistance substrate 23 insulating substrate 33 n-type contact layer 35 n Side light guide layer 36 Multiple quantum well (MQW) active layer 37 p side light guide layer 39 p-type contact layer 81 Recess (notch)

Claims (8)

Depositing a p-type gallium nitride compound semiconductor layer by epitaxial growth while introducing a p-type dopant gas in an atmosphere containing hydrogen gas at a first substrate temperature;
On the p-type gallium nitride compound semiconductor layer, the forbidden band width is reduced to the p-type nitride by epitaxial growth while introducing an n-type dopant gas in an atmosphere containing the hydrogen gas at a second substrate temperature. Depositing an n-type gallium nitride compound semiconductor layer smaller than the gallium compound semiconductor layer;
In the atmosphere containing the hydrogen gas, the substrate is cooled to a third substrate temperature that is lower than the first and second substrate temperatures and exists in a temperature range in which atomic hydrogen is dissolved in the p-type gallium nitride compound semiconductor layer. And a process of
And a step of depositing a metal thin film in contact with the n-type gallium nitride compound semiconductor layer. After the cooling step, the n-type gallium nitride compound semiconductor layer is selectively etched until the p-type gallium nitride compound semiconductor layer is exposed, and the n-type gallium nitride compound semiconductor layer left by the etching is removed. Forming a drain region and a source region by a pattern;
Depositing a gate insulating film on the p-type gallium nitride compound semiconductor exposed between the drain region and the source region;
Forming a gate electrode on the gate insulating film between the drain region and the source region, and depositing the metal thin film to form the drain electrode on the drain region and the source. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a source electrode is formed on the region. After the cooling step, the n-type gallium nitride compound semiconductor layer is selectively etched until the p-type gallium nitride compound semiconductor layer is exposed, and the n-type gallium nitride compound semiconductor layer left by the etching is removed. Forming a drain region and a source region by a pattern;
Depositing a gallium nitride compound semiconductor layer having a larger forbidden band than the p-type gallium nitride compound semiconductor on the p-type gallium nitride compound semiconductor exposed between the drain region and the source region; ,
Forming a gate electrode on the gallium nitride compound semiconductor layer having a larger forbidden band than the p-type gallium nitride compound semiconductor between the drain region and the source region, 2. The method of manufacturing a semiconductor device according to claim 1, wherein a drain electrode is formed on the drain region and a source electrode is formed on the source region by the step of depositing.   The method further comprises the step of further selectively etching the exposed p-type gallium nitride compound semiconductor layer after the selective etching of the n-type gallium nitride compound semiconductor layer to form a recess gate. A method for manufacturing a semiconductor device according to 2 or 3.   In the step of depositing the n-type gallium nitride compound semiconductor layer, a layer having an impurity density equal to or higher than the solid solubility of the n-type gallium nitride compound semiconductor layer is formed at the interface with the p-type gallium nitride compound semiconductor layer. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the method starts after being performed.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the layer having an impurity density equal to or higher than the solid solubility is a 1 to 5 molecular layer made of only n-type impurity atoms. The method further comprises a step of forming an electrode layer in contact with the n-type gallium nitride compound semiconductor layer by performing a heat treatment in an atmosphere not containing the hydrogen gas after the step of depositing the metal thin film. Item 7. The method for manufacturing a semiconductor device according to any one of Items 1 to 6. The first and second substrate temperatures do not belong to a temperature range in which the atomic hydrogen is dissolved in the p-type gallium nitride compound semiconductor layer. Semiconductor device manufacturing method.

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