JP4091958B2 - Liquid crystal drive device - Google Patents

Description

  The present invention applies a voltage according to image data to a pixel electrode through a source line and a pixel switch, and displays an image by accumulating charges between the pixel electrode and the counter electrode, so-called active matrix. The present invention belongs to a technology related to a liquid crystal driving device for driving a liquid crystal display device using a liquid crystal panel.

  For example, as shown in FIG. 21, an active matrix liquid crystal display device includes a liquid crystal layer 901, a pixel electrode 902, a counter electrode 903, a pixel switch 904 made of a TFT (Thin Film Transistor), a gate line 905, A liquid crystal panel 907 having a source line 906, a gate driver 908, and a source driver 909 are provided.

  The gate driver 908 sequentially applies drive pulses to the gate lines 905. The source driver 909 applies a voltage corresponding to the image data of each pixel to each source line 906. That is, a voltage that sequentially changes according to image data of pixels corresponding to each gate line 905 to which driving pulses are sequentially input is applied to the source line 906, and the voltage is applied between the pixel electrode 902 and the counter electrode 903. An image is displayed by being held in (liquid crystal capacity).

  In the liquid crystal display device as described above, when the voltage applied to the source line 906 changes, in addition to the liquid crystal capacitance, a current that charges and discharges to the parasitic capacitance of the source line 906 flows. Is consumed. In particular, when line inversion driving is performed in which the polarity is inverted for each pixel corresponding to the gate lines 905 adjacent to each other in order to prevent deterioration in image quality, the charge / discharge current that flows for each polarity inversion is large. Even when the display density difference between the pixels is small, the power consumption tends to increase.

  The reduction of the power consumption is an important issue particularly in devices that require long-time driving by batteries, such as mobile terminals such as mobile phones, which have been rapidly increasing in recent years. Therefore, various techniques have been proposed to reduce the power consumption.

  For example, in Japanese Patent Laid-Open No. 2000-221932, prior to the application of a voltage to a source line by a source driver, all the source lines are once connected to each other and the potential of the source line is averaged. Discloses a technique for reducing the current that flows when a voltage corresponding to image data is applied.

  Also, in Japanese Patent Publication No. 9-504389, prior to the application of a voltage to the source line by the source driver, the capacitor is connected to the source line, whereby the electric charge is accumulated in the capacitor, or the accumulated electric charge is A technique for discharging and averaging the potential of the source line is disclosed.

In Japanese Patent Laid-Open No. 10-222130, when a negative voltage is applied after applying a positive voltage to a source line using a positive polarity capacitor and a negative polarity capacitor, for example, Connect a negative capacitor to the source line to accumulate positive charges and lower the source line potential, and connect a negative capacitor that stores negative charges to connect more potential to the source line. A technique for reducing the current that flows when the next negative voltage is applied is disclosed.
JP 2000-221932 A JP-T 9-504389 JP-A-10-222130

  However, each of the conventional liquid crystal driving devices has a problem that it is difficult to significantly reduce power consumption. In other words, if all the source lines are uniformly connected to each other or capacitors are connected as described above, any source line will be at an average potential, so the same voltage is applied next time, for example. In such a case, it is necessary to supply charges for raising or lowering the potential of the source line again. Therefore, useless charge transfer occurs, and power consumption increases accordingly. Further, as disclosed in the above Japanese Patent Laid-Open No. 10-222130, if a capacitor is connected twice every time a voltage corresponding to image data is applied to the source line, the time required for the sequence becomes longer. In some cases, it may be difficult to display an image at a high scanning frequency.

  In view of the above points, it is an object of the present invention to make it possible to easily reduce power consumption, to shorten the time required for charge accumulation and supply, and to reduce the circuit scale. To do.

In order to solve the above-mentioned problem, the solving means taken by the invention of claim 1 is:
The pixel electrode in a liquid crystal display device having a source line, a pixel switch, a pixel electrode connected to the source line via the pixel switch, and a counter electrode provided to face the pixel electrode; A liquid crystal driving device that applies a voltage according to image data for each pixel via a source line,
A plurality of charge storage means for storing charge;
Charge storage means connecting / disconnecting means for connecting / disconnecting the source line and the charge storage means;
After applying a first voltage corresponding to the previous image data to the pixel electrodes, before applying the second voltage corresponding to the next image data to the pixel electrodes,
After connecting the source line to one of the plurality of charge storage means selected according to the first voltage at a first timing,
Control means for controlling each source line to connect the source line to one of the plurality of charge storage means selected according to the second voltage at a second timing;
It is provided with.

According to the first aspect of the present invention, the source line is connected to the charge storage means selected according to the first or second voltage, thereby reducing the movement of useless charge between the source lines and The utilization efficiency can be further improved.

The invention of claim 2
The liquid crystal driving device according to claim 1 ,
The image data is multi-value image data,
Each of the plurality of charge storage units is provided corresponding to a voltage group in which one or more voltages applied to the pixel electrode according to the multi-value image data are grouped.
The control means includes
At the first timing, the source line is connected to the charge storage means corresponding to the voltage group including the first voltage,
At the second timing, the source line is controlled to be connected to the charge storage means corresponding to the voltage group including the second voltage.

According to the second aspect of the present invention, even when a multi-value image is displayed, it is possible to reduce unnecessary charge transfer between the source lines and further improve the charge utilization efficiency.

The invention of claim 3
The liquid crystal driving device according to claim 1 ,
The image data is binary image data,
The plurality of charge storage means includes a high voltage charge storage means corresponding to a voltage applied to the pixel electrode according to the binary image data, and a low voltage charge storage means,
The control means includes
At the first timing, the source line is connected to the high voltage charge storage means or the low voltage charge storage means corresponding to the first voltage,
At the second timing, the source line is controlled to be connected to the high voltage charge storage means or the low voltage charge storage means corresponding to the second voltage.

According to the third aspect of the present invention, even when a binary image is displayed, the use efficiency of charges can be further improved by reducing unnecessary charge transfer between source lines.

The invention of claim 4
A liquid crystal driving device according to any one of claims 1 to 3 ,
The control means controls the presence or absence of connection between the source line and the charge storage means at the first timing and the second timing according to the first voltage and the second voltage. It is characterized by.

The invention of claim 5
The liquid crystal driving device according to claim 4 ,
The control means determines the connection between the source line and the charge storage means at the first timing and the second timing when a difference between the first voltage and the second voltage is a predetermined value or more. It is characterized by controlling to perform to.

  According to these, when the change in the voltage applied to the source line is small, unnecessary charge movement is prevented, so that the charge utilization efficiency can be further improved.

The invention of claim 6
The pixel electrode in a liquid crystal display device having a source line, a pixel switch, a pixel electrode connected to the source line via the pixel switch, and a counter electrode provided to face the pixel electrode; A liquid crystal driving device that applies a voltage according to image data for each pixel via a source line,
A source line connecting line for connecting the source lines,
A connecting line connecting / disconnecting means for connecting / disconnecting the source line and the source line connecting line;
After applying a first voltage corresponding to the previous image data to the pixel electrodes, before applying the second voltage corresponding to the next image data to the pixel electrodes,
Control means for controlling each source line so as to connect the source line to the source line connection line according to the first voltage and the second voltage;
It is provided with.

The invention of claim 7
The liquid crystal driving device according to claim 6 ,
The control means controls the connection between the source line and the source line connection line so that the difference between the first voltage and the second voltage is greater than or equal to a predetermined value.

  According to these, again, when the change in the voltage applied to the source line is small, unnecessary charge movement is prevented, so that the charge utilization efficiency can be further improved and the charge storage means is used. Since it is not necessary, the circuit scale can be greatly reduced.

  According to the present invention, the source line is connected to the capacitive element and then connected to the counter electrode, is connected to the source line in accordance with the image data signal, and further in accordance with the change in the image data signal before and after. By switching capacitor elements and selectively connecting source lines to each other in response to changes in image data signals and successive image data signals, power consumption can be greatly reduced easily. In addition, it is possible to shorten the time required for charge accumulation and supply and to reduce the circuit scale.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 schematically shows a configuration of a main part of a liquid crystal display device including a source driver 300 (liquid crystal driving device) for line inversion driving, a gate driver 200, and a liquid crystal panel 100 according to Embodiment 1 of the present invention. It is a circuit diagram. Here, the line inversion drive reverses the polarity of the voltage applied to the pixel electrode with respect to the counter electrode, which will be described later, for each horizontal scanning period in order to prevent the display image quality of the liquid crystal panel 100 from deteriorating. In general, the potential of the counter electrode is kept constant, and a higher and lower voltage is applied to the pixel electrode, and the potential relationship between the voltage applied to the pixel electrode is reversed by changing the potential of the counter electrode. Here, for the sake of simplicity, the former example will be described.

In FIG. 1, a liquid crystal panel 100 is
Liquid crystal layers L11 to Lmn,
Pixel electrodes P11 to Pmn,
A counter electrode 101;
For example, pixel switches T11 to Tmn made of TFT (Thin Film Transistor),
Gate lines G1 to Gm;
Source lines S1 to Sn, and an image signal voltage corresponding to image data is held between the pixel electrodes P11 to Pmn and the counter electrode 101 (liquid crystal capacitance) so that an image is displayed. It has become.

  The gate driver 200 sequentially applies drive pulses to the gate lines G1 to Gm, and turns on the pixel switches T11 to Tmn connected to the gate lines G1 to Gm, whereby the voltages of the source lines S1 to Sn are turned on. Is applied to the pixel electrodes P11 to Pmn.

  The source driver 300 applies an image signal voltage of each pixel to each source line S1 to Sn. More specifically, the source driver 300 is provided with DA converters 311 to 31n for converting digital image data into analog voltage signals, and the DA converters 311 to 31n are connected to the DA driver transfer gates 321 to 32n, respectively. It is connected to the source lines S1 to Sn.

  The source lines S1 to Sn are connected to each other via the connection line transfer gates 331 to 33n and the source line connection line 330, and are connected to the positive capacitive element transfer gate 341 and the negative capacitive element transfer gate 342. Alternatively, it is connected to one end side of the positive capacitive element 351, one end side of the negative capacitive element 352, or the counter electrode 101 via the counter electrode transfer gate 343. The capacitive elements 351 and 352 store and supply positive or negative charges with the parasitic capacitances of the source lines S1 to Sn, respectively. Further, one end sides of the capacitive elements 351 and 352 are connected to each other via a short-circuit transfer gate 344. The other end side of the capacitive elements 351 and 352 is connected to, for example, the counter electrode 101, although not limited thereto.

  Each of the transfer gates 321... Is controlled by a control signal CTL1, CTL2, CTL3, SELH, SELL, or SHORT output from the timing control unit 301.

  The liquid crystal display device configured as described above responds to image data between each of the pixel electrodes P11 to Pmn and the counter electrode 101 by the following operation corresponding to the change of each control signal shown in FIG. The image signal voltage is held (written).

(Period T1)
This period is a period in which writing to the pixel electrodes P11 to P1n is performed when any one of the gate lines G1 to Gm, for example, the gate line G1 is at the H level. At this time, the control signal CTL1 becomes H level, the DA connection transfer gates 321 to 32n are turned ON, and the image signal voltage having a positive polarity with respect to the counter electrode 101 outputted from the DA converters 311 to 31n is supplied to the source line S1. Applied to ~ Sn. Thus, when an H level drive pulse is output from the gate driver 200 to the gate line G1 as described above, the pixel switches T11 to T1n connected to the gate line G1 are turned on, and the DA converters 311 to 31n are turned on. The output image signal voltage is applied to the pixel electrodes P11 to P1n, and is held in the liquid crystal capacitance between the pixel electrodes P11 to P1n and the counter electrode 101. This voltage is also held in the parasitic capacitances of the source lines S1 to Sn.

(Period T2)
Next, when CTL1 becomes L level, the DA connection transfer gates 321 to 32n are turned OFF, while when CTL2 and SELH become H level, the connection line transfer gates 331 to 33n and the positive capacitive element transfer gate 341 are turned ON. Thus, the source lines S1 to Sn are disconnected from the DA converters 311 to 31n and connected to the positive capacitive element 351. Therefore, positive charges held in the parasitic capacitances of the source lines S1 to Sn move to the positive capacitive element 351, and the potentials of the source lines S1 to Sn are lowered.

(Period T3)
When SELH becomes L level, the positive electrode capacitive element transfer gate 341 is turned OFF. On the other hand, when CTL3 becomes H level, the counter electrode transfer gate 343 is turned ON, and the source lines S1 to Sn are connected from the positive electrode capacitor 351. It is disconnected and connected to the counter electrode 101. Therefore, the potentials of the source lines S1 to Sn are further lowered to the same potential as that of the counter electrode 101.

(Period T4)
In this period, the negative voltage is written into the pixel electrodes P21 to P2n in the same manner as described in the period T1. That is, when CTL1 becomes H level, the DA connection transfer gates 321 to 32n are turned on, and the negative image signal voltage output from the DA converters 311 to 31n is applied to the source lines S1 to Sn. Then, the drive pulse is output from the gate driver 200 to the gate line G2 next to the gate line G1 to which the drive pulse is applied in the period T1, and output from the DA converters 311 to 31n to the corresponding pixel electrodes P21 to P2n. The negative image signal voltage thus applied is applied and held. Here, since the voltages of the source lines S1 to Sn before the image signal voltage is applied are the same as those of the counter electrode 101 as described above, the positive image signal voltage is maintained. Thus, power consumption is reduced as compared with the case where a negative image signal voltage is applied.

(Period T5)
As in the above-described period T2, except that SELL becomes H level instead of SELH, the negative-capacitance element transfer gate 342 is turned on, the source lines S1 to Sn are disconnected from the DA converters 311 to 31n, and the negative electrode Connected to the capacitive element 352. Therefore, negative charges held in the parasitic capacitances of the source lines S1 to Sn move to the negative capacitance element 352, and the potentials of the source lines S1 to Sn rise.

(Period T6)
When SELL goes to L level and CTL3 goes to H level, the negative capacitive element transfer gate 342 is turned off, the counter electrode transfer gate 343 is turned on, and the source lines S1 to Sn are connected to the counter electrode 101. The potentials of the source lines S1 to Sn are further increased to the same potential as that of the counter electrode 101.

(After period T7)
Hereinafter, by repeating the same operation as the period T1 to T6, the image signal voltages output from the DA converters 311 to 31n are sequentially applied to the pixel electrodes P11 to Pmn corresponding to the gate lines G1 to Gm. An image for one screen is displayed.

  Further, for example, when SHORT becomes H level during the period T7 and the short-circuit transfer gate 344 is turned ON to short-circuit the capacitive elements 351 and 352, the voltage between both terminals of the capacitive elements 351 and 352 is reduced. Becomes the average voltage before short circuit. This average voltage is stochastically almost the same voltage as the counter electrode 101.

  Therefore, the source lines S1 to Sn are connected to these capacitive elements 351 and 352 in the period T2 or the period T5 as described above, and further thereafter, the source lines S1 to Sn are connected to the counter electrode 101. As a result, the voltages of the source lines S1 to Sn can be lowered or raised. Therefore, it is possible to reduce power consumed when an image signal voltage corresponding to image data is next applied.

  In the above example, the voltage of the source lines S1 to Sn has been described as positive or negative for convenience, but this is relative to the potential of the counter electrode 101, and thus, for example, a reference of a predetermined power source Even if the potential and ground potential are both positive and negative, the mechanism for reducing power consumption is the same.

  In addition, although the potential of the counter electrode 101 has been described as being constant, the voltage of the source lines S1 to Sn may be changed to be negative by changing the potential. The general behavior is the same.

  In the above example, the other end side of the capacitive elements 351 and 352 is connected to the counter electrode 101. However, the present invention is not limited to this. That is, even when connected to a potential different from that of the counter electrode 101, only the charge accumulated in the capacitor elements 351 and 352 increases or decreases according to the potential difference between the potential and the potential of the counter electrode 101 as described above. The operation is the same. Here, when connected to the counter electrode 101 as described above, when one end side of the capacitive elements 351 and 352 is short-circuited, the potential on the one end side is the same as the counter electrode 101, that is, the other end. The same potential as the side. Therefore, when the other end sides of the capacitive elements 351 and 352 are connected to the counter electrode 101 as described above, instead of the short circuit, the both end sides of the capacitive elements 351 and 352 are individually short-circuited, respectively. -The electric charge accumulated in 352 may be discharged.

  Further, in order to short-circuit the capacitive elements 351 and 352, instead of using the short-circuit transfer gate 344 as described above, a positive capacitive element transfer gate 341 and a negative capacitive element transfer gate 342 are provided. You may make it turn ON simultaneously.

  Further, the period during which the capacitive elements 351 and 352 are short-circuited is not limited to the period T7, and any period of T3, 4 and 6, that is, the capacitive elements 351 and 352 are all separated from the source lines S1 to Sn. Any period may be used.

  Further, the connection relationship of the transfer gates 321... Is not limited to the above, and may be configured as shown in FIG. In the example shown in the figure, the source lines S1 to Sn are connected to the positive capacitive element 351 via the connection line transfer gates 361 to 36n, the source line connection line 360, and the positive capacitive element transfer gate 341. The connection line transfer gates 371 to 37n, the source line connection line 370, and the negative capacity element transfer gate 342 are connected to the negative capacity element 352. The source line connection lines 360 and 370 are connected to the counter electrode 101 via the counter electrode transfer gates 381 and 382, respectively. Even in such a configuration, substantially the same operation is performed by controlling the transfer gates 361, etc. by the control signals CTL1, CTL3 to 5, SELH, SELL, and SHORT as shown in FIG. Power consumption can be reduced.

  Further, when the source lines S1 to Sn are connected to the capacitor elements 351 and 352 and the counter electrode 101 (periods T2, T3, T5, T6, etc.), the gate line of one pixel to be written next, for example, a gate line If a drive pulse from the gate driver 200 is applied to G2 to turn on the pixel switches T21 to T2n, charge accumulation between the capacitive elements 351 and 352 is similarly performed with respect to the liquid crystal capacitance of these pixels. Can supply.

  Further, the parasitic capacitance of the source lines S1 to Sn is also generated between the source lines S1 to Sn and the gate lines G1 to Gm. Therefore, instead of connecting the source lines S1 to Sn to the counter electrode 101, they may be connected to the gate lines G1 to Gm to prevent an increase in power consumption due to the parasitic capacitance. However, in this case, in order to separate the gate driver 200 from each of the gate lines G1 to Gm, it is necessary to provide a transfer gate similar to the DA connection transfer gates 321 to 32n, and a plurality of gate lines G1. When Gm is connected to the source lines S1 to Sn, it is necessary to use pixel switches T11 to Tmn that are turned off when the source-gate voltage is 0V.

  Further, in addition to the above-described line inversion driving, when column inversion driving in which an image signal voltage having a reverse polarity is applied to each of adjacent source lines S1 to Sn is applied, for example, as shown in FIG. In addition, the source line connection line 330, the connection line transfer gates 331 to 33n, the capacitor elements 351 and 352, and the like may be provided separately for odd columns and even columns.

  Each time writing to the pixel electrodes P11 to P1m is performed as described above, not only one of the positive capacitive element 351 and the negative capacitive element 352 is connected to the source lines S1 to Sn but also one of the capacitances. After the elements are connected and the counter electrode 101 is connected, the other capacitor element may be further connected. In this case, the sequence increases while the voltages from the DA converters 311 to 31n are applied. However, charge accumulation and supply by the capacitive elements 351 and 352 are performed more efficiently, so that power consumption can be further reduced. Can do. Further, instead of sequentially connecting the two capacitive elements 351 and 352, if both terminals of one capacitive element are alternately switched and connected, the positive capacitive element 351 and the negative capacitive element 352 are connected. Since it can be used also, it is possible to reduce the circuit scale. Further, the reduction in circuit scale by alternately switching and connecting the two terminals of one capacitive element in this way is also effective when the connection to the counter electrode 101 is not performed.

(Embodiment 2)
As a second embodiment of the present invention, a liquid crystal driving device capable of further reducing power consumption will be described. In the second embodiment, for convenience of explanation, an example in which a binary image is displayed by applying two types of relatively high and low voltages having the same polarity to the counter electrode 101 to the pixel electrodes P11 to Pmn. explain. Further, the movement of charges will be described as the movement of positive charges. In the following embodiments, components having the same functions as those in the first embodiment and the like are denoted by the same reference numerals and description thereof is omitted.

  FIG. 6 is a circuit diagram schematically showing a configuration of a main part of a liquid crystal display device including a source driver 400 (liquid crystal driving device) according to the second embodiment.

  In the source driver 400, the source lines S1 to Sn are connected to the high voltage capacitive element 431 via the high voltage transfer gates 411 to 41n, while the low voltage transfer gates 421 to 42n are used. The capacitor element 432 is connected. The high voltage transfer gates 411 to 41n and the low voltage transfer gates 421 to 42n are controlled by a switching control unit 441 to 44n. That is, it is similar to the modification of the first embodiment (FIG. 3) in that the source lines S1 to Sn are connected to the capacitive elements 431 and 432 via the transfer gates 411, 421. The transfer gates 411... Are largely controlled by the switching control units 441 to 44n.

  For example, as shown in FIG. 7, the switching control units 441 to 44n are configured to include two AND circuits 441a, 441b..., And image data signals input from the data latches 451 to 45n to the DA converters 311 to 31n, The high voltage transfer gates 411 to 41n or the low voltage transfer gates 421 to 42n are selectively turned on according to the control signal CTL6. In addition, the timing control unit 401 outputs control signals CTL1 and CTL6.

  The liquid crystal display device configured as described above responds to image data between each of the pixel electrodes P11 to Pmn and the counter electrode 101 by the following operation corresponding to the change of each control signal shown in FIG. The image signal voltage is held (written). Here, as an example of the displayed image, a checkered pattern image in which the brightness is inverted for each pixel adjacent vertically and horizontally will be described as an example.

(Period T1)
In this period, for example, writing to the pixel electrodes P11 to P1n is performed in the same manner as in the first embodiment (FIG. 2). That is, when an image signal voltage corresponding to the image data signal output from the data latches 451 to 45n is output from the DA converters 311 to 31n, and CTL1 becomes H level and the DA connection transfer gates 321 to 32n are turned ON. The image signal voltage is applied to the source lines S1 to Sn. Therefore, when the gate line G1 is driven to the H level, the pixel switches T11 to T1n are turned on and the image signal voltages are applied to the pixel electrodes P11 to P1n, and the pixel electrodes P11 to P1n and the counter electrode 101 are connected. Of liquid crystal capacity. On the other hand, since CTL6 is at L level during this period T1, AND circuits 441a, 441b... Of the switching control units 441 to 44n output L level signals regardless of the image data signals output from the data latches 451 to 45n. The high voltage transfer gates 411 to 41n and the low voltage transfer gates 421 to 42n are all turned off.

(Period T2)
Next, when CTL1 becomes L level and CTL6 becomes H level, the DA connection transfer gates 321 to 32n are turned off, and the high voltage transfer gates 411 to 41n or the low voltage transfer gates 421 to 42n are data latches 451. Are turned on in response to image data signals from .about.45n, and each source line S1.about.Sn is connected to either the high voltage capacitive element 431 or the low voltage capacitive element 432.

  More specifically, in the example of FIG. 8, for example, the output of the data latch 451 is at the L level, so that an L level signal is output from the AND circuit 441a of the switching control unit 441 and the high voltage transfer gate 411 is turned off. The AND circuit 441b outputs an H level signal, the low voltage transfer gate 421 is turned on, and the source line S1 is connected to the low voltage capacitor 432. Therefore, positive charges accumulated in the low-voltage capacitor 432 are supplied to the source line S1, and the potential of the source line S1 rises (symbol A in FIG. 8).

  For example, since the output of the data latch 452 is at the H level, an H level signal is output from the AND circuit 442a of the switching control unit 442 and the high voltage transfer gate 412 is turned on, while the AND circuit 442b is at the L level. The low voltage transfer gate 422 is turned off, and the source line S2 is connected to the high voltage capacitor 431. Therefore, the positive charge held in the source line S2 moves to and accumulates in the high voltage capacitive element 431, and the potential of the source line S2 decreases (symbol B in FIG. 8).

(Period T3)
Thereafter, when a latch signal (not shown) is input to the data latches 451 to 45n while CTL1 remains at L level and CTL6 remains at H level, the image data signal of each pixel corresponding to the next gate line G2 is latched and switched. It inputs into the control parts 441-44n. (Note that the latched image signal is also input to the DA converters 311-31n, but since the DA connection transfer gates 321-32n remain OFF, the potential of the source lines S1-Sn is not affected.)
Therefore, for example, in the example of FIG. 8, since the signal latched and output by the data latch 451 is H level, an H level signal is output from the AND circuit 441a of the switching control unit 441, and the high voltage transfer gate 411 is turned ON. On the other hand, an L level signal is output from the AND circuit 441b, the low voltage transfer gate 421 is turned OFF, and the source line S1 is connected to the high voltage capacitor 431. Therefore, positive charges accumulated in the high-voltage capacitive element 431 are supplied to the source line S1, and the potential of the source line S1 further increases (symbol C in FIG. 8).

  Since the output of the data latch 452 is L level, an L level signal is output from the AND circuit 442a of the switching control unit 442 and the high voltage transfer gate 412 is turned OFF, while the AND circuit 442b outputs an H level signal. Is output, the low-voltage transfer gate 422 is turned on, and the source line S2 is connected to the low-voltage capacitive element 432. Therefore, the positive charge held in the source line S2 moves to and accumulates in the low voltage capacitive element 432, and the potential of the source line S2 further decreases (symbol D in FIG. 8).

(Period T4)
As described in the period T1, the writing to the pixel electrodes P21 to P2n is performed. That is, when CTL6 becomes L level and the transfer gates 411 to 41n and 421 to 42n are all turned OFF, and when CTL1 becomes H level, the DA connection transfer gates 321 to 32n are turned ON, and the DA converters 311 to 31n The output image signal voltage is applied to the source lines S1 to Sn.

  Specifically, for example, since the output of the data latch 451 is at the H level, a high voltage is applied to the source line S1 and the pixel electrode P21. Here, for example, as described above, since the potential of the source line S1 rises in the periods T2 and T3 (symbol C in FIG. 8), the DA converter 311 generates charges corresponding to the potential difference indicated by the symbol E in FIG. Just supply.

(After period T5)
Hereinafter, by repeating the same operations as in the above-described periods T2 to T4, the image signal voltages output from the DA converters 311 to 31n are sequentially applied to the pixel electrodes P11 to Pmn corresponding to the gate lines G1 to Gm, An image for one screen is displayed.

  As in the above-described periods T2 and T5, the source lines S1 to Sn are connected to the high voltage capacitor element 431 according to the potential of the source lines S1 to Sn, that is, according to the voltage applied to the pixel electrodes P11 to Pmn immediately before. By selectively being connected to the low-voltage capacitor element 432, charge accumulation in the high-voltage capacitor element 431 and the low-voltage capacitor without causing unnecessary charge transfer between the source lines S1 to Sn. Charge can be supplied from the element 432. That is, the charges held in the high-potential source lines S1 to Sn are accumulated in the high-voltage capacitor element 431, and the low-potential source lines S1 to Sn are supplied with charges from the low-voltage capacitor element 432. Rises. Further, as in the subsequent periods T3 and T6, the high voltage capacitor 431 or the low voltage capacitor 432 is selectively connected in accordance with the voltage applied to the source lines S1 to Sn next, so that The source lines S1 to Sn to which a high voltage is applied are supplied with charges from the high voltage capacitive element 431, and the potential further rises, while the source lines S1 to Sn to which a low voltage is applied next are held. The charge is accumulated in the low voltage capacitor element 432. Therefore, the electric power held in the source lines S1 to Sn can be effectively accumulated and used so that the power consumption can be reduced.

  In the above example, the case where the present invention is applied to a liquid crystal display device that displays a binary image has been described. However, the present invention is not limited to this, and the present invention can be similarly applied to a case where a multi-value image is displayed. In this case, the most significant bit (MSB) signal of the image data may be used as a signal input to the switching control units 441 to 44n, or three or more capacitive elements may be provided, Using a plurality of bits of signals, that is, by dividing the applied voltage into a plurality of groups and connecting the source lines S1 to Sn to the capacitive elements corresponding to each group, charge can be stored and supplied more efficiently. It may be performed.

In addition, an example in which voltages having the same polarity are applied to the pixel electrodes P11 to Pmn with respect to the counter electrode 101 has been described. The present invention can also be applied to the case of line inversion driving in which is inverted. That is, for example, when a binary image is displayed by line inversion driving, it can be considered in the same way as when a quaternary image is displayed. For example, when the potential of the counter electrode is 8 V,
+ H = 16V
+ L = 9V
-L = 7V
-H = 0V
Then, as shown in FIG. 9, a + H capacitive element 461, a + L capacitive element 462, a -L capacitive element 463, a -H capacitive element 464, and transfer gates 471 to 474 are provided. If the source lines S1 to Sn are connected in association with the + H, + L, -L, or -H voltage, the potential of the image signal is higher or lower than the potential of the counter electrode. Also in this case, power consumption can be reduced by the same mechanism as described above.

  Further, when column inversion driving in which image signal voltages having opposite polarities are applied to the adjacent source lines S1 to Sn is applied, the polarity of the source lines S1 to Sn and the voltage level are similarly changed. Thus, it may be connected to the corresponding capacitor element.

(Embodiment 3)
As a third embodiment of the present invention, a liquid crystal driving device capable of further reducing power consumption will be described. Also in the third embodiment, as in the second embodiment, two types of voltages having the same polarity with respect to the counter electrode 101 are applied to the pixel electrodes P11 to Pmn to display a binary image. An example will be described.

  FIG. 10 is a circuit diagram schematically showing a configuration of a main part of a liquid crystal display device including a source driver 500 (liquid crystal driving device) according to the third embodiment.

  Compared to the source driver 400 of the second embodiment, the source driver 500 includes switching control units 541 to 54n instead of the switching control units 441 to 44n, and includes data latches in addition to the data latches 451 to 45n. The difference is that 551 to 55n are provided. The data latches 551 to 55n hold the image data input from the data latches 451 to 45n to the DA converters 311 to 31n next.

  Further, for example, as shown in FIG. 11, the switching control units 541 to 54n are configured to include NOR circuits 541a,..., Latch circuits 541b, and AND circuits 541c and 541d, and include data latches 451 to 45n and data. The high-voltage transfer gates 411 to 41n or the low-voltage transfer gates 421 to 42n are selectively turned on according to the image data signal input from the latches 551 to 55n and the control signal CTL6. Yes. More specifically, for example, the switching control unit 541 selects either the transfer gate 411 or the low-voltage transfer gate 421 according to the output from the data latch 451 only when the outputs of the data latch 451 and the data latch 551 are different from each other. It is supposed to turn on.

  The liquid crystal display device configured as described above responds to image data between each of the pixel electrodes P11 to Pmn and the counter electrode 101 by the following operation corresponding to the change of each control signal shown in FIG. The image signal voltage is held (written). Here, as an example of the displayed image, a checkered pattern image in which the brightness is inverted for each pixel adjacent vertically and horizontally will be described as an example.

(Period T1)
In this period, for example, writing to the pixel electrodes P11 to P1n is performed in the same manner as in the first and second embodiments (FIGS. 2 and 8). That is, when an image signal voltage corresponding to the image data signal output from the data latches 451 to 45n is output from the DA converters 311 to 31n, and CTL1 becomes H level and the DA connection transfer gates 321 to 32n are turned ON. The image signal voltage is applied to the source lines S1 to Sn. Therefore, when the gate line G1 is driven to the H level, the pixel switches T11 to T1n are turned on and the image signal voltages are applied to the pixel electrodes P11 to P1n, and the pixel electrodes P11 to P1n and the counter electrode 101 are connected. Of liquid crystal capacity. On the other hand, during this period T1, since CTL6 is at L level, the AND circuits 541c, 541d... Of the switching control units 541 to 54n are not related to the image data signals output from the data latches 451 to 45n and the data latches 551 to 55n. An L level signal is output, and the high voltage transfer gates 411 to 41n and the low voltage transfer gates 421 to 42n are all turned OFF. Therefore, none of the source lines S1 to Sn is connected to the capacitive elements 431 and 432.

(Period T2)
Next, when CTL1 becomes L level and CTL6 becomes H level, the DA connection transfer gates 321 to 32n are turned off, and the high voltage transfer gates 411 to 41n or the low voltage transfer gates 421 to 42n are data latches 451. To 45 n and the image data signals from the data latches 551 to 55 n, and each source line S 1 to Sn is connected to either the high voltage capacitor 431 or the low voltage capacitor 432.

  More specifically, in the example of FIG. 12, for example, the output of the data latch 451 is L level and the output of the data latch 551 is H level, so the output of the NOR circuit 541a of the switching control unit 541 is sent to the latch circuit 541b by a latch signal (not shown). When held and output, the AND circuit 541c outputs an L level signal and the high voltage transfer gate 411 is turned OFF, while the AND circuit 541d outputs an H level signal and outputs a low voltage signal. The transfer gate 421 is turned on, and the source line S1 is connected to the low voltage capacitor 432. Therefore, positive charges accumulated in the low-voltage capacitor element 432 are supplied to the source line S1, and the potential of the source line S1 rises.

  For example, since the output of the data latch 452 is H level and the output of the data latch 552 is L level, an H level signal is output from the AND circuit 542c of the switching control unit 542 and the high voltage transfer gate 412 is turned ON. On the other hand, an L level signal is output from the AND circuit 542d, the low voltage transfer gate 422 is turned OFF, and the source line S2 is connected to the high voltage capacitor 431. Therefore, the positive charge held in the source line S2 moves to and accumulates in the high voltage capacitive element 431, and the potential of the source line S2 decreases.

  That is, when the applied voltage changes from a low voltage to a high voltage, the source lines S1 to Sn are connected to the low voltage capacitor 432 and supplied with the charges accumulated in the low voltage capacitor 432. When the voltage changes from a high voltage to a low voltage, charges connected to the high voltage capacitor element 431 and stored in the source lines S1 to Sn are accumulated in the high voltage capacitor element 431. On the other hand, when the voltage applied to the source lines S1 to Sn does not change, the NOR circuit 541a and the like of the switching control units 541 to 54n (and therefore the latch circuit 541b) regardless of whether the voltage is a high voltage or a low voltage. Etc.) is at the L level, the source lines S1 to Sn are not connected to any of the capacitive elements 431 and 432, and the same voltage is maintained. Therefore, for such source lines S1 to Sn, useless charge movement does not occur, so that the charge utilization efficiency is improved.

(Period T3)
Thereafter, when a latch signal (not shown) is input to the data latches 451 to 45n and the data latches 551 to 55n while the CTL1 remains at the L level and the CTL6 remains at the H level, the next data held in the data latches 551 to 55n The image data signal of each pixel corresponding to the gate line G2 is latched by the data latches 451 to 45n and input to the switching control units 541 to 54n. Further, the next image data signal is further latched in the data latches 551 to 55n. (Note that the latch timing to the data latches 551 to 55n is not necessarily the same as that of the data latches 451 to 45n, but may be any timing until the next latch by the data latches 451 to 45n is performed. )
Therefore, for example, in the example of FIG. 12, the signal latched and output by the data latch 451 becomes H level, so that an H level signal is output from the AND circuit 541c of the switching control unit 541 and the high voltage transfer gate 411 is turned on. On the other hand, an L level signal is output from the AND circuit 541d, the low voltage transfer gate 421 is turned OFF, and the source line S1 is connected to the high voltage capacitor 431. Therefore, positive charges accumulated in the high voltage capacitor element 431 are supplied to the source line S1, and the potential of the source line S1 further rises.

  On the other hand, since the output of the data latch 452 is at the L level, an L level signal is output from the AND circuit 542c of the switching control unit 542 and the high voltage transfer gate 412 is turned OFF, while the AND circuit 542d is at the H level. The low-voltage transfer gate 422 is turned on, and the source line S2 is connected to the low-voltage capacitor 432. Therefore, the positive charge held in the source line S2 moves to and accumulates in the low voltage capacitive element 432, and the potential of the source line S2 further decreases.

  Further, for the source lines S1 to Sn whose voltages to be applied next do not change, the outputs of the latch circuits 541b... Are maintained at the L level, so that they are not connected to any of the capacitive elements 431 and 432 and are the same. Maintained at voltage. Therefore, for such source lines S1 to Sn, useless charge transfer does not occur, and the charge accumulated in the positive capacitive element transfer gate 341 is applied from a low voltage. Since charges are supplied only to the source lines S1 to Sn that change to a high voltage, charges are used more efficiently.

(Period T4)
As described in the period T1, the writing to the pixel electrodes P21 to P2n is performed. That is, when CTL6 becomes L level and the transfer gates 411 to 41n and 421 to 42n are all turned OFF, and when CTL1 becomes H level, the DA connection transfer gates 321 to 32n are turned ON, and the DA converters 311 to 31n The output image signal voltage is applied to the source lines S1 to Sn.

  Specifically, for example, since the output of the data latch 451 is at the H level, a high voltage is applied to the source line S1 and the pixel electrode P21. Here, for example, as described above, since the potential of the source line S1 rises in the periods T2 and T3, the DA converter 311 supplies charges corresponding to the potential difference between the potential and the potential output from the DA converter 311. Just do it. Further, the source lines S1 to Sn whose voltages to be applied next do not change from before are not connected to any of the capacitive elements 431 and 432 at T2 and T3 as described above, and the held voltage does not change. Even when a voltage is applied from the DA converters 311 to 31n to the source lines S1 to Sn, almost no current flows and no power is consumed.

(After period T5)
Hereinafter, by repeating the same operations as in the above-described periods T2 to T4, the image signal voltages output from the DA converters 311 to 31n are sequentially applied to the pixel electrodes P11 to Pmn corresponding to the gate lines G1 to Gm, An image for one screen is displayed.

  Only when the voltage applied immediately before the pixel electrodes P11 to Pmn is different from the voltage applied next, as in the above-described periods T2 and T5, the source lines S1 to Sn according to the voltage applied immediately before. Is selectively connected to the high-voltage capacitor element 431 or the low-voltage capacitor element 432, so that useless charges are generated between the source lines S 1 to Sn and between the source lines S 1 to Sn and the capacitor elements 431 and 432. Charge accumulation and supply can be performed without causing movement. Further, only when the voltage applied immediately before the pixel electrodes P11 to Pmn is different from the voltage applied next, as in the following periods T3 and T6, the voltage is applied to the source lines S1 to Sn next. By selectively connecting to the high-voltage capacitor element 431 or the low-voltage capacitor element 432 in accordance with the voltage to be stored, the charge can be stored and supplied without causing unnecessary charge movement. it can. Therefore, the electric power held in the source lines S1 to Sn can be more effectively accumulated and used so that the power consumption can be reduced. Furthermore, since the same voltage is maintained without being connected to any of the capacitive elements 431 and 432 for the source lines S1 to Sn whose applied voltage does not change, even if a voltage is applied from the DA converters 311 to 31n. Little current flows and no power is consumed.

  Note that, in the third embodiment, as described in the second embodiment, three or more capacitive elements are provided to apply to a liquid crystal display device that displays a multi-valued image, or line inversion. The present invention may also be applied to a liquid crystal display device using a column inversion driving method.

  Also, the circuit configuration is not limited to the above, and for example, as shown in FIG. 13, data latches 451 to 45n may be provided between the data latches 551 to 55n and the switching control units 541 to 54n. That is, in this case, the values held by the data latches 451 to 45n and the data latches 551 to 55n are updated before the period T2, and only the values held by the data latches 451 to 45n when the period T3 is reached. For example, it may be updated.

(Embodiment 4)
FIG. 14 is a circuit diagram schematically showing a configuration of a main part of a liquid crystal display device including a source driver 600 (liquid crystal driving device) according to the fourth embodiment.

  Although the source driver 600 has a configuration similar to that of the second embodiment (FIG. 6), no capacitor is provided, and only the source lines S1 to Sn are connected to the first transfer gates 611 to 611. 61n or the second transfer gates 621 to 62n and the source line connection line 610 or the source line connection line 620 are connected to each other. Further, the source lines S1 to Sn are divided into two groups, a first group and a second group, and a switching control unit 44n-1 corresponding to the second group, for example, the source lines Sn-1, Sn,. ... 44n is inputted with a signal obtained by inverting the output from the data latches 45n-1, 45n,... By NOT circuits 63n-1, 63n,. That is, the source lines S1... And the source lines Sn... Of each group are connected to the opposite source line connection lines 610 and 620 for the same image data. More specifically, for example, as shown in FIG. 15, after the writing to the pixel electrodes P11 to P1n is performed in the period T1, as in the first embodiment, the data in the first group is written in the period T2. When the outputs of the latches 451 are at the L level, the first transfer gates 611 are turned off and the second transfer gates 621 are turned on, while in the second group, the outputs of the data latches 45n are at the L level. In this case, the first transfer gates 61n are turned on, and the second transfer gates 62n are turned off.

  With the configuration as described above, for example, a case where one display line is configured with 10 pixels as illustrated in FIG. 16 will be described. In the period T2, the low voltage among the left five pixels in the period T1. The source line corresponding to the pixel to which the voltage is applied and the source line corresponding to the pixel to which the high voltage is applied among the right five pixels are short-circuited, while the pixel to which the high voltage is applied among the left five pixels And the source line corresponding to the pixel to which the low voltage is applied among the five pixels on the right side are short-circuited to each other, and each source line connected to each other is held in each source line. The charge is averaged. Therefore, for example, the charge held in the source line to which a high voltage is applied is 6 (unit is a unit proportional to coulomb), the charge held in the source line to which a low voltage is applied is 0, and pattern 1 in FIG. When a voltage as shown in FIG. 2 is applied, the high voltage is applied in the periods T1 and T3, the charges held in the third source line from the right are both 6, and the charges are held in the source line in the period T2. Since the charge is 1, only the difference of 5 is supplied from the power source. On the other hand, as shown in the figure, if all the source lines are short-circuited regardless of the level of the applied voltage in the period T2, the charge held in the third source line from the right is 0.6. Thus, only 5.4 charges are supplied from the power supply in the period T3, so that the power consumption is reduced by an amount corresponding to 0.4 charges by short-circuiting by grouping as described above. be able to. Similarly, in the other patterns 2 to 5 shown in FIG. 16, the power consumption can be reduced as compared with the case where all the source lines are short-circuited.

  Here, depending on the display pattern, the power consumption is not necessarily reduced by the grouping as described above, but the correlation of the display pattern between the corresponding pixels in the display lines adjacent to each other as shown in FIG. Such a high display is often used, for example, on a computer screen or the like on which many window displays or ruled lines are displayed, and is particularly effective in reducing power consumption when such display is performed. In addition, since it is not necessary to provide a capacitor as described above, the circuit scale can be reduced. Furthermore, since the first transfer gates 611 to 61n and the like need only be kept in a single switching state while CTL1 is at the L level, the period can be easily shortened.

  In the above example, each pixel of the display line is divided into left and right groups and grouped. However, the present invention is not limited to this. For example, the pixels may be grouped into odd-numbered pixels and even-numbered pixels. Alternatively, the pixels may be grouped for each of a plurality of adjacent pixels, or each group may be configured with pixels at random positions.

  In the above example, an example in which a signal inverted by the NOT circuits 63n-1, 63n,... Is input to some of the switching controllers 44n-1, 44n, is not limited to this. The signals output from the first transfer gates 61n-1, 61n,... To the first transfer gates 62n-1, 62n,.

  Also in the fourth embodiment, three or more source line connection lines 610 and the like may be provided and applied to a liquid crystal display device on which a multi-value image is displayed. In addition, at that time, whether or not the voltages applied to the source lines S1 to Sn are the same or not, whether or not there is connection to the source line connection lines 610. It may be controlled.

(Embodiment 5)
FIG. 17 is a circuit diagram schematically showing a configuration of a main part of a liquid crystal display device including a source driver 700 (liquid crystal driving device) according to the fifth embodiment.

  The source driver 700 is configured such that the source lines S1 to Sn are connected via the source line connection transfer gates 711 to 71n and the source line connection line 710. The source line connection transfer gates 711 to 71n are controlled by switching control units 721 to 72n, respectively. As shown in FIG. 18, the switching control units 721 to 72n are configured to include NOR circuits 721a ... and AND circuits 721b ..., and CTL6 is at the H level and outputs from the data latches 451-45n. When the output from the data latches 551 to 55n is different, that is, only when the voltage applied to the source lines S1 to Sn changes, the source line connection transfer gates 711 to 71n are turned on. ing.

  With the configuration as described above, L level signals are output from the switching control units 721 to 72n in the source lines S1 to Sn in which the voltage applied to write data one after another does not change, and the source lines Since the connection transfer gates 711 to 71n are turned off, there is no useless transfer of charges between the other source lines S1 to Sn, and the same voltage as the held voltage is applied from the DA converters 311 to 31n. As a result, almost no current flows and no power is consumed. In addition, between the source lines S1 to Sn in which the applied voltage changes, an L level signal is output from the switching control units 721 to 72n, the source line connection transfer gates 711 to 71n are turned on, and the source line connection line 710 are connected to each other through the high voltage source line 710, the charge moves from the high voltage source lines S1 to Sn to the low voltage source lines S1 to Sn, that is, the source lines S1 to Sn to which the next high voltage is applied. When a voltage is applied, the current flowing from the power supply can be reduced, and thus power consumption can be kept small. Moreover, since it is not necessary to provide a capacitive element as in the fourth embodiment, the circuit scale can also be kept small. Furthermore, since it is only necessary to keep the source line connection transfer gates 711 to 71n in a single switching state while CTL1 is at the L level, it is also easy to shorten the period.

  Also in the fifth embodiment, when a multi-value image is displayed, whether or not there is connection to the source line connection line 710 depending on the difference in voltage applied to the source lines S1 to Sn before and after. It may be controlled.

  In addition, if all the source lines S1 to Sn whose applied voltage changes as described above are connected to each other, the source lines S1 to Sn can be easily set to an average potential. For example, a source driver 800 as shown in FIG. 19 may be provided so that different source line connection lines are connected depending on whether the applied voltage changes to a high voltage or a low voltage. In this source driver 800, the transfer gates 611 to 61n and 621 to 62n similar to those in the fourth embodiment (FIG. 14) for connecting the source lines S1 to Sn to the source line connection lines 610 and 620 are the same as those in the embodiment. It is controlled by the switching control units 541 to 54n similar to the third mode (FIG. 10). Further, the switching control units 54n-1, 54n,... Corresponding to the source lines Sn-1, Sn,... Of the second group receive the outputs from the data latches 45n-1, 55n-1,. Inverted signal is input. Accordingly, as shown in FIG. 20, the source line S1... Where the applied voltage changes to a high voltage in the first group, the source line Sn... Where the applied voltage changes to a low voltage in the second group, and the first. The source lines S2... In which the applied voltage changes to a low voltage in the group and the source lines Sn-1... In which the applied voltage changes to a high voltage in the second group are connected to each other. Also, the voltage can be averaged to reduce the current flowing in the source line to which the next high voltage is applied.

  The liquid crystal drive device according to the present invention connects the source line to the capacitive element and then connects it to the counter electrode, according to the image data signal, and further according to the change of the image data signal before and after the source line. It is easy to significantly reduce power consumption by switching the capacitive elements connected to each other or by selectively connecting source lines to each other in accordance with changes in image data signals and successive image data signals. It is possible to reduce the time required to store and supply charges and reduce the circuit scale, and the voltage corresponding to the image data is applied to the pixel electrode via the source line and the pixel switch. A liquid crystal display using a so-called active matrix liquid crystal panel that displays an image by applying charge and accumulating charge between the pixel electrode and the counter electrode. It is useful as a liquid crystal driving device for driving the device.

4 is a circuit diagram illustrating a configuration of a liquid crystal display device according to Embodiment 1. FIG. 3 is a timing chart showing the operation of the liquid crystal display device. 6 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a modification of the first embodiment. FIG. 3 is a timing chart showing the operation of the liquid crystal display device. FIG. 10 is a circuit diagram illustrating a configuration of a main part of a liquid crystal display device according to another modification of the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a second embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a switching control unit. 3 is a timing chart showing the operation of the liquid crystal display device. FIG. 10 is a circuit diagram illustrating a configuration of a main part of a liquid crystal display device according to a modification of the second embodiment. FIG. 5 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a third embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a switching control unit. 3 is a timing chart showing the operation of the liquid crystal display device. FIG. 10 is a circuit diagram illustrating a configuration of a main part of a liquid crystal display device according to a modification of the third embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a fourth embodiment. 3 is a timing chart showing the operation of the liquid crystal display device. FIG. 11 is an explanatory diagram showing a specific operation example of the liquid crystal display device. FIG. 10 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a fifth embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a switching control unit. FIG. 10 is a circuit diagram illustrating a configuration of a liquid crystal display device according to a modification of the fifth embodiment. 3 is a timing chart showing the operation of the liquid crystal display device. It is a circuit diagram which shows the structure of the conventional liquid crystal display device.

Explanation of symbols

G1-Gm Gate line
S1 to Sn source line L11 to Lmn Liquid crystal layer P11 to Pmn Pixel electrode T11 to Tmn Pixel switch 100 Liquid crystal panel 101 Counter electrode 200 Gate driver 300 Source driver 301 Timing control unit 311 to 31n DA converter 321 to 32n DA connection transfer gate 330 Source Line connection line 331 to 33n Connection line transfer gate 341 Positive capacitive element transfer gate 342 Negative capacitive element transfer gate 343 Counter electrode transfer gate 344 Short circuit transfer gate 351 Positive capacitive element 352 Negative capacitive element 360 Source Line connection line 361 to 36n Connection line transfer gate 370 Source line connection line 371 to 37n Connection line transfer gate 381/3 82 Counter electrode transfer gate 400 Source driver 401 Timing control unit 411 to 41n High voltage transfer gate 421 to 42n Low voltage transfer gate 431 High voltage capacitor 432 Low voltage capacitor 441 to 44n Switching control unit 441a AND circuit 441b AND circuit 451 to 45n Data latch 461 + H capacitive element 462 + L capacitive element 463 -L capacitive element 464 -H capacitive element 471 to 47n switching control unit 471a and 471b AND circuit 500 source driver 541 to 54n switching control unit 541a NOR circuit 541b Latch circuit 541c AND circuit 541d AND circuit 551-55n Data latch 600 Source driver 610 Source line connection line 611-61n Transfer gate 620 source lines connecting line 621~62n second transfer transfer gate 700 source driver 710 source lines connecting line 711~71n source line connected gate 721~72n switching control unit 721a NOR circuit 721b the AND circuit 800 Source driver

Claims (7)

The pixel electrode in a liquid crystal display device having a source line, a pixel switch, a pixel electrode connected to the source line via the pixel switch, and a counter electrode provided to face the pixel electrode; A liquid crystal driving device that applies a voltage according to image data for each pixel via a source line,
A plurality of charge storage means for storing charge;
Charge storage means connecting / disconnecting means for connecting / disconnecting the source line and the charge storage means;
After applying a first voltage corresponding to the previous image data to the pixel electrodes, before applying the second voltage corresponding to the next image data to the pixel electrodes,
After connecting the source line to one of the plurality of charge storage means selected according to the first voltage at a first timing,
Control means for controlling each source line to connect the source line to one of the plurality of charge storage means selected according to the second voltage at a second timing;
A liquid crystal driving device comprising: The liquid crystal driving device according to claim 1 ,
The image data is multi-value image data,
Each of the plurality of charge storage units is provided corresponding to a voltage group in which one or more voltages applied to the pixel electrode according to the multi-value image data are grouped.
The control means includes
At the first timing, the source line is connected to the charge storage means corresponding to the voltage group including the first voltage,
2. A liquid crystal driving device according to claim 1, wherein the source line is controlled to be connected to the charge storage means corresponding to the voltage group including the second voltage at the second timing. The liquid crystal driving device according to claim 1 ,
The image data is binary image data,
The plurality of charge storage means includes a high voltage charge storage means corresponding to a voltage applied to the pixel electrode according to the binary image data, and a low voltage charge storage means,
The control means includes
At the first timing, the source line is connected to the high voltage charge storage means or the low voltage charge storage means corresponding to the first voltage,
And controlling the source line to be connected to the high voltage charge storage means or the low voltage charge storage means corresponding to the second voltage at the second timing. . A liquid crystal driving device according to any one of claims 1 to 3 ,
The control means controls the presence or absence of connection between the source line and the charge storage means at the first timing and the second timing according to the first voltage and the second voltage. A liquid crystal driving device. The liquid crystal driving device according to claim 4 ,
The control means determines the connection between the source line and the charge storage means at the first timing and the second timing when a difference between the first voltage and the second voltage is a predetermined value or more. A liquid crystal drive device characterized by being controlled to The pixel electrode in a liquid crystal display device having a source line, a pixel switch, a pixel electrode connected to the source line via the pixel switch, and a counter electrode provided to face the pixel electrode; A liquid crystal driving device that applies a voltage according to image data for each pixel via a source line,
A source line connecting line for connecting the source lines,
A connecting line connecting / disconnecting means for connecting / disconnecting the source line and the source line connecting line;
After applying a first voltage corresponding to the previous image data to the pixel electrodes, before applying the second voltage corresponding to the next image data to the pixel electrodes,
Control means for controlling each source line so as to connect the source line to the source line connection line according to the first voltage and the second voltage;
A liquid crystal driving device comprising: The liquid crystal driving device according to claim 6 ,
The control means controls the connection between the source line and the source line connection line so as to be performed when a difference between the first voltage and the second voltage is greater than or equal to a predetermined value. Drive device.

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