JP4095396B2 - Timing verification method, timing verification apparatus, program, and recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit timing verification method, a timing verification apparatus, a program, and a recording medium.
[0002]
In the development of a semiconductor integrated circuit, there is a process of performing a delay calculation of the logic circuit and verifying and guaranteeing the operation of the logic circuit by verifying the operation timing and delay. In recent semiconductor integrated circuits, higher integration and higher speed of the circuit and lowering of the operating voltage have been achieved. Therefore, the power supply voltage drop in the chip has a great influence on the delay and fluctuation of the circuit operation, and it is necessary to perform timing verification considering the power supply voltage drop of each instance (cell). Yes.
[0003]
[Prior art]
FIG. 15 is a flowchart showing a conventional timing verification process. Each step shown in the figure is executed by a verification device (not shown).
[0004]
When processing for timing verification is started, circuit information is first read from a predetermined storage device into the verification device (step 201). Then, a floor plan is performed based on the circuit information, and circuit blocks constituting the semiconductor integrated circuit are roughly arranged (step 202).
[0005]
Next, each instance (cell) in the chip is arranged and wired (step 203), and a rough delay value is estimated based on the wiring length and wiring capacity determined by the arrangement and wiring. After that, timing adjustment / verification is performed using the delay value (step 204). If a problem (timing error) occurs as a result of the timing verification, the process returns to step 203 to perform placement and wiring. If no problem occurs, the circuit parasitic capacitance is extracted (Extract). (Step 205).
[0006]
Thereafter, power supply network analysis is performed based on the net list acquired in step 201, the extraction result in step 205, and the like (step 206). Then, the first timing verification is performed based on the analysis result (step 207).
[0007]
If there is a problem as a result of the first timing verification, the process returns to step 203 to perform placement and wiring. If there is no problem, the delay for each cell is determined based on the power supply voltage drop of each cell in the chip. A value is calculated (step 208). Second timing verification is performed based on the delay value (step 209). If a problem occurs as a result of the second timing verification, the process returns to step 203 to perform placement and wiring. If no problem occurs, the timing verification processing of the semiconductor integrated circuit is terminated.
[0008]
In the above processing, the first timing verification (step 207) eliminates the timing error of the circuit operation not considering the power supply voltage drop, and the second timing verification (step 209) determines the circuit operation timing considering the power supply voltage drop. The error is removed. As described above, by performing the first and second timing verification, the convergence to an appropriate operation timing is improved.
[0009]
For example, Patent Document 1, Patent Document 2, and Patent Document 3 disclose conventional techniques for performing timing verification in consideration of a power supply voltage drop.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-321725
[Patent Document 2]
JP 2000-99554 A
[Patent Document 3]
JP 2000-195960 A
[0011]
[Problems to be solved by the invention]
By the way, when the chip size of the semiconductor integrated circuit is small and the power supply voltage drop is relatively small, the power supply voltage drop has a small effect on the circuit operation and delay, so that it becomes a big problem for timing and design in the semiconductor integrated circuit. There wasn't. Therefore, when the power supply voltage drop is relatively small, the method of performing the second timing verification in consideration of the power supply voltage drop at the final stage of the process in which the placement / wiring is determined as in the timing verification process of FIG. The above problem did not occur.
[0012]
However, in recent semiconductor integrated circuits, as the scale and power consumption of the semiconductor integrated circuit increase, the influence on the circuit operation and delay variation due to the power supply voltage drop has become a problem. For this reason, in the method of performing timing verification considering the power supply voltage drop at the final stage as in the above-described conventional technology, it is difficult to change the circuit or change the circuit arrangement to converge at an appropriate timing, In such a case, a timing error may occur.
[0013]
The present invention has been made to solve the above problems, and its purpose is to accurately perform timing verification in consideration of a power supply voltage drop in a semiconductor chip, and to reduce the number of steps for developing a semiconductor integrated circuit. A timing verification method, a timing verification device, a program, and a recording medium.
[0014]
[Means for Solving the Problems]
  To achieve the above objective,According to the first aspect of the present invention, the step executed by the timing verification device includes:
The central processing unit included in the timing verification device reads circuit information stored in a storage device and performs floorplanning based on the read circuit information, and the central processing unit is allowed in a semiconductor chip. Setting a maximum value of the power supply voltage drop as a target power supply voltage drop; and calculating the power supply voltage drop for timing verification based on the target power supply voltage drop by the central processing unit; The central processing unit performs first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification, and stores delay information of each cell obtained by the first timing verification in the storage device. And a step of storing, after the central processing unit performs the first timing verification, obtained by an analysis result of a power supply network analysis. A step of comparing the power supply voltage drop amount for each cell with the power supply voltage drop amount for timing verification, and the central processing unit reviewing the delay variation according to the power supply voltage drop amount for cells having different values in the comparison And overwriting the delay information obtained by the review on the delay information of each cell stored in the storage device, and the central processing unit, the delay information of each cell stored in the storage device Performing a second timing verification based on
Also,ClaimItem 5, 7 and 9, the maximum value of the power supply voltage drop allowed in the semiconductor chip is set as the target power supply voltage drop, and the timing verification is performed based on the target power supply voltage drop. The amount of power supply voltage drop is calculated. Then, the first timing verification is performed in consideration of the power supply voltage drop amount for timing verification. Further, the power supply voltage drop amount obtained by the power supply network analysis is compared with the power supply voltage drop amount for timing verification, and the delay variation is reexamined according to the power supply voltage drop amount for cells having different values, and the second change is made. Timing verification is performed. In this case, by performing timing verification in consideration of the amount of power supply voltage drop from the initial stage, convergence to an appropriate operation timing is improved, and the number of circuit design reversions is reduced. In addition, when performing the second timing verification in the final stage, the delay value is not recalculated when the power supply voltage drop amount obtained by the power supply network analysis matches the power supply voltage drop amount for timing verification. It is possible to reduce the processing load.
[0015]
  Also,According to the second aspect of the present invention, in the step executed by the timing verification device, the central processing unit included in the timing verification device reads the circuit information stored in the storage device, and converts the read circuit information into the read circuit information. A step of performing a floor plan based on the step, the central processing unit calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip, and the central processing unit Performing a first timing verification considering delay variation corresponding to the power supply voltage drop amount, storing delay information of each cell obtained by the first timing verification in the storage device, and the central processing unit After performing the first timing verification, the amount of power supply voltage drop for each cell obtained from the analysis result of power supply network analysis, Comparing the power supply voltage drop amount for verifying the timing, and the central processing unit reviews the delay variation according to the power supply voltage drop amount for the cells having different values in the comparison, and the delay obtained by the review Overwriting the delay information of each cell stored in the storage device with the information, and the central processing unit performs a second timing verification based on the delay information of the cell stored in the storage device Steps.
Also,If you cannot set the target power supply voltage dropItem 6, 8, and 10, the power supply voltage drop amount for timing verification is calculated based on the power supply voltage distribution in the semiconductor chip, and the first timing verification is performed in consideration of the power supply voltage drop amount. Is done. Thereafter, the power supply voltage drop amount obtained by the power supply network analysis is compared with the power supply voltage drop amount for timing verification, and the delay variation is reexamined according to the power supply voltage drop amount for cells having different values, and the second Timing verification is performed. Also in this case, by considering the power supply voltage drop amount for timing verification in the initial stage of timing verification, the convergence to an appropriate operation timing is improved, and the number of circuit design reversions is reduced. In addition, when performing the second timing verification in the final stage, the delay value is not recalculated when the power supply voltage drop amount obtained by the power supply network analysis matches the power supply voltage drop amount for timing verification. It is possible to reduce the processing load.
[0016]
  Claim4According to the invention described in the above, when the power supply network analysis condition and the second timing verification condition are different from each other, the power supply voltage drop amount of each cell obtained by the power supply network analysis is the power supply current under each condition. Correction is performed using the ratio and the ratio of the resistance values. As a result, a delay value matching the second timing verification condition is obtained.
[0017]
  Claim3According to the above-described invention, the power supply voltage drop amount for timing verification is calculated based on the ratio of the cumulative number of cells corresponding to the power supply voltage drop amount in the semiconductor chip. Note that the ratio of the cumulative number of cells according to the amount of power supply voltage drop is the ratio to the total number of cells in the semiconductor chip, and the ratio according to the power supply voltage drop of a predetermined value is that the amount of power supply voltage drop in the cell is the predetermined amount. This is a cumulative rate of the number of cells that are less than the value.That is, according to the third aspect of the present invention, the timing verification is performed based on the ratio of the accumulated number of cells in which the power supply voltage drop amount in the cell is less than a predetermined value to the total number of cells in the semiconductor chip. A power supply voltage drop amount is calculated.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings.
[0019]
FIG. 1 is a schematic configuration diagram of the timing verification device 11.
The timing verification device 11 includes a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter referred to as CPU) 12, a memory 13, a storage device 14, a display device 15, an input device 16, and a drive device 17. They are connected to each other via a bus 18.
[0020]
The CPU 12 executes a program using the memory 13 and realizes processing necessary for timing verification. The memory 13 stores programs and data necessary for providing a timing verification function. The memory 13 usually includes a cache memory, a system memory, a display memory, and the like (not shown).
[0021]
The display device 15 is used for display of a layout display, a parameter input screen, and the like. Usually, a CRT, LCD, PDP, or the like (not shown) is used for this. The input device 16 is used to input requests, instructions, and parameters from the user. For this, a keyboard and a mouse device (not shown) are used.
[0022]
The storage device 14 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, etc. (not shown). The storage device 14 stores program data (hereinafter referred to as a program) for timing verification processing, which will be described later, and various data files (hereinafter referred to as files). In response to an instruction from the input device 16, the CPU 12 appropriately transfers data stored in a program and various files to the memory 13, and sequentially executes it. This storage device 14 is also used as a database.
[0023]
The program executed by the CPU 12 is provided on the recording medium 19. The drive device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads a program from the recording medium 19 via the drive device 17 and installs it in the storage device 14.
[0024]
As the recording medium 19, an arbitrary computer-readable recording medium such as a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM,...), A magneto-optical disk (MO, MD,. Can be used. The above-described program can be stored in the recording medium 19 and loaded into the memory 13 for use as necessary.
[0025]
Note that the recording medium 19 includes a medium on which a program uploaded or downloaded via a communication medium is recorded, and a disk device. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.
[0026]
Next, an outline of the timing verification process according to the present embodiment will be described with reference to FIGS. 2 to 7 show part of a circuit in a semiconductor integrated circuit.
[0027]
First, the CPU 12 of the verification apparatus 11 reads the circuit information of the semiconductor integrated circuit and performs a floor plan for layout design. Thereby, as shown in FIG. 2, each cell 21a-21e is roughly arrange | positioned. Based on this floor plan, a target value for power supply voltage drop (for example, 10% drop) is set.
[0028]
Next, a power supply voltage drop amount used for timing verification is calculated. Here, for example, a power supply voltage drop amount (= target value × 0.5 = 5%) for timing verification is obtained. Then, power supply wiring is performed so as to satisfy the target value (10%) of the power supply voltage drop. Thereby, as shown in FIG. 3, arrangement | positioning and wiring of each cell 21a-21e are performed. After this placement and wiring, power supply network analysis is performed and it is confirmed that there is no current density violation. Next, a delay value considering the power supply voltage drop amount for timing verification (5% drop) is obtained, and the first timing verification is performed based on the delay value.
[0029]
Here, the power supply voltage drop amount of each of the cells 21a to 21e calculated from the result of the power supply network analysis is as shown in FIG. That is, the cell 21a = 2%, the cell 21b = 5%, the cell 21c = 10%, the cell 21d = 8%, and the cell 21e = 5%.
[0030]
Then, as shown in FIGS. 3 and 5, the delay values are recalculated for the cells 21a, 21c, and 21d in which the power supply voltage drop amount for timing verification and the power supply voltage drop amount based on the result of the power supply network analysis do not coincide with each other. After that, the second timing verification is performed.
[0031]
When a timing error occurs in the second timing verification, for example, a cell (buffer) 21f is inserted as shown in FIG. The power supply voltage drop amount in the cell 21f is 5% by using the power supply drop amount for timing verification. Then, the power supply network analysis is performed again. Based on the result, the power supply voltage drop amount of the cell 21f is reviewed as shown in FIG. Thereafter, the second timing verification corresponding to the power supply voltage drop amount is performed, and the timing error is eliminated, and the verification process is terminated.
[0032]
Next, timing verification processing executed by the CPU 12 of the timing verification device 11 will be described in detail with reference to the flowchart of FIG.
First, the CPU 12 reads circuit information and a net list of the semiconductor integrated circuit from a predetermined file stored in the storage device 14 (step 101). The circuit information includes information such as operating conditions related to signal transmission from the input terminal to the output terminal, power supply voltage, required power consumption, temperature conditions, and the like. Then, the CPU 12 performs a floor plan based on the information, and roughly arranges circuit blocks in the semiconductor integrated circuit (step 102). In this floor plan, approximate values of the thickness and wiring density of the power supply wiring are set, and circuit blocks are roughly arranged to satisfy them.
[0033]
Next, the CPU 12 sets the maximum value of the power supply voltage drop allowed by the semiconductor chip (power supply voltage tolerance) for the target operation such as the operation speed of the circuit, and estimates it as the target value of the power supply voltage drop. (Step 103). The power supply voltage allowable value is set as a value corresponding to the target operation limit of the semiconductor integrated circuit.
[0034]
FIG. 9 is an explanatory diagram showing the relationship between the power supply voltage drop and the delay variation coefficient. When the power supply voltage drop is “0”, the delay variation coefficient is “1”, and the delay variation coefficient increases as the drop amount increases. Table data indicating this relationship is stored in the storage device 14. Then, the CPU 12 obtains the power supply voltage drop amount corresponding to the delay variation coefficient K1 at the limit of the target operation in the semiconductor integrated circuit as the target value Vp1.
[0035]
Then, the CPU 12 determines whether or not the condition of the power supply wiring set in the floor plan in step 102 of FIG. 8 satisfies the target value Vp1 of the power supply voltage drop (step 104). Placement and wiring are performed for each cell (instance) (step 105). If the target value cannot be achieved, the process returns to step 102 and the floor plan is performed again to review the wiring layer conditions and the like.
[0036]
The power supply wiring in the semiconductor chip is formed in a mesh shape or the like, but in step 105 for placing and wiring, the interval and number of each power supply wiring mesh, the thickness of the wiring, etc. so as to achieve the target value of the power supply voltage drop. Is set.
[0037]
After the placement / wiring, the CPU 12 estimates a rough delay value based on the wiring length and the wiring capacity determined by the placement / wiring, and performs timing adjustment / verification using the delay value. Implement (step 106). In this timing adjustment / verification, the power supply voltage drop amount (eg, 5%) used for timing verification is calculated based on the target value (eg, 10%) of the power supply voltage drop, and the power supply voltage drop amount is used to vary the delay value. It will be implemented in a form that reflects the quantity. This timing adjustment / verification is simply performed at an early stage, and the power supply voltage drop used for the timing verification is a uniform value for all cells.
[0038]
Specifically, the operating condition range of the semiconductor integrated circuit is, for example, a power supply voltage of 1.8 V ± 0.15 V, a temperature of −40 ° C. to 125 ° C., a process best to a process worst, and a voltage drop amount for timing verification of 0. 1V. Here, the process best to the process worst indicate a range of transistor manufacturing variations, wiring resistance values, and capacitance values between wirings due to the process. In this case, for example, under the worst condition, the timing verification of the entire chip is performed at 1.55 V, the temperature of 125 ° C., and the process worst. In the timing verification, the delay value (= Typ × Kv × Kt × Kp) is obtained by multiplying the typical value Typ of the delay value by the voltage coefficient Kv, the temperature coefficient Kt, and the process coefficient Kp in each condition. .
[0039]
If a problem (timing error) occurs as a result of the timing adjustment / verification in step 106, the CPU 12 returns to step 105 and performs placement / wiring again. That is, if the expected operation or delay value is not obtained as a result of the timing adjustment / verification, the cell or the circuit itself is reviewed.
[0040]
If no problem has occurred, the CPU 12 extracts the parasitic capacitance of the circuit (step 107). Here, parasitic capacitance extraction is performed for each wiring in the circuit in consideration of a combination of adjacent layers, a combination of upper and lower layers, and the like.
[0041]
Thereafter, the CPU 12 performs power supply network analysis based on the net list acquired in step 101, the extraction result in step 107, and the like (step 108). In this power supply network analysis, a known matrix operation is used for the power supply network of the entire circuit (entire chip) to calculate the current density of the power supply wiring between the cells and blocks, the power supply voltage drop amount, and the like.
[0042]
Then, the CPU 12 confirms that there is no violation of the current density of each wiring in the power supply network analysis, and performs the first timing verification (step 109). In the first timing verification, a voltage drop amount for timing verification (for example, 5%) that is a uniform value is used for each cell, and delay variation according to the voltage drop amount is reflected. Further, the delay information (data relating to the delay value) of each cell obtained here is temporarily stored in the storage device 14.
[0043]
When a problem (timing error) occurs in the first timing verification, the CPU 12 returns to step 105 and performs placement and wiring again. On the other hand, when there is no problem in the first timing verification, the CPU 12 calculates a delay variation considering the power supply voltage drop of each cell (step 110).
[0044]
FIG. 10 shows a specific example of the delay variation calculation process.
That is, the CPU 12 compares the power supply voltage drop amount in each cell obtained from the result of the power supply network analysis with the power supply voltage drop amount for timing verification (step 110a). The delay value is recalculated (step 110b). The result of this recalculation is overwritten on the delay information stored in the storage device 14 in the first timing verification (step 109). On the other hand, the delay information of the storage device 14 stored in step 109 is maintained for the cells having a small difference in the power supply voltage drop. Thereby, the delay information of the storage device 14 becomes a value in which the power supply voltage drop amount of each cell is taken into consideration.
[0045]
In step 110a, when the difference in power supply voltage drop amount is outside the preset allowable range, the CPU 12 considers that the difference is large and executes the process in step 110b. If it is within the allowable range, the difference is considered to be small and the process of step 110b is bypassed. Further, data relating to the allowable range used in this determination is prepared for each cell and set in the storage device 14.
[0046]
Thereafter, as shown in FIG. 8, the CPU 12 performs the second timing verification based on the delay information of each cell (step 111). If a problem (timing error) occurs in the second timing verification, the CPU 12 returns to step 105 and performs placement and wiring again. On the other hand, if no problem has occurred, the CPU 12 ends this process.
[0047]
Next, a specific example in the case where the power supply voltage drop amount corresponding to the second timing verification condition is reflected in the delay value will be described.
In the power supply network analysis in step 108, since the current density is normally checked under the condition that the power consumption is maximized, the condition may be different from the condition required for the second timing verification. In this case, since the power supply voltage drop amount is determined by the current amount I and the resistance R, the power supply voltage drop amount obtained by the power supply network analysis is corrected according to the timing verification conditions.
[0048]
Specifically, for example, conditions for maximizing power consumption are power supply voltage: maximum, process: best, and temperature: maximum. In contrast, the worst condition in timing verification (timing worst condition) is power supply voltage: minimum, process: worst, temperature: maximum, and the best condition in timing verification (timing best condition) is power supply voltage: maximum, Process: Best, Temperature: Minimum.
[0049]
Therefore, when the power supply voltage drop amount under the timing worst condition is calculated from the condition that the power consumption is maximized, the power supply voltage condition and the process condition are different. Further, when the power supply voltage drop amount under the timing best condition is calculated, the correction is made using the ratio of the consumption current and the ratio of the temperature dependence coefficient of the resistance.
[0050]
Here, it is assumed that the power supply voltage drop when the power consumption is maximum is Vdp_P, the power supply voltage drop under the timing worst condition is Vdp_TW, and the power supply voltage drop under the timing best condition is Vdp_TB. The current amount when the power consumption is maximum is Ip, the current amount under the timing worst condition is Itw, and the current amount under the timing best condition is Itb. Further, the maximum value of the temperature dependency coefficient of resistance in the wiring (specifically, the resistance value when the temperature is maximum) is Rmax, and the minimum value of the temperature dependency coefficient of resistance (specifically, the temperature is minimum). Resistance value in this case) is Rmin.
[0051]
In this case, the power supply voltage drop amounts Vdp_TW and Vdp_TB under the timing worst condition and the timing best condition can be obtained by the following equations.
Vdp_TW = Vdp_P × (Itw / Ip)
Vdp_TB = Vdp_P × (Itb / Ip) × (Rmin / Rmax)
Based on the power supply voltage drop amounts Vdp_TW and Vdp_TB obtained in this way, a delay value under each condition is calculated, and the delay value is taken into consideration when the second timing verification is performed.
[0052]
As described above, according to the above embodiment, the following effects can be obtained.
(1) The maximum value of the power supply voltage drop allowed in the semiconductor chip is set as the target power supply voltage drop, and the power supply voltage drop for timing verification is calculated based on the target power supply voltage drop. The amount of power supply voltage drop for timing verification is a uniform value for all cells, and the first timing verification is performed using the amount of power supply voltage drop. Further, when the power supply voltage drop amount of each cell obtained from the result of the power supply network analysis is different from the power supply voltage drop amount for timing verification, the second timing verification is performed after the delay value is reviewed for the cell. Is called. In this case, by performing timing verification in consideration of the amount of power supply voltage drop from the initial stage, convergence to an appropriate timing can be improved, and the number of times of design return can be reduced. In addition, when performing the second timing verification in the final stage, the delay value is not recalculated when the power supply voltage drop amount obtained by the power supply network analysis matches the power supply voltage drop amount for timing verification. The processing load on the CPU 12 can be reduced. Also, the capacity of the memory 13 in the timing verification device 11 can be reduced.
[0053]
As described above, since the timing verification in consideration of the power supply voltage drop in the semiconductor chip is accurately performed, the reliability of the semiconductor integrated circuit can be improved and the development man-hour of the semiconductor integrated circuit can be reduced. .
[0054]
(2) By correcting the power supply voltage drop amount of each cell obtained by the power supply network analysis by using the ratio of the power supply current and the ratio of the resistance value, the delay value in accordance with the second timing verification condition can be obtained. Can be sought.
[0055]
(3) In the present embodiment, the placement / wiring process is performed so as to satisfy the target power supply voltage drop amount, so that the convergence to an appropriate operation timing can be further improved.
[0056]
(4) An allowable range is provided to determine the magnitude of the difference in power supply voltage drop. By appropriately setting this allowable range, it is possible to suppress the number of cells (number of instances) that require recalculation of the delay value.
[0057]
(Second Embodiment)
A second embodiment embodying the present invention will be described below.
FIG. 11 is a flowchart illustrating the timing verification process according to the second embodiment. The present embodiment is a specific example of the timing verification process when the target value of the power supply voltage drop amount in the semiconductor chip cannot be set.
[0058]
In the first embodiment, the step 103 for estimating the target value of the power supply voltage drop amount and the step 104 for determining whether or not the target value is satisfied are executed. In the process, step 113 is executed instead of step 103 and step 104. In the other steps (101, 102, 105 to 111), processing equivalent to that in the first embodiment is executed.
[0059]
Specifically, in step 113, the CPU 12 performs a simple power supply network analysis based on circuit information such as the target power consumption of the semiconductor chip, the number of used wiring layers, the number of power supply terminals, and the like to obtain an approximate power supply voltage drop. Calculate the amount. Then, the CPU 12 calculates the power supply voltage drop amount for timing verification from the calculated estimated value of the power supply voltage drop in consideration of the power supply voltage drop distribution of the entire chip.
[0060]
This power supply voltage drop amount for timing verification is used in timing verification (steps 106 and 109) that is carried out preventively in the initial stage, and is reviewed when performing final timing verification (step 111). For example, the maximum value or the minimum value in the semiconductor chip can be selected. In addition, the power supply voltage drop amount for timing verification can be selectively used according to the purpose of timing verification.
[0061]
However, in order to reduce the number of times of returning to step 105 for performing placement and wiring and to improve the convergence of the operation timing, it is important to appropriately determine the power supply voltage drop amount for timing verification.
[0062]
Therefore, in this embodiment, the power supply voltage drop amount for timing verification is determined in consideration of the power supply voltage drop distribution of the entire chip.
FIG. 12A is a schematic configuration diagram of the semiconductor chip 22, and FIG. 12B is an explanatory diagram showing distribution of power supply voltage in the chip 22.
[0063]
As shown in FIG. 12A, an I / O portion 24 is provided around the core portion 23 in the semiconductor chip 22, and a plurality of pads 25 for supplying the power supply voltage Vdd are formed outside thereof. . As shown in FIG. 12B, the power supply voltage drop amount in the chip 22 gradually increases from the core peripheral portions P1 and P2 toward the core central portion P0. That is, the power supply voltage drop amount in the chip 22 is the maximum value Vdpmax at the core center portion P0 and the minimum value Vdpmin at the core peripheral portions P1 and P2. Note that the distribution of the power supply voltage drop in the semiconductor chip 22 may be uneven depending on the position of the circuit block formed in the core portion 23 or the like.
[0064]
FIG. 13 shows the relationship between the power supply voltage drop amount in the semiconductor chip 22 and the ratio of the target area corresponding to the voltage drop amount. Here, the ratio of the target area indicates the ratio (the ratio of the cumulative number of cells) of accumulating areas that are less than the predetermined value with respect to the power supply voltage drop amount of the predetermined value. In FIG. 13, the target area increases as the power supply voltage drop increases, and when the power supply voltage drop reaches the maximum value Vdpmax, the corresponding target areas are all areas (100%). Specifically, for example, when performing timing verification so as to cover 60% of the number of cells (number of instances) with respect to the total number of cells (all areas) in the semiconductor chip 22, the power supply voltage drop amount for timing verification is Is set to ½ of the maximum value Vdpmax.
[0065]
FIG. 14 is a flowchart illustrating a calculation process of the power supply voltage drop amount for timing verification.
As shown in FIG. 14, the CPU 12 estimates a power supply voltage drop by performing a simple power supply network analysis (step 113a). Thereafter, the CPU 12 determines the distribution of the power supply voltage drop amount in the chip (step 113b) and determines the ratio to the total number of cells (instances) (step 113c). Then, the CPU 12 obtains the power supply voltage drop amount corresponding to the ratio from the relationship shown in FIG. 13 as the voltage drop amount for timing verification (temporary power supply voltage drop amount) (step 113d).
[0066]
Then, in consideration of the voltage drop amount for timing verification, the placement / wiring process (step 105) to the delay fluctuation calculation process (step 110) are executed.
Also in the present embodiment, as in the first embodiment, the power supply voltage drop amount for timing verification is considered in the initial stage. As a result, convergence to an appropriate operation timing can be improved, and the number of circuit design returns can be reduced.
[0067]
Further, since the power supply voltage drop amount for timing verification is calculated based on the ratio of the cumulative number of cells according to the power supply voltage drop amount in the semiconductor chip, the convergence of the operation timing can be further improved.
[0068]
The above embodiment can be modified as follows.
In step 110a in FIG. 10, when the difference in the power supply voltage drop amount is outside the allowable range (when the difference is large), the delay variation according to the power supply voltage drop amount is reviewed, but the present invention is not limited to this. It is not something. Only when the difference of the power supply voltage drop amount is small or large with respect to the predetermined value, the delay variation according to the power supply voltage drop amount of the cell may be reviewed. That is, the delay variation calculation process (step 110) in consideration of the power supply voltage drop can be changed as appropriate according to the application of the semiconductor integrated circuit.
[0069]
Further, the data related to the allowable range used in the determination in step 110a is stored in advance in the storage device 14, but may be set by input data based on the operation of the input device 16.
[0070]
In the first embodiment, as in the second embodiment, the power supply voltage drop amount for timing verification may be calculated in consideration of the power supply voltage distribution of the entire chip. In this way, the power supply voltage drop amount for timing verification can be set appropriately, and the convergence of the operation timing can be improved.
[0071]
As a method of calculating the power supply voltage drop amount for timing verification, for example, an average value of the minimum value and the maximum value is used in addition to the method of calculating the power supply voltage distribution of the entire chip as in the above embodiment. The average value may be obtained as the power supply voltage drop amount for timing verification.
[0072]
The various embodiments described above can be summarized as follows.
(Appendix 1) A timing verification method for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
The maximum power supply voltage drop allowed in the semiconductor chip is set as the target power supply voltage drop, and the power supply voltage drop for timing verification is calculated based on the target power supply voltage drop. After performing the first timing verification considering the delay variation corresponding to the amount, the power supply voltage drop amount for each cell obtained from the analysis result of the power supply network analysis is compared with the power supply voltage drop amount for the timing verification, A timing verification method comprising: performing second timing verification by reviewing delay variation according to a power supply voltage drop amount for cells having different values.
(Appendix 2) A timing verification method for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Based on the distribution of the power supply voltage in the semiconductor chip, the power supply voltage drop amount for timing verification is calculated, and after performing the first timing verification considering the delay variation corresponding to the power supply voltage drop amount, the analysis of the power supply network analysis The power supply voltage drop amount for each cell obtained as a result is compared with the power supply voltage drop amount for timing verification, and the second timing verification is performed by reviewing the delay variation according to the power supply voltage drop amount for cells having different values. The timing verification method characterized by performing.
(Supplementary Note 3) When the condition in the power network analysis and the condition in the second timing verification are different, the power supply voltage drop amount for each cell obtained in the power network analysis is calculated by comparing the power supply current ratio in each condition. The timing verification method according to appendix 1 or 2, wherein a delay value in accordance with the second timing verification condition is obtained by performing correction using the ratio of the resistance value and the resistance value.
(Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the power supply voltage drop amount for timing verification is calculated based on a ratio of the cumulative number of cells according to the power supply voltage drop amount in the semiconductor chip. The timing verification method according to the above.
(Supplementary note 5) The timing verification method according to supplementary note 1, wherein the placement / wiring process is performed to determine the density of the power supply wiring and the thickness of the wiring so as to satisfy the target power supply voltage drop amount.
(Supplementary note 6) The timing verification method according to supplementary note 2, wherein the arrangement / wiring process is performed to determine the density of the power supply wiring and the thickness of the wiring in consideration of the power supply voltage drop amount for the timing verification.
(Supplementary note 7) The power supply voltage drop amount for timing verification is a uniform value for all cells, and the first timing verification is performed using the uniform value. The timing verification method described.
(Supplementary note 8) A timing verification device for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Means for setting the maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop and calculating the power supply voltage drop for timing verification based on the target power supply voltage drop;
Means for performing first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Means for performing second timing verification
A timing verification apparatus comprising:
(Supplementary note 9) A timing verification device for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Means for calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Means for performing first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Means for performing second timing verification
A timing verification apparatus comprising:
(Appendix 10) A program for performing timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Setting a maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop, and calculating a power supply voltage drop for timing verification based on the target power supply voltage drop;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Performing the second timing verification
The program characterized by including.
(Appendix 11) A program for performing timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Performing the second timing verification
The program characterized by including.
(Supplementary note 12) A computer-readable recording medium storing a program for performing timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
The program is
Setting a maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop, and calculating a power supply voltage drop for timing verification based on the target power supply voltage drop;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Performing the second timing verification
A recording medium comprising:
(Supplementary note 13) A computer-readable recording medium storing a program for performing timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
The program is
Calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. Performing the second timing verification
A recording medium comprising:
[0073]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to accurately perform timing verification in consideration of a power supply voltage drop in a semiconductor chip, and to reduce the number of steps for developing a semiconductor integrated circuit.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a timing verification device.
FIG. 2 is an explanatory diagram showing an outline of timing verification processing;
FIG. 3 is an explanatory diagram showing an outline of timing verification processing;
FIG. 4 is an explanatory diagram showing an outline of timing verification processing;
FIG. 5 is an explanatory diagram showing an outline of timing verification processing;
FIG. 6 is an explanatory diagram showing an outline of timing verification processing;
FIG. 7 is an explanatory diagram showing an outline of timing verification processing;
FIG. 8 is a flowchart showing timing verification processing according to the first embodiment;
FIG. 9 is an explanatory diagram showing a relationship between a power supply voltage drop amount and a delay variation coefficient;
FIG. 10 is a flowchart illustrating a delay variation calculation process.
FIG. 11 is a flowchart illustrating timing verification processing according to the second embodiment.
12A is a schematic configuration diagram of a semiconductor chip, and FIG. 12B is an explanatory diagram showing a distribution of power supply voltage in the chip.
FIG. 13 is an explanatory diagram showing a relationship between a power supply voltage drop amount and a ratio of a target area according to the power supply voltage drop amount;
FIG. 14 is a flowchart showing a calculation process of a power supply voltage drop amount.
FIG. 15 is a flowchart showing a conventional timing verification process;
[Explanation of symbols]
11 Timing verification device
19 Recording media
21a-21f cell
22 semiconductor chips

Claims (10)

A timing verification method of a timing verification apparatus that performs operation timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
The steps performed by the timing verification device include:
The central processing unit provided in the timing verification device reads circuit information stored in a storage device, and performs a floor plan based on the read circuit information;
The central processing unit sets a maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop;
The central processing unit calculates a power supply voltage drop amount for timing verification based on the target power supply voltage drop amount;
Said central processing unit, performing a first timing verification considering delay variation corresponding to the power supply voltage drop amount for the timing verification, the delay information of each cell obtained by the first timing verification in the storage device Storing, and
Said central processing unit, after the first timing verification, comparing the power supply voltage drop amount of each cell obtained by the analysis result of the power supply network analysis, and a power supply voltage drop amount for the timing verification ,
The central processing unit reviews delay variation according to the amount of power supply voltage drop for cells having different values in the comparison, and delay information obtained by the review is stored in the storage device as delay information of each cell. Step overwriting
The central processing unit performs a second timing verification based on delay information of each cell stored in the storage device ;
Timing verification method, which comprises a. A timing verification method of a timing verification apparatus that performs operation timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
The steps performed by the timing verification device include:
The central processing unit provided in the timing verification device reads circuit information stored in a storage device, and performs a floor plan based on the read circuit information;
The central processing unit calculates a power supply voltage drop amount for timing verification based on a power supply voltage distribution in a semiconductor chip;
The central processing unit performs first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification, and stores delay information of each cell obtained by the first timing verification in the storage device. Storing, and
Said central processing unit, after the first timing verification, comparing the power supply voltage drop amount of each cell obtained by the analysis result of the power supply network analysis, and a power supply voltage drop amount for the timing verification ,
The central processing unit reviews delay variation according to the amount of power supply voltage drop for cells having different values in the comparison, and delay information obtained by the review is stored in the storage device as delay information of each cell. Step overwriting
The central processing unit performs a second timing verification based on delay information of each cell stored in the storage device ;
Timing verification method, which comprises a.   The central processing unit calculates the power supply voltage drop amount for timing verification based on the ratio of the cumulative number of cells in which the power supply voltage drop amount in the cells is less than a predetermined value to the total number of cells in the semiconductor chip. The timing verification method according to claim 2, wherein the timing verification method is calculated.   When the condition in the power supply network analysis is different from the condition in the second timing verification in the central processing unit, the power supply voltage drop amount for each cell obtained in the power supply network analysis is calculated as the power supply current in each condition. 4. The delay value according to the second timing verification condition is obtained by performing correction using the ratio of the first and the resistance values, and the correction value is used. 5. Timing verification method. A timing verification device for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Means for setting the maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop and calculating the power supply voltage drop for timing verification based on the target power supply voltage drop;
Means for performing first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And a means for performing second timing verification. A timing verification device for verifying operation timing in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Means for calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Means for performing first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And a means for performing second timing verification. A program for causing a timing verification device to execute timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Setting a maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop, and calculating a power supply voltage drop for timing verification based on the target power supply voltage drop;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And performing a second timing verification ;
A program for causing the timing verification device to execute the above . A program for causing a timing verification device to execute timing verification in consideration of a voltage drop of a power supply wiring in a semiconductor integrated circuit,
Calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And performing a second timing verification ;
A program for causing the timing verification device to execute the above . A program for executing the timing verification considering the voltage drop of the power supply wiring in a semiconductor integrated circuit in a computer,
Setting a maximum value of the power supply voltage drop allowed in the semiconductor chip as a target power supply voltage drop, and calculating a power supply voltage drop for timing verification based on the target power supply voltage drop;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And performing a second timing verification ;
A computer-readable recording medium on which the program for causing the computer to execute is recorded . A program for executing the timing verification considering the voltage drop of the power supply wiring in a semiconductor integrated circuit in a computer,
Calculating a power supply voltage drop amount for timing verification based on a power supply voltage distribution in the semiconductor chip;
Performing a first timing verification considering delay variation corresponding to the amount of power supply voltage drop for timing verification;
Compare the power supply voltage drop for each cell obtained from the analysis result of the power supply network analysis with the power supply voltage drop for the timing verification, and review the delay variation according to the power supply voltage drop for cells with different values. And performing a second timing verification ;
A computer-readable recording medium on which the program for causing the computer to execute is recorded .

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