JP4191986B2 - Method and apparatus for designing semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device (LSI) design method and design apparatus, and more particularly to a design method and design apparatus for designing power supply wiring optimal for an LSI.
[0002]
In general, in the design of LSI, when layout design is completed, power supply network analysis for performing various verifications such as verification of the minimum operating voltage and timing verification for guaranteeing the operation is performed, and this power supply network analysis is completed to become NG. The LSI is redesigned. Since such redesign leads to an increase in cost, it is necessary to design an optimal power supply at the initial stage of design.
[0003]
[Prior art]
In LSI design, it is necessary to keep the IR drop value based on the power supply wiring below an allowable value. Generally, the maximum IR drop value allowed in an LSI is determined by the minimum voltage that guarantees the operation and timing of the LSI, and is expressed by the following equation.
[0004]
(Maximum IR drop) = (VDD supply voltage)-(minimum voltage)
Here, the VDD power supply voltage is a power supply voltage supplied to the inside of the chip (core unit) with respect to the LSI, and the VDD power supply voltage and the minimum voltage are values determined in the LSI specifications.
[0005]
In power supply design, it is necessary to set the amount of power supply wiring so that the total value of IR drop values generated on the VDD power supply side and the VSS power supply side is smaller than the maximum IR drop value. That is, the IR drop value IRdrop of the entire LSI is determined by the IR drop value VDD-IRdrop generated on the VDD power supply side and the IR drop value VSS-IRdrop generated on the VSS power supply side,
(IRdrop) = (VDD-IRdrop) + (VSS-IRdrop)
It is necessary to prevent the IR drop value IRdrop from exceeding the aforementioned maximum IR drop value.
[0006]
When the IR drop value IRdrop exceeds the maximum IR drop value, an IR drop violation occurs, causing a malfunction of the LSI. For this reason, in the power supply design, when the layout design is completed, a power supply network analysis is performed to check whether there is an IR drop violation. If there is a violation, the power supply design is performed again to determine the IR drop value IRdrop. Does not exceed the maximum IR drop value.
[0007]
Hereinafter, a conventional LSI design method will be described with reference to the flowchart of FIG.
First, the maximum IR drop value is determined according to the specifications of the LSI to be designed (step 51), and then the number of power supplies (the number of power supply I / Os) and the number of wiring layers are determined (steps 52a and 52b). When the resistance value of the power supply I / O depends on the number of wiring layers, the determination of the number of wiring layers is generally performed simultaneously with the determination of the number of power supplies.
[0008]
Next, after determining the chip size of the LSI (step 53) and performing a floor plan for setting the cell placement area and the like (step 54), the amount of power supply in the core area (power supply wiring amount per unit area) Is determined (step 55).
[0009]
Next, the LSI power supply is designed based on the determined power supply quantity (step 56), the cells are arranged (step 57), and wiring between the arranged cells is performed (step 58). Here, when wiring between cells cannot be performed (NG), the power supply quantity in the core area is changed by changing the number of power supplies, the number of wiring layers, or the chip size, etc. / Redo wiring.
[0010]
When the placement / wiring of the cell is completed, the power supply network analysis is performed on the layout (step 59). In this power supply network analysis, it is verified whether or not the IR drop value exceeds the maximum IR drop value together with various verifications such as timing verification and crosstalk verification (see, for example, Patent Document 1).
[0011]
Here, if there is an IR drop violation, the power supply quantity in the core area is changed (for example, the wiring width is increased) and the layout is performed again, and the layout after the change is again performed, as described above. It is confirmed whether or not there is an IR drop violation by performing power supply network analysis. Conventionally, a method has been employed in which such a series of processing is repeated until a target IR drop value is achieved.
[0012]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-321729
[0013]
[Problems to be solved by the invention]
By the way, in the conventional design method as described above, since the chip size and the amount of power supply are determined by empirical rules, the amount of power supply wiring (power supply pattern) is frequently set or conversely insufficient. It was happening.
[0014]
The reason why the power supply pattern is excessively set may be that the chip size is estimated to be large. However, if the power supply pattern is excessively set, the power supply wiring becomes redundant and the optimal power supply wiring It can not be. On the other hand, the cause of the shortage of the power supply pattern may be that the estimated value of the power supply quantity is small, which causes the above-described IR drop violation.
[0015]
Conventionally, since power supply design is performed without properly estimating the chip size and power supply quantity in this way, it is difficult to optimize power supply wiring, and results of power supply network analysis after layout design There is a problem that there is a high possibility that an excessive setting or shortage of the power supply pattern will occur. As a result, there has been a problem that the number of times of redesign of the LSI increases, leading to an increase in design time and an increase in design cost.
[0016]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a design method and a design apparatus for a semiconductor integrated circuit device that can easily optimize power supply wiring.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, according to the first and tenth aspects of the present invention, the power supply design is performed based on the power supply quantity in which the power supply wiring amount per unit area is estimated. Depends on design equipment In a method for designing a semiconductor integrated circuit device, The step executed by the design apparatus is performed by a central processing unit included in the design apparatus. A step of dividing a core part by a plurality of unit circuits each having an electrically equivalent characteristic and calculating a resistance value per unit circuit corresponding to an IR drop value in the core part region, and is set for each unit circuit Calculating the amount of power supply that is equivalent to the amount of power supply wiring equivalent to the resistance value. As a result, it is possible to estimate the amount of power supply with high accuracy before designing the layout, and the power supply wiring can be easily optimized. Also, according to this, since excessive setting or shortage of the power supply quantity is suppressed, the number of redesigns can be reduced, the design time can be shortened, and the design cost can be reduced.
[0018]
Further, the central processing unit calculates in advance a power supply quantity that is equivalent to the power supply wiring quantity equivalent to the resistance value set per unit circuit, and the power supply quantity is tabulated according to the number of wiring layers to which power supply wiring can be assigned. A table is created, the power supply quantity table is stored in a storage device, and the power supply quantity is calculated based on the power supply quantity table. Thereby, it is possible to easily estimate the amount of power supply corresponding to the resistance value per unit circuit. further The IR drop value in the core part region is a plurality of power supply characteristic values that determine power consumption consumed in the core part, a power supply voltage supplied to the core part, and an IR drop value outside the core part region. And is set based on. Thereby, it is possible to estimate the power supply quantity with high accuracy while appropriately adjusting the IR drop value in the target core area.
[0019]
Claim 2 According to the invention described in (2), the plurality of unit circuits include a resistance network composed of a plurality of resistors connected in a substantially cross shape and a current source connected to the center of the resistance network, Central processing unit For each current source , Equivalent current source that equally divides the current consumed by the core The Set each You The As a result, the amount of power supply can be easily estimated based on the resistance value per unit circuit.
[0021]
Claim 3 According to the invention described in the above, according to the number of wiring layers to which the power supply wiring can be assigned Set For each wiring layer of Power occupancy Is stored in the storage device I did it. Thereby, it can be set as the optimal power supply wiring according to each wiring layer to be utilized.
[0022]
Claim 4 According to the invention described in The central processing unit is According to the number of wiring layers to which the power supply wiring can be assigned, the upper limit value of the power supply occupation ratio is set so as to ensure the signal wiring property of each wiring layer. Thereby, it is possible to calculate the power supply quantity while ensuring the signal wiring property.
[0023]
Claim 5 According to the invention described in The central processing unit is When the amount of power supply exceeds the upper limit value of the power supply occupancy, the number of wiring layers to which the power supply wiring can be allocated is increased, or the plurality of power supply characteristic values are adjusted to adjust the resistance value per unit circuit Was set higher. Thereby, it can be set as the design method which can prevent the signal wiring property from being impaired reliably and can calculate the amount of power supplies.
[0024]
Claim 6 According to the invention described in The central processing unit is The lower limit value of the power occupation ratio is further set according to the number of wiring layers to which the power wiring can be assigned. As a result, it is possible to further optimize the power supply wiring by effectively using the wiring layer to which the power supply wiring can be assigned.
[0025]
Claim 7 According to the invention described in The central processing unit is When the power supply quantity is below the lower limit value of the power supply occupancy rate, the number of wiring layers to which the power supply wiring can be assigned is reduced, or the plurality of power supply characteristic values are adjusted to adjust the resistance value per unit circuit. Was set low. As a result, it is possible to provide a design method that can easily optimize the power supply wiring.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
FIG. 1 is an explanatory diagram showing an equivalent circuit model of the VDD power supply network. In the present embodiment, a method of calculating the power supply wiring amount of the VDD power supply wiring based on the IR drop value VDD-IRdrop generated on the VDD power supply side will be described, but based on the IR drop value VSS-IRdrop generated on the VSS power supply side. A similar method can be applied when calculating the power supply wiring amount.
[0027]
As shown in FIG. 1, a VDD power supply is provided in a chip (hereinafter referred to as a core section) 11 of a semiconductor integrated circuit device (LSI) via a plurality of power supply I / Os (not shown) arranged along each side. A voltage 12 (indicated by V in the figure) is supplied. The core unit 11 is configured by being divided by a plurality of power units 13 as unit circuits.
[0028]
Here, in each path through which the VDD power supply voltage 12 is supplied to the core unit 11, assuming that the resistance Io of the power supply I / O, the bonding wire resistance Rb, and the package resistance Rp, these resistors Rio, Rb, Rp It can be considered that each is connected in series to the VDD power supply voltage 12 corresponding to the I / O arrangement position.
[0029]
At this time, the IR drop value VDD-IRdrop on the VDD power supply side is calculated by the following equation.
(VDD-IRdrop) = (POWERcore / VDD / # IO) x (Rp + Rb + Rio) + (CORE-IRdrop)
However, POWERcore: Core power consumption
VDD: Core power supply voltage (VDD power supply voltage 12 above)
#IO: Number of power I / O
Rp: Package resistance
Rb: Bonding wire resistance
Rio: Power I / O resistance
CORE-IRdrop: Core IR drop value
It is.
[0030]
Incidentally, the core unit power consumption POWERcore and the core unit power supply voltage VDD are values determined by specifications according to the circuit configuration of the LSI. The number of power I / Os #IO, the package resistance Rp, the bonding wire resistance Rb, and the power source I The / O resistance Rio is given as a power supply characteristic value that determines an IR drop value outside the core region.
[0031]
Therefore, the IR drop value VDD-IRdrop on the VDD power supply side can be adjusted using the following method.
(1) Adjust the number of power I / Os #IO, that is, the number of power sources.
(2) The package resistance Rp is adjusted.
(3) The bonding wire resistance Rb is adjusted.
(4) The resistance Rio of the power supply I / O is adjusted.
(5) Adjust the core IR drop value CORE-IRdrop.
[0032]
Hereinafter, the adjustment method of the core part IR drop value CORE-IRdrop of the above (5) will be described in detail.
As shown in FIG. 2 (a), the core portion 11 is configured by being divided by a plurality of power units 13, and each of these power units 13 is connected in a substantially cross shape as shown in FIG. 2 (b). This is modeled by a resistance network 13a composed of a plurality of resistors and a current source 13b connected to the center of the resistance network 13a.
[0033]
The current source 13b of each power unit 13 includes a current source equivalent to a current value obtained by equally dividing the core unit consumption current (= core unit power consumption POWERcore / core unit power supply voltage VDD) consumed by the core unit 11 by the number of power units. Each is set. That is, each power unit 13 is set as an equivalent region having the same electrical characteristics.
[0034]
The core part IR drop value CORE-IRdrop is adjusted by changing the power supply quantity (the power supply wiring amount per unit area) in the core part 11 region divided by the plurality of power units 13. Specifically, the target IR power supply side IR drop value VDD-IRdrop is achieved by estimating the amount of power supply having a resistance value equivalent to the combined resistance value (hereinafter referred to as power unit resistance) Rpu per power unit 13. The core IR drop value CORE-IRdrop is adjusted as follows.
[0035]
Here, the relationship between the power unit resistance Rpu and the IR drop value VDD-IRdrop will be described.
As shown in FIG. 3, the IR drop value VDD-IRdrop changes in proportion to the value of the power unit resistance Rpu, and the amount of change varies depending on the power consumption value of the core unit 11 (core unit power consumption POWERcore). Thereby, the power unit resistance Rpu is set as a value corresponding to the target IR drop value VDD-IRdrop (specifically, the core part IR drop value CORE-IRdrop) according to the core part power consumption POWERcore.
[0036]
For example, consider three types of core power consumption POWERcore, “POWER1”, “POWER2”, “POWER3” (POWER3>POWER2> POWER1). In this case, the power unit resistance Rpu needs to be set to a larger value as the core power consumption POWERcore is smaller than the target predetermined IR drop value VDD-IRdrop. Therefore, in other words, the target IR drop value VDD-IRdrop can be realized by appropriately setting the value of the power unit resistance Rpu in accordance with the core unit power consumption POWERcore.
[0037]
The correspondence relationship between the power unit resistance Rpu and the IR drop value VDD-IRdrop (hereinafter referred to as IR drop characteristic) shown in FIG. 3 is experimentally obtained in advance and stored as a data file in the storage device of the automatic design device described later. ing.
[0038]
Next, the relationship between the power unit resistance Rpu and the power supply quantity will be described.
The power supply quantity having a resistance value equivalent to the power unit resistance Rpu is calculated according to the power supply quantity table shown in FIG.
[0039]
In this power supply quantity table, the power supply quantity corresponding to the values of a plurality of types of power unit resistances Rpu is recorded according to the number of wiring layers to which power supply wiring can be assigned in advance. Specifically, the power occupancy rate for each wiring layer set in accordance with the number of wiring layers to which power wiring can be assigned (ratio of power wiring per unit area in each wiring layer) is recorded. The number of VDD power supply lines in the power unit 13 corresponding to each power supply occupation rate is recorded. This power supply quantity table is stored as a data file in the storage device of the automatic design apparatus described later, as described above.
[0040]
FIG. 4A shows the values of six types of power unit resistances Rpu for the wiring layers of 5 to 7 layers (M5 to M7 in the figure) when there are 7 wiring layers to which power supply wiring can be assigned. The power supply quantity corresponding to each (the wiring width in each wiring layer is fixed) is illustrated.
[0041]
Normally, LSIs have different power supply structures depending on the number of wiring layers in which power supply wiring can be used (assigned). That is, the wiring width and the wiring interval of the VDD power supply wiring and the VSS power supply wiring used in each wiring layer are different. For this reason, according to the number of wiring layers to be used, a power supply quantity table corresponding to each value of various power unit resistances Rpu is calculated in advance for each wiring layer and used as a table, so that the area within the core portion 11 region can be used. Can be easily calculated.
[0042]
Incidentally, as shown in FIG. 4B, the power occupancy ratio is expressed as a ratio of the power wiring amount (VDD power wiring and VSS power wiring) in the power unit 13 in this embodiment. Is calculated by
[0043]
Power occupancy = n x 2 x (power supply wiring width + (Power supply wiring interval) / (Power unit width)
However, n is the number of VDD power supply lines in the power unit 13, and the number of VDD power supply lines and VSS power supply lines are the same.
[0044]
Here, the relationship between the power supply quantity and the signal wiring property will be described.
The amount of power supply needs to be estimated in consideration of signal wiring in each wiring layer. Specifically, the upper limit value of the power occupancy rate is set so that the signal wiring property of each wiring layer (the area where signal wiring is applied) is ensured, and if the power supply quantity exceeds this upper limit value, the signal wiring channel is insufficient. to decide.
[0045]
In this case, for example, by increasing the number of wiring layers and increasing the number of layers to which power supply wiring can be assigned, the amount of power supply per layer is suppressed. Thereby, it can suppress that the signal wiring property in each wiring layer is impaired.
[0046]
Incidentally, the power supply quantity in each wiring layer can be optimized by setting the lower limit value of the power supply occupancy ratio contrary to the upper limit value of the power supply occupancy ratio. For example, if the lower limit value of the power occupancy rate in a certain wiring layer is set to 10% and the power supply quantity falls below this lower limit value, the power wiring is optimized by reducing the number of wiring layers to which power wiring is allocated. Can do.
[0047]
Next, a power supply design process using the above-described equivalent model of the VDD power supply network will be described with reference to the flowchart shown in FIG.
First, the target VDD power supply side IR drop value VDD-IRdrop is determined from the maximum IR drop value determined according to the specifications of the LSI to be designed (step 21).
[0048]
Next, a package for mounting a chip is selected (step 22), and then the number of power supplies (number of power I / Os #IO) and the number of wiring layers are determined (steps 23a and 23b). When the power I / O resistance Rio depends on the number of wiring layers, the number of wiring layers is generally determined simultaneously with the determination of the number of power supplies. May be performed at the time of estimation (step 26 indicated by a two-dot chain line in the figure).
[0049]
Next, the IR drop value VDD-IRdrop, the core part power consumption POWERcore, the core part power supply voltage VDD, the package resistance Rp, the bonding wire resistance Rb, the number of power supply I / Os #IO determined in the steps 21 to 23a and 23b, respectively. , The target value of the core IR drop value CORE-IRdrop is determined from the power I / O resistance Rio (step 24).
[0050]
Next, an equivalent circuit model (see FIG. 2) in which the core unit 11 is divided by the power unit 13 is created, and the power unit resistance Rpu is calculated according to the IR drop characteristic (see FIG. 3) described above (step 25).
[0051]
Next, the power supply quantity having a resistance value equivalent to the power unit resistance Rpu calculated in step 25 is estimated according to the above-described power supply quantity table (see FIG. 4A) (step 27).
[0052]
Then, it is determined whether or not the amount of power supply estimated in this step 27 exceeds the preset upper limit value of the power occupancy or whether it does not fall below the lower limit value (step 28).
[0053]
Here, in step 28, when the power supply quantity does not satisfy the predetermined reference value (upper limit value or lower limit value) of the power occupancy rate (NG), the number of wiring layers is changed (step 29).
[0054]
Specifically, if the power supply quantity exceeds the upper limit value of the power occupancy rate, the number of wiring layers that can be assigned with power supply wiring is increased, and conversely, the power supply quantity is lower than the lower limit value of the power supply occupancy ratio. In such a case, the number of wiring layers to which power supply wiring can be assigned is reduced. Then, the power supply quantity is calculated again according to the power supply quantity table corresponding to the number of wiring layers after the change, and it is determined again whether or not the power occupancy standard is satisfied.
[0055]
In step 29, if the number of wiring layers cannot be changed (NG), the process proceeds to step 22 or 23a, where the package resistance Rp, bonding wire resistance Rb, power I / O number #IO, power I / O Various power supply characteristic values such as the resistor Rio are changed.
[0056]
Specifically, when the power supply quantity exceeds the upper limit value of the power supply occupancy rate, the power unit resistance Rpu is set to a high resistance value by adjusting the various power supply characteristic values. When the value is below the lower limit value, the power unit resistance Rpu is set to a low resistance value. As a result, the target value of the core IR drop value CORE-IRdrop is adjusted.
[0057]
Thereafter, the above-described series of processing is repeatedly performed until the power supply quantity determined in step 27 satisfies a predetermined power occupancy standard, and the power supply design is completed.
After such power supply design processing is completed, LSI power supply design is performed in the same manner as in step 56 shown in FIG. 8 according to the amount of power supply determined in step 27, and cell placement is performed in the same manner as in steps 57 to 59. / After wiring, power supply network analysis is performed to finish LSI design.
[0058]
In the power supply design process described above, the power supply quantity that achieves the target IR drop value VDD-IRdrop is estimated in advance before designing the layout of the LSI, so that an IR drop violation occurs in the power supply network analysis after the layout design. There is no.
[0059]
FIG. 6 is an explanatory diagram illustrating a specific example relating to the power supply design process of the present embodiment.
Here, for example, a case where three power I / Os 33 (power I / O resistors: Rio) are arranged along each side of the core 32 in the chip 31 will be described. As described above, the bonding wire resistance Rb and the package resistance Rp are connected in series to the outside of each power supply I / O 33, and the VDD power supply voltage 34 (indicated by V in the figure) is supplied to the core portion 32 through them. ) Is supplied.
[0060]
Now, in this LSI, for example, the core power consumption POWERcore is 1 W, the core power supply voltage VDD is 1.3 V, the minimum voltage that guarantees the operation of the LSI is 1.2 V, and the IR drop value VDD-IRdrop on the VDD power supply side is Assuming 50% of the IR drop value IRdrop of the entire LSI, the IR drop value VDD-IRdrop is
(VDD-IRdrop) = (1.3-1.2) × 0.5 = 0.05 (V)
It becomes.
[0061]
Therefore, when the resistance values of the package resistance Rp, the bonding wire resistance Rb, and the power supply I / O resistance Rio are variable, the target value of the core IR drop value CORE-IRdrop is:
(CORE-IRdrop) ≦ 0.05−1 / 1.3 / (3 × 4) × (Rp + Rb + Rio)
It becomes. That is, the power unit resistance Rpu satisfying this conditional expression is calculated, and the power supply quantity may be estimated from the resistance value.
[0062]
Note that the power supply design process of the present embodiment as described above is performed using a computer system (automatic design apparatus) composed of a general CAD (Computer Aided Design) apparatus, as shown in FIG. The computer system 41 includes a central processing unit (hereinafter referred to as CPU) 42, a memory 43, a storage device 44, a display device 45, an input device 46 and a drive device 47, which are connected to each other via a bus 48.
[0063]
The CPU 42 executes a program using the memory 43 and realizes processing necessary for the layout design of the semiconductor memory device. The memory 43 usually includes a cache memory, a system memory, a display memory, and the like. The display device 45 is used for display of a layout display, a parameter input screen, and the like, and usually a CRT, LCD, PDP or the like is used for this. The input device 46 is used to input a request or instruction from a user and parameters, and a keyboard and a mouse device are used for this.
[0064]
The storage device 44 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, and the like. In the storage device 44, program data (hereinafter referred to as a program) for realizing the power supply design process of the present embodiment, the above-described IR drop characteristics (see FIG. 3), a power supply quantity table (see FIG. 4A), etc. The various data files (hereinafter referred to as files) are stored. In response to an instruction from the input device 46, the CPU 42 appropriately transfers data stored in the program and various files to the memory 43, and sequentially executes it. The storage device 44 is also used as a database.
[0065]
A program executed by the CPU 42 is provided on the recording medium 49. The drive device 47 drives the recording medium 49 and accesses the stored contents. The CPU 42 reads a program from the recording medium 49 via the drive device 47 and installs it in the storage device 44.
[0066]
As the recording medium 49, an arbitrary recording medium such as a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM,...), A magneto-optical disk (MO, MD,...) Can be used. The recording medium 49 includes a medium on which a program uploaded or downloaded via a communication medium is recorded, and a disk device.
[0067]
As described above, according to the present embodiment, the following effects can be obtained.
(1) An equivalent circuit model in which the core portion 11 is divided by a plurality of power units 13 each having the same electrically characteristic is created, and a power unit resistance Rpu corresponding to a target IR drop value based on various power supply characteristic values. Is calculated. Then, the power supply quantity equivalent to the power unit resistance Rpu is estimated according to the power supply quantity table prepared in advance according to the number of wiring layers to which the power supply wiring can be assigned. Thereby, it is possible to estimate the power supply quantity with high accuracy before designing the layout, and it is possible to easily optimize the power supply wiring by preventing excessive setting of the power supply pattern and shortage of the power supply pattern.
[0068]
(2) By estimating the power supply quantity from the viewpoint of the IR drop value IRdrop that guarantees the operation of the LSI, various power supply quantities required for power supply design such as the number of wiring layers and the number of power supply I / Os are estimated with high accuracy. It becomes possible. Furthermore, since the chip size is also uniquely determined, the number of LSI design work steps can be reduced as compared with the prior art. Thereby, it is possible to shorten the LSI design time while optimizing the power supply wiring.
[0069]
(3) By setting the upper limit value of the power occupancy according to the number of wiring layers and judging whether or not the power supply quantity exceeds the upper limit value, it is possible to estimate the power supply quantity while ensuring signal wiring performance. it can.
[0070]
(4) Set the lower limit value of the power supply occupancy rate according to the number of wiring layers, and make effective use of each wiring layer that can allocate power supply wiring by judging whether the power supply quantity is below this lower limit value It is possible to estimate the optimum amount of power supply that can be performed.
[0071]
(5) In this embodiment, the power supply quantity is estimated with high accuracy before layout design, so that no IR drop violation occurs in the power network analysis after design. As a result, the number of LSI redesigns can be reduced, and the design cost can be reduced.
[0072]
(6) In the present embodiment, a power supply quantity table in which a power supply quantity corresponding to each of a plurality of types of power unit resistances Rpu is calculated and tabulated according to the number of wiring layers to which power supply wiring can be allocated is created in advance. The power supply quantity can be easily estimated according to the table.
[0073]
In addition, you may implement the said embodiment in the following aspects.
The mode of the power supply quantity table that defines the relationship between the power unit resistance Rpu and the power supply quantity is not limited to that shown in FIG.
[0074]
In the above embodiment, the upper limit value and the lower limit value of the power occupancy ratio do not necessarily need to be set for each wiring layer, and may be set as appropriate according to the number of wiring layers to which power wiring can be assigned.
[0075]
The characteristics of the above embodiment are summarized as follows.
(Supplementary note 1) A method for designing a semiconductor integrated circuit device, in which a power supply is designed based on an estimated amount of power supply wiring per unit area,
Dividing the core part by a plurality of unit circuits each having an electrically equivalent characteristic, and calculating a resistance value per unit circuit corresponding to an IR drop value in the core part region;
Calculating a power supply quantity that is equivalent to a power supply wiring amount equivalent to a resistance value set per unit circuit;
A method for designing a semiconductor integrated circuit device, comprising:
(Supplementary Note 2) The IR drop value in the core region is
It is set based on power consumption consumed in the core part, power supply voltage supplied to the core part, and a plurality of power supply characteristic values that determine IR drop values outside the core part region. A method for designing a semiconductor integrated circuit device according to appendix 1.
(Supplementary Note 3) The plurality of unit circuits include a resistance network composed of a plurality of resistors connected in a substantially cross shape and a current source connected to the center of the resistance network, and each current source is consumed by a core portion. 3. The method of designing a semiconductor integrated circuit device according to appendix 1 or 2, wherein an equivalent current source obtained by equally dividing the consumed current is set.
(Supplementary Note 4) A power supply quantity table that is calculated in advance according to the number of wiring layers to which power supply wiring can be allocated is created by calculating in advance the power supply quantity that is equivalent to the resistance value set per unit circuit. The method of designing a semiconductor integrated circuit device according to any one of appendices 1 to 3, wherein the power supply quantity is calculated based on the power supply quantity table.
(Supplementary note 5) The method for designing a semiconductor integrated circuit device according to supplementary note 4, wherein a power occupancy is set for each wiring layer in accordance with the number of wiring layers to which the power supply wiring can be assigned.
(Supplementary Note 6) The method for designing a semiconductor integrated circuit device according to Supplementary Note 5, wherein the power supply occupancy is a ratio of a power supply wiring amount per unit circuit.
(Additional remark 7) The upper limit value of the said power supply occupation rate is set so that the signal wiring property of each wiring layer may be ensured according to the number of wiring layers which can allocate the said power supply wiring. A method for designing a semiconductor integrated circuit device according to the description.
(Supplementary Note 8) When the power supply quantity exceeds the upper limit value of the power supply occupancy, the number of wiring layers to which the power supply wiring can be allocated is increased, or the plurality of power supply characteristic values are adjusted to adjust the unit circuit. 8. The method of designing a semiconductor integrated circuit device according to appendix 7, wherein the resistance value per unit is set high.
(Supplementary note 9) The semiconductor integrated circuit device according to any one of supplementary notes 5 to 8, wherein a lower limit value of the power supply occupation ratio is further set according to the number of wiring layers to which the power supply wiring can be assigned. Design method.
(Supplementary Note 10) When the power supply quantity is below the lower limit value of the power supply occupancy rate, the number of wiring layers to which the power supply wiring can be assigned is reduced, or the plurality of power supply characteristic values are adjusted to adjust the unit circuit. 10. The method of designing a semiconductor integrated circuit device according to appendix 9, wherein the resistance value per contact is set low.
(Supplementary Note 11) A design apparatus for a semiconductor integrated circuit device that performs power supply design based on a power supply quantity in which an amount of power supply wiring per unit area is estimated,
Means for dividing a core part by a plurality of unit circuits each having an electrically equivalent characteristic, and calculating a resistance value per unit circuit corresponding to an IR drop value in the core part region;
Means for calculating a power supply quantity that is equivalent to a power supply wiring amount equivalent to a resistance value set per unit circuit;
An apparatus for designing a semiconductor integrated circuit device, comprising:
[0076]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a design method and a design apparatus for a semiconductor integrated circuit device that can easily optimize power supply wiring.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating an equivalent circuit model of a VDD power supply network according to an embodiment.
FIGS. 2A and 2B are explanatory views showing an equivalent circuit model in which a core portion is divided by a power unit. FIG. 2A is an explanatory view of the core portion, and FIG. 2B is an explanatory view of the power unit.
FIG. 3 is an explanatory diagram showing power unit resistance-IR drop characteristics;
4A and 4B are explanatory diagrams showing a relationship between a power unit resistance and a power supply quantity, where FIG. 4A is an explanatory view of a power supply quantity table, and FIG. 4B is an explanatory view of a power supply occupation rate;
FIG. 5 is a flowchart showing a power supply design process.
FIG. 6 is an explanatory diagram illustrating a specific example related to a power supply design process.
FIG. 7 is a schematic configuration diagram of a computer system.
FIG. 8 is a flowchart showing conventional LSI design.
[Explanation of symbols]
11 Core part
13 Power unit as unit circuit
Rpu Power unit resistance as a resistance value per unit circuit
CORE-IRdrop Core IR drop value as IR drop value in the core area

Claims (8)

A design method of a semiconductor integrated circuit device by a design device that performs power supply design based on an estimated amount of power supply wiring per unit area,
The step of executing the design apparatus includes:
The central processing unit included in the design apparatus divides the core part by a plurality of unit circuits each having an electrically equivalent characteristic, and calculates a resistance value per unit circuit corresponding to the IR drop value in the core part region. Steps,
The central processing unit calculates in advance a power supply quantity that is equivalent to a power supply wiring quantity equivalent to a resistance value set per unit circuit, and a power supply quantity table tabulated according to the number of wiring layers to which power supply wiring can be assigned create and store the power supply amount table in the storage device, it viewed including the steps of calculating the power amount based on the power supply amount table, a,
The IR drop value in the core area is
It is set based on power consumption consumed in the core part, power supply voltage supplied to the core part, and a plurality of power supply characteristic values that determine IR drop values outside the core part region. A method for designing a semiconductor integrated circuit device.   The plurality of unit circuits include a resistance network composed of a plurality of resistors connected in a substantially cross shape and a current source connected to the center of the resistance network,
  2. The method of designing a semiconductor integrated circuit device according to claim 1, wherein the central processing unit sets an equivalent current source obtained by equally dividing the current consumption consumed by the core unit for each current source.   3. The semiconductor integrated circuit device according to claim 1, wherein a power occupancy for each wiring layer set in accordance with the number of wiring layers to which the power wiring can be allocated is stored in the storage device. Design method.   The central processing unit sets an upper limit value of the power occupancy rate so as to ensure signal wiring property of each wiring layer according to the number of wiring layers to which the power wiring can be allocated. 4. A method for designing a semiconductor integrated circuit device according to 3.   When the amount of power supply exceeds the upper limit value of the power supply occupancy rate, the central processing unit increases the number of wiring layers to which the power supply wiring can be allocated, or adjusts the plurality of power supply characteristic values. 5. The method of designing a semiconductor integrated circuit device according to claim 4, wherein the resistance value per unit circuit is set high.   6. The semiconductor according to claim 3, wherein the central processing unit further sets a lower limit value of the power occupancy rate in accordance with the number of wiring layers to which the power supply wiring can be assigned. A method for designing an integrated circuit device.   When the central processing unit is less than the lower limit value of the power supply occupancy, the central processing unit reduces the number of wiring layers to which the power supply wiring can be allocated, or adjusts the plurality of power supply characteristic values. 7. The method for designing a semiconductor integrated circuit device according to claim 6, wherein the resistance value per unit circuit is set low.   A design apparatus for a semiconductor integrated circuit device that performs power supply design based on an estimated amount of power supply wiring per unit area,
  Means for dividing a core part by a plurality of unit circuits each having an electrically equivalent characteristic, and calculating a resistance value per unit circuit corresponding to an IR drop value in the core part region;
  A method for calculating the amount of power supply equivalent to the amount of power supply wiring equivalent to the resistance value set per unit circuit. Stepped
An apparatus for designing a semiconductor integrated circuit device, comprising:

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