JP4120450B2 - Electronic circuit driving method, electronic circuit, electro-optical device driving method, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic circuit driving method, an electronic circuit, an electro-optical device driving method, an electro-optical device, and an electronic apparatus.
[0002]
[Prior art]
For example, one of display displays as an electro-optical device is a display display in which each pixel circuit includes a drive transistor that controls an organic EL element.
[0003]
Each pixel circuit is connected to a scanning line driving circuit and a data line driving circuit, and a pixel circuit is selected by a scanning signal output from the scanning line driving circuit, and a data line driving circuit is connected to the selected pixel circuit. The data signal output from is supplied. The organic EL element emits light when the driving transistor supplies a driving current according to the magnitude of the data signal to the organic EL element (see Patent Document 1).
[0004]
[Patent Document 1]
International Publication No. WO98 / 36407 Pamphlet
[0005]
[Problems to be solved by the invention]
In a display device including an electro-optical element such as an organic EL element or a liquid crystal element, in order to improve moving image characteristics, a so-called impulse driving method for shortening a driving period for driving the electro-optical element within one frame is one promising method. Is the method. On the other hand, when displaying a still image, it may be better not to shorten the driving period of the electro-optic element. Therefore, the object is to drive an electronic circuit, an electronic circuit, an electro-optical device driving method, an electro-optical device, and an electronic apparatus that can suppress a change in luminance that occurs when the driving period of the electro-optical element is switched. Is to provide.
[0006]
[Means for Solving the Problems]
An electronic circuit driving method of the present invention includes an electronic element, and a first transistor and a second transistor that can be electrically connected to the electronic element, and at least one of the first transistor and the second transistor. A method of driving an electronic circuit that supplies current to the electronic element through a single transistor, wherein the electronic element is passed through the first transistor and not through the second transistor, and A first method for supplying a current and a second method for supplying a second current to the electronic element via the first transistor and the second transistor can be switched, and the second method In the method, the length of the period for supplying the second current is shorter than the length of the period for supplying the first current in the first method. The gain coefficient of the first transistor and the gain of the second transistor are set so that the current per frame period of the first current is equal to the current per frame period of the second current for the data signal. A ratio with a coefficient is set.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection And a ninth control terminal connected to the first terminal; a ninth terminal; a tenth terminal; and a fifth control terminal; wherein the ninth terminal serves as the first control terminal. The eleventh terminal includes a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal. The twelfth terminal may be connected to the second terminal, and the twelfth terminal may be composed of a fourth switching element connected to one data line.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection A capacitor including the capacitive element connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal; the thirteenth terminal connected to the first connection terminal; The fourteenth terminal may be composed of a fifth switching element connected to one data line.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection And the capacitive element children are connected to the first terminal, a fifteenth terminal and a sixteenth terminal and a eighth control terminal of said fifteenth terminal of said first end A third transistor connected to the first and the eighth control terminal connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal; The seventeenth terminal includes a sixth switching element connected to the first connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, and the eighteenth terminal and the tenth control terminal. Sixteen terminals may be connected to the nineteenth terminal and the twentieth terminal may be composed of a seventh switching element connected to one data line.
The electronic circuit of the present invention includes a capacitor element that accumulates electric charge according to a data signal supplied via a data line, and a first transistor that is set in a conductive state according to the electric charge accumulated in the capacitor element. The second transistor whose conduction state is set according to the charge accumulated in the capacitor element is connected to the second transistor, and is turned on so as to correspond to the conduction state of the second transistor. A first switching element that passes a first current of a level, the first transistor and the first switching element are connected, and the first switching element is turned on so that the first current flows. And a second switching element for passing a second current at a level corresponding to the conduction state of the first transistor, and the driving capability of the first transistor is increased. , B is the sum of the drive capability of the first transistor and the drive capability of the second transistor, C is the period during which both the first switching element and the second switching element are turned on, When the period during which the switching element is turned off and the second switching element is turned on is D, the driving capability of the first transistor and the second transistor are set so as to satisfy the relationship of A: B = C: D. The driving capability of the transistor is set.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection And a ninth control terminal connected to the first terminal; a ninth terminal; a tenth terminal; and a fifth control terminal; wherein the ninth terminal serves as the first control terminal. The eleventh terminal includes a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal. The fourth terminal may be connected to the second terminal, and the twelfth terminal may be connected to one data line.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection A capacitor including the capacitive element connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal; the thirteenth terminal connected to the first connection terminal; The fourteenth terminal may include a fifth switching element connected to one data line.
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , Fifth terminal and sixth terminal And a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, an eighth terminal, and a fourth control terminal. And the seventh terminal comprises the second switching element connected to the second terminal and the sixth terminal, a first connection terminal and a second connection terminal, and the first connection A capacitor having a terminal connected to the first control terminal, a second connection terminal connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal; A third transistor in which the fifteenth terminal is connected to the first terminal, the eighth control terminal is connected to the first control terminal, and a seventeenth terminal. An eighteenth terminal and a ninth control terminal, wherein the seventeenth terminal is connected to the first connection terminal. A sixth switching element, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, wherein the eighteenth terminal and the sixteenth terminal are connected to the nineteenth terminal, The twentieth terminal may include a seventh switching element connected to one data line.
In the electronic circuit driving method, an electronic element or a current driving element may be connected to the eighth terminal.
The electro-optical device driving method of the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits each including an electro-optical element disposed corresponding to an intersection of the scanning lines and the data lines. Each of the plurality of unit circuits further includes a first transistor and a second transistor whose conduction state is set according to the electric charge accumulated in the capacitor element. Storing a charge corresponding to image data supplied via the data line to the capacitive element of the unit circuit connected to the selected scanning line among the plurality of scanning lines; and It is determined whether the display data is data for display or data for display of a still image, and when it is determined that the image data is display of a still image, the electro-optic element, the second transistor, When the electro-optical element is supplied with a current corresponding to the electric charge stored in the capacitive element in a predetermined period, or when it is determined that the image data is a moving image display, the electro-optical element Supplying a current corresponding to the electric charge stored in the capacitive element to the electro-optic element in a period shorter than the predetermined period in a state where the element and the second transistor are electrically connected;
It is characterized by including.
In the driving method of the electro-optical device, each of the plurality of unit circuits includes the first transistor including a first terminal, a second terminal, and a first control terminal, and a third terminal. A fourth terminal and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element including a second transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; A second switching element including a first terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal; And the second connection terminal, the first connection terminal is connected to the first control terminal, The second connection terminal includes the capacitive element connected to the first terminal, a ninth terminal, a tenth terminal, and a fifth control terminal, wherein the ninth terminal is the first control terminal. A third switching element connected to the terminal, the tenth terminal connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal, The eleventh terminal may be connected to the second terminal, and the twelfth terminal may be composed of a fourth switching element connected to one data line of the plurality of data lines. .
In the driving method of the electro-optical device, each of the plurality of unit circuits includes the first transistor including a first terminal, a second terminal, and a first control terminal, and a third terminal. A fourth terminal and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element including a second transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; A second switch, wherein the seventh terminal is connected to the second terminal and the sixth terminal. A first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. The capacitive element, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, wherein the thirteenth terminal is connected to the first connection terminal, and the fourteenth terminal is the plurality of the plurality of terminals. You may comprise from the 5th switching element connected to one data line of the data lines.
In this driving method, each of the plurality of unit circuits includes the first transistor having the first terminal, the second terminal, and the first control terminal, the third terminal, and the fourth terminal. And the second control terminal, the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element having a fifth terminal, a sixth terminal, and a third control terminal, the fifth terminal being connected to the fourth terminal, a seventh terminal, and a third terminal A second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second connection. The first connection terminal is connected to the first control terminal, and the second connection terminal is The capacitor connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, wherein the fifteenth terminal is connected to the first terminal, An eighth control terminal includes a third transistor connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, and the seventeenth terminal A sixth switching element connected to the first connection terminal; a nineteenth terminal; a twentieth terminal; a tenth control terminal; and a tenth control terminal. The seventh switching element may be connected to 19 terminals, and the twentieth terminal may be connected to one data line of the plurality of data lines.
The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits each including an electro-optical element arranged corresponding to an intersection of the scanning lines and the data lines. Each of the plurality of unit circuits includes a capacitive element that accumulates charges in accordance with a data signal supplied via the data line, and a charge that is accumulated in the capacitive element. The first transistor in which the conduction state is set, the second transistor in which the conduction state is set in accordance with the charge accumulated in the capacitor, and the second transistor are connected to be turned on. A first switching element for passing a first current of a level corresponding to a conduction state of the second transistor; and the first switch connected to the first transistor and the first switching element. And a second switching element that passes the second current at a level corresponding to the conduction state of the first transistor together with the first current and supplies the second current to the electro-optic element. , A is the driving capability of the first transistor, B is the sum of the driving capability of the first transistor and the driving capability of the second transistor, and both the first switching element and the second switching element are on. Assuming that C is a period during which the first switching element is turned off and D is a period during which the first switching element is turned off and the second switching element is turned on, the relationship A: B = C: D is satisfied. The driving capability of the first transistor and the driving capability of the second transistor are set.
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, the first connection terminal is connected to the first control terminal, and the first connection terminal The connection terminal includes the capacitive element connected to the first terminal, a ninth terminal, a tenth terminal, and a fifth control terminal, and the ninth terminal is the first control terminal. And the tenth terminal comprises a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal, The eleventh terminal may be connected to the second terminal, and the twelfth terminal may include a fourth switching element connected to one data line of the plurality of data lines.
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, the first connection terminal is connected to the first control terminal, and the first connection terminal The capacitor has a connection terminal connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, and the thirteenth terminal is connected to the first connection terminal. The fourteenth terminal may include a fifth switching element connected to one data line of the plurality of data lines.
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, the first connection terminal is connected to the first control terminal, and the first connection terminal The capacitor has a connection terminal connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, and the fifteenth terminal is connected to the first terminal. The eighth control terminal includes a third transistor connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, and the seventeenth control terminal. A sixth switching element connected to the first connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, the eighteenth terminal and the sixteenth terminal. May be connected to the nineteenth terminal, and the twentieth switching element may be connected to one data line of the plurality of data lines.
  The electronic circuit driving method of the present invention is an electronic circuit driving method including an electronic element, and a first transistor and a second transistor that can be electrically connected to the electronic element. And a period in which a current is supplied to the electronic element via at least one of the second transistors, and a current is supplied to the electronic element via the first transistor and the second transistor; This is different from a period in which current is supplied to the electronic element through the first transistor when current passes through the first transistor and current does not pass through the second transistor.
[0007]
According to this, only the first current generated by the first transistor is supplied to the electronic element by electrically disconnecting the second transistor and the electronic element. Alternatively, a current obtained by combining the first current and the second current generated by the second transistor by electrically connecting the second transistor and the electronic element is an electronic element. To supply. As a result, the electronic element can be driven in accordance with the first current or the current obtained by combining the first current and the second current.
[0008]
According to the electronic circuit driving method of the present invention, the electronic element, the capacitive element that accumulates the electric charge according to the data signal, and the first current that has the current level according to the electric charge accumulated in the capacitive element are generated. The electronic circuit further includes a second transistor that generates a second current having a current level corresponding to a charge stored in the capacitor, and the electronic circuit further includes: A first switching element that is connected to a second transistor and is turned on to pass the second current, is connected to the first transistor and the first switching element, and is connected to the first switching element. And a second switching element that passes the second current together with the first current by being turned on together with the element, the first switching element and the front A first step of accumulating electric charge according to a data signal in the capacitive element with the second switching element turned off, and the second switching element turned on with the first switching element turned on. And a second step of turning on or off the switching element.
[0009]
According to this, only the first current generated by the first transistor is supplied to the electronic element by turning off the first switching element and turning on the second switching element. Alternatively, by turning on both the first switching element and the second switching element, a current obtained by combining the first current and the second current is supplied to the electronic element. In other words, currents having different current levels can be supplied to the electronic element by on / off controlling the first switching element.
[0010]
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection And a ninth control terminal connected to the first terminal; a ninth terminal; a tenth terminal; and a fifth control terminal; wherein the ninth terminal serves as the first control terminal. The eleventh terminal includes a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal. The twelfth terminal may be connected to the second terminal, and the twelfth terminal may be composed of a fourth switching element connected to one data line of the plurality of data lines.
[0011]
According to this, in the electronic circuit configured as described above, current having different current levels can be supplied to the electronic element by controlling the first switching element on and off.
[0012]
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection A capacitor including the capacitive element connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal; the thirteenth terminal connected to the first connection terminal; The fourteenth terminal may include a fifth switching element connected to one data line of the plurality of data lines.
[0013]
According to this, in the electronic circuit configured as described above, current having different current levels can be supplied to the electronic element by controlling the first switching element on and off.
[0014]
In the electronic circuit driving method, the electronic circuit includes the first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal; , A fifth terminal, a sixth terminal, and a third control terminal, the first switching element having the fifth terminal connected to the fourth terminal, a seventh terminal, and a third terminal The second switching element having the eighth terminal and the fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal and the second terminal. A connection terminal, wherein the first connection terminal is connected to the first control terminal and the second connection The capacitor includes the capacitive element connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, and the fifteenth terminal is connected to the first terminal. The eighth control terminal includes a third transistor connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal; A terminal including a sixth switching element connected to the first connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal; and the eighteenth terminal and the sixteenth terminal The seventh switching element may be connected to the nineteenth terminal, and the twentieth terminal is connected to one of the plurality of data lines.
[0015]
According to this, in the electronic circuit configured as described above, current having different current levels can be supplied to the electronic element by controlling the first switching element on and off.
[0016]
The electronic circuit of the present invention includes a capacitor element that accumulates electric charge according to a data signal supplied via a data line, and a first transistor that is set in a conductive state according to the electric charge accumulated in the capacitor element. The second transistor whose conduction state is set according to the charge accumulated in the capacitor element is connected to the second transistor, and is turned on so as to correspond to the conduction state of the second transistor. A first switching element that passes a first current of a level, and is connected to the first transistor and the first switching element, and is turned on together with the first switching element, so that the first current And a second switching element for passing a second current of a level corresponding to the conduction state of the first transistor.
[0017]
According to this, it is possible to provide an electronic circuit that allows currents having different current levels to pass through the second switching element by controlling on / off of the first switching element.
[0018]
In this electronic circuit, the driving capability of the first transistor and the driving capability of the second transistor are the driving capability of the first transistor, the driving capability of the first transistor, and the driving capability of the second transistor. The ratio to the sum of the capacities is that the first switching element is turned off and the second switching element is turned on, and both the first switching element and the second switching element are turned on. It may be set so as to be the same as the ratio to the period to be performed.
[0019]
According to this, the current flowing through the second switching element when the first switching element is off and the second switching element is on, and the first switching element and the second switching element are In both cases, the current level per predetermined time of the current flowing through the second switching element in the ON state can be made the same.
[0020]
In this electronic circuit, the electronic circuit includes the first transistor having a first terminal, a second terminal, and a first control terminal, a third terminal, a fourth terminal, and a second terminal. A second terminal having a control terminal, the third terminal connected to the first terminal, and the second control terminal connected to the first control terminal; The first switching element, the seventh terminal, and the eighth terminal, wherein the fifth terminal is connected to the fourth terminal. And a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, a first connection terminal and a second connection terminal, The first connection terminal is connected to the first control terminal, and the second connection terminal is the The capacitor connected to one terminal, a ninth terminal, a tenth terminal, and a fifth control terminal, and the ninth terminal is connected to the first control terminal. The tenth terminal includes a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal, wherein the eleventh terminal is the In addition to being connected to the second terminal, the twelfth terminal may include a fourth switching element connected to one data line of the plurality of data lines.
[0021]
According to this, in the electronic circuit configured as described above, an electronic circuit capable of passing currents having different current levels through the second switching element by controlling on / off of the first switching element. Can be provided.
[0022]
In this electronic circuit, the electronic circuit includes the first transistor having a first terminal, a second terminal, and a first control terminal, a third terminal, a fourth terminal, and a second terminal. A second terminal having a control terminal, the third terminal connected to the first terminal, and the second control terminal connected to the first control terminal; The first switching element, the seventh terminal, and the eighth terminal, wherein the fifth terminal is connected to the fourth terminal. And a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, a first connection terminal and a second connection terminal, The first connection terminal is connected to the first control terminal, and the second connection terminal is the The capacitor connected to one terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, the thirteenth terminal being connected to the first connection terminal, and the fourteenth terminal. And a fifth switching element connected to one data line of the plurality of data lines.
[0023]
According to this, in the electronic circuit configured as described above, an electronic circuit capable of passing currents having different current levels through the second switching element by controlling on / off of the first switching element. Can be provided.
[0024]
In this electronic circuit, the electronic circuit includes the first transistor having a first terminal, a second terminal, and a first control terminal, a third terminal, a fourth terminal, and a second terminal. A second terminal having a control terminal, the third terminal connected to the first terminal, and the second control terminal connected to the first control terminal; The first switching element, the seventh terminal, and the eighth terminal, wherein the fifth terminal is connected to the fourth terminal. And a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal, a first connection terminal and a second connection terminal, The first connection terminal is connected to the first control terminal, and the second connection terminal is the The capacitor connected to one terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, wherein the fifteenth terminal is connected to the first terminal, and the eighth terminal A control terminal including a third transistor connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, the seventeenth terminal being the first control terminal. A sixth switching element connected to one connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, wherein the eighteenth terminal and the sixteenth terminal are the nineteenth terminal. A seventh switching element connected to a terminal, wherein the twentieth terminal is connected to one data line of the plurality of data lines.
[0025]
According to this, in the electronic circuit configured as described above, an electronic circuit capable of passing currents having different current levels through the second switching element by controlling on / off of the first switching element. Can be provided.
[0026]
In this electronic circuit, an electronic element or a current driving element may be connected to the eighth terminal.
According to this, it is possible to provide an electronic circuit that can supply currents having different current levels to the electronic element or the current driving element by controlling on / off of the first switching element.
[0027]
The driving method of the electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits having electro-optical elements arranged corresponding to the intersections of the scanning lines and the data lines. Each of the plurality of unit circuits further includes a first transistor and a second transistor whose conduction state is set according to the electric charge accumulated in the capacitor element. Storing a charge corresponding to image data supplied via the data line to the capacitive element of the unit circuit connected to the selected scanning line among the plurality of scanning lines; and the electro-optic element; A current corresponding to the electric charge accumulated in the capacitor element is supplied to the electro-optic element in a state where the second transistor is electrically disconnected, or the electro-optic element and the second transistor are supplied. A current corresponding to preparative electrically the charge accumulated in the capacitor to the electro-optical element in the connected state and supplying.
[0028]
According to this, only the first current generated by the first transistor is supplied to the electro-optic element by turning off the first switching element and turning on the second switching element. Alternatively, a current obtained by combining the first current and the second current is supplied to the electro-optical element by turning on both the first switching element and the second switching element. That is, currents having different current levels can be supplied to the electro-optic element by controlling the first switching element to be turned on / off. Accordingly, one frame period is used as a period for supplying a current corresponding to the electric charge accumulated in the capacitive element to the electro-optic element, or a shorter time is accumulated in the capacitive element in the electro-optic element. When controlling the light emission of the electro-optical element by a so-called hold type display method used as a period for supplying a current according to the charge, the first switching element is turned off and the second switching element is turned on. Only the first current is supplied to the electro-optic element. Further, in the case of controlling the light emission of the electro-optical element by a so-called impulse-type display method in which a current corresponding to the electric charge accumulated in the capacitive element is instantaneously supplied to the electro-optical element, the first switching element and Both the second switching elements are turned on to supply the first current and the second current to the electro-optical element. By doing so, it is possible to drive an electro-optical device that can suppress a change in luminance of the electro-optical element that occurs when the hold-type display method and the impulse-type display method are switched.
[0029]
In the driving method of the electro-optical device, each of the plurality of unit circuits includes the first transistor including a first terminal, a second terminal, and a first control terminal, and a third terminal. A fourth terminal and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element including a second transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; A second switching element including a first terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal; And the second connection terminal, the first connection terminal is connected to the first control terminal, The second connection terminal includes the capacitive element connected to the first terminal, a ninth terminal, a tenth terminal, and a fifth control terminal, wherein the ninth terminal is the first control terminal. A third switching element connected to the terminal, the tenth terminal connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal, The eleventh terminal may be connected to the second terminal, and the twelfth terminal may be composed of a fourth switching element connected to one data line of the plurality of data lines. Good.
[0030]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; Driving an electro-optical device that can suppress a change in luminance of the electro-optical element that occurs when switching to a so-called impulse-type display method that instantaneously supplies a current corresponding to the accumulated charge to the electro-optical element. Can do.
[0031]
In the driving method of the electro-optical device, each of the plurality of unit circuits includes the first transistor including a first terminal, a second terminal, and a first control terminal, and a third terminal. A fourth terminal and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element including a second transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; A second switching element including a first terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal; And the second connection terminal, the first connection terminal is connected to the first control terminal, 2 connection terminals comprising the capacitive element connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, wherein the thirteenth terminal serves as the first connection terminal. The 14th terminal may be comprised from the 5th switching element connected to one data line among these data lines.
[0032]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; Driving an electro-optical device that can suppress a change in luminance of the electro-optical element that occurs when switching to a so-called impulse-type display method that instantaneously supplies a current corresponding to the accumulated charge to the electro-optical element. Can do.
[0033]
In the driving method of the electro-optical device, each of the plurality of unit circuits includes the first transistor including a first terminal, a second terminal, and a first control terminal, and a third terminal. A fourth terminal and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is connected to the first control terminal. A first switching element including a second transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; A second switching element including a first terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal; And the second connection terminal, the first connection terminal is connected to the first control terminal, 2 connection terminals comprising the capacitive element connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, the fifteenth terminal being the first terminal A third transistor connected to the eighth control terminal and connected to the first control terminal; a seventeenth terminal, an eighteenth terminal, and a ninth control terminal; 17 includes a sixth switching element connected to the first connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, and the eighteenth terminal and the sixteenth control terminal. The terminal may be connected to the 19th terminal, and the 20th terminal may be composed of a seventh switching element connected to one data line of the plurality of data lines.
[0034]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; Driving an electro-optical device that can suppress a change in luminance of the electro-optical element that occurs when switching to a so-called impulse-type display method that instantaneously supplies a current corresponding to the accumulated charge to the electro-optical element. Can do.
[0035]
The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits each including an electro-optical element arranged corresponding to an intersection of the scanning lines and the data lines. Each of the plurality of unit circuits includes a capacitive element that accumulates charges in accordance with a data signal supplied via the data line, and a charge that is accumulated in the capacitive element. The first transistor in which the conduction state is set, the second transistor in which the conduction state is set in accordance with the charge accumulated in the capacitor, and the second transistor are connected to be turned on. A first switching element for passing a first current of a level corresponding to a conduction state of the second transistor; and the first switch connected to the first transistor and the first switching element. And a second switching element that passes the second current at a level corresponding to the conduction state of the first transistor together with the first current and supplies the second current to the electro-optic element. It was.
[0036]
According to this, only the first current generated by the first transistor is supplied to the electro-optic element by turning off the first switching element and turning on the second switching element. Alternatively, a current obtained by combining the first current and the second current is supplied to the electro-optical element by turning on both the first switching element and the second switching element. That is, it is possible to provide an electro-optical device that can supply currents having different current levels to the electro-optical element by controlling on / off of the first switching element.
[0037]
In this electro-optical device, the driving capability of the first transistor and the driving capability of the second transistor are the driving capability of the first transistor, the driving capability of the first transistor, and the driving capability of the second transistor. The ratio to the sum of the driving capabilities is such that the first switching element is turned off and the second switching element is turned on, and both the first switching element and the second switching element are turned on. It may be set so as to be the same as the ratio to the period of time.
[0038]
According to this, the luminance of the electro-optic element during the period in which the first switching element is turned off and the second switching element is turned on, and the first switching element and the second switching element The luminances of the electro-optic elements can be made the same during the period in which both are set to the on state.
[0039]
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, the first connection terminal is connected to the first control terminal, and the first connection terminal The connection terminal includes the capacitive element connected to the first terminal, a ninth terminal, a tenth terminal, and a fifth control terminal, and the ninth terminal is the first control terminal. And the tenth terminal comprises a third switching element connected to the second terminal, an eleventh terminal, a twelfth terminal, and a sixth control terminal, The eleventh terminal may be connected to the second terminal, and the twelfth terminal may include a fourth switching element connected to one data line of the plurality of data lines.
[0040]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; To provide an electro-optical device capable of suppressing a change in luminance of an electro-optical element that occurs when a so-called impulse-type display method is instantaneously supplied to the electro-optical element in accordance with accumulated electric charge. Can do.
[0041]
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the first connection terminal The capacitor has a connection terminal connected to the first terminal, a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, and the thirteenth terminal is connected to the first connection terminal. The fourteenth terminal may include a fifth switching element connected to one data line of the plurality of data lines.
[0042]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; To provide an electro-optical device capable of suppressing a change in luminance of an electro-optical element that occurs when a so-called impulse-type display method is instantaneously supplied to the electro-optical element in accordance with accumulated electric charge. Can do.
[0043]
In the electro-optical device, each of the plurality of unit circuits includes a first transistor including a first terminal, a second terminal, and a first control terminal, a third terminal, and a fourth terminal. A second control terminal, the third terminal being connected to the first terminal, and the second control terminal being connected to the first control terminal. A first switching element including a transistor, a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal; and a seventh terminal The second switching element, wherein the seventh terminal is connected to the second terminal and the sixth terminal, and the first connection terminal. A second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the first connection terminal The capacitor has a connection terminal connected to the first terminal, a fifteenth terminal, a sixteenth terminal, and an eighth control terminal, and the fifteenth terminal is connected to the first terminal. The eighth control terminal includes a third transistor connected to the first control terminal, a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, and the seventeenth control terminal. A sixth switching element connected to the first connection terminal, a nineteenth terminal, a twentieth terminal, and a tenth control terminal, the eighteenth terminal and the sixteenth terminal. May be connected to the 19th terminal, and the 20th terminal may include a seventh switching element connected to one data line of the plurality of data lines.
[0044]
According to this, by providing the unit circuit as described above, a period of time during which all the electro-optic elements are driven (one frame period) is supplied with a current corresponding to the electric charge accumulated in the capacitive element. A so-called hold-type display method in which a period of time used for supplying the current corresponding to the electric charge accumulated in the capacitive element is used for the electro-optic element or a time shorter than that is used for the capacitive element; To provide an electro-optical device capable of suppressing a change in luminance of an electro-optical element that occurs when a so-called impulse-type display method is instantaneously supplied to the electro-optical element in accordance with accumulated electric charge. Can do.
[0045]
In this electro-optical device, the electro-optical element may be an EL element. According to this, it is possible to suppress a change in luminance of the EL element that occurs when an image is displayed by switching between the hold type display method and the impulse type display method.
[0046]
In the electro-optical device, the EL element may have a light emitting layer made of an organic material.
According to this, it is possible to suppress a change in luminance of the organic EL element that occurs when an image is displayed by switching between the hold type display method and the impulse type display method.
[0047]
The electronic device in the present invention includes the electronic circuit.
According to this, it is possible to provide an electronic device including an electronic circuit that can pass currents having different current levels through the second switching element by controlling on / off of the first switching element. it can. In addition, the difference in current level supplied to the electronic element when this on / off control is performed can be suppressed.
[0048]
An electronic apparatus according to the present invention includes the electro-optical device.
According to this, in an electronic apparatus having an electro-optical device that can display an image by switching between the hold-type display method and the impulse-type display method, the electro-optical element when the display methods are switched. A difference in luminance can be suppressed. As a result, an electronic device with excellent display quality can be provided.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an electrical configuration of an organic EL display. FIG. 2 is a block circuit diagram showing an electrical configuration of the display panel unit and the data line driving circuit. FIG. 3 is a circuit diagram of the pixel circuit in the present embodiment.
[0050]
The organic EL display 10 includes a signal generation circuit 11, a display panel unit 12, a scanning line driving circuit 13, a data line driving circuit 14, and a display control circuit 15. The signal generation circuit 11, the scanning line driving circuit 13, the data line driving circuit 14, and the display control circuit 15 of the organic EL display 10 may be configured by independent electronic components. For example, each of the signal generation circuit 11, the scanning line driving circuit 13, the data line driving circuit 14, and the display control circuit 15 may be configured by a one-chip semiconductor integrated circuit device. Further, all or part of the signal generation circuit 11, the scanning line driving circuit 13, the data line driving circuit 14, and the display control circuit 15 is configured by a programmable IC chip, and the function is software by a program written in the IC chip. May be realized.
[0051]
The organic EL display 10 is a display that can be used by switching between a hold-type display method and an impulse-type display method. In the hold-type display method, a light emission period of each organic EL element OLED (see FIG. 3) formed on the display panel unit 12 is selected as one frame period (all scanning lines Y1 to Yn described later are selected in one cycle). The display method is set so as to be substantially equal to the (end period).
[0052]
The impulse display method is a set display method in which the light emission period of each organic EL element OLED is instantaneous. That is, in the impulse-type display method, a period (light emission period) in which a driving current Iel (see FIG. 3) described later corresponding to the charge accumulated in the holding capacitor Co (see FIG. 3) described later is supplied to the organic EL element OLED. In this display method, the storage capacitor Co is made shorter than a period (data writing period) in which charges corresponding to the data signal Idata are accumulated. In the present embodiment, the organic EL display 10 performs display using the hold-type display method when displaying a still image, and performs display using the impulse-type display method when displaying a moving image. It has become. In the present embodiment, the light emission period of the organic EL element OLED when displaying an image by the impulse type display method is set in advance to be ¼ that when the image is displayed by the hold type display method. Has been.
[0053]
The signal generation circuit 11 generates a scanning line driving signal SK and a data line driving signal DK for displaying an image on the display panel unit 12 based on image data D supplied from an external device (not shown). The signal generation circuit 11 outputs the scanning line driving signal SK to the scanning line driving circuit 13 and outputs the data line driving signal DK to the data line driving circuit 14.
[0054]
Further, the signal generation circuit 11 determines whether the image displayed on the display panel unit 12 is a still image or a moving image based on the image data D. When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image, the signal generation circuit 11 generates a display control signal GK to that effect and displays the generated display control signal GK as a display control circuit. 15 is output. When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image, the signal generation circuit 11 generates a display control signal GK to that effect and displays the generated display control signal GK as a display control circuit. 15 is output. Note that the determination of whether the image displayed on the display panel unit 12 is a still image or a moving image may be made based on image data for one frame of the display panel unit 12. Further, it may be performed based on image data for pixel circuits arranged corresponding to one or a plurality of scanning lines among n scanning lines Y1 to Yn described later.
[0055]
As shown in FIG. 2, the display panel unit 12 includes a plurality of pixel circuits 20 arranged in a matrix. Further, the display panel unit 12 extends along the row direction and m data lines X1 to Xm (m is a natural number) extending along the column direction of the pixel circuits 20 arranged in a matrix. N scanning lines Y1 to Yn (n is a natural number) provided. The pixel circuit 20 is disposed at a position corresponding to the intersection of the data lines X1 to Xm and the scanning lines Y1 to Yn. Each pixel circuit 20 is connected to corresponding data lines X1 to Xm and scanning lines Y1 to Yn, respectively.
[0056]
In addition, the display panel unit 12 includes a plurality of power supply lines VL. In the present embodiment, each power supply line VL extends in parallel with each of the scanning lines Y1 to Yn. Each power supply line VL is connected to each corresponding pixel circuit 20 and connected to a drive voltage supply line Lo extending along the column direction of the pixel circuit 20 disposed on the right end side of the display panel unit 12. It is connected. A driving voltage Voel is supplied to the driving voltage supply line Lo. Accordingly, the drive voltage Voel is supplied to each pixel circuit 20 via the drive voltage supply line Lo and the power supply line VL.
[0057]
Further, the display panel unit 12 includes a plurality of signal lines LS1 to LSn. Each signal line LS <b> 1 to LSn extends in parallel along the row direction of the pixel circuit 20. Each signal line LS1 to LSn is connected to the corresponding pixel circuit 20 and to the scanning line driving circuit 13 respectively. The signal lines LS <b> 1 to LSn supply timing signals SY <b> 1 to SYn described later output from the scanning line driving circuit 13 to the corresponding pixel circuits 20.
[0058]
In addition, the display panel unit 12 includes a plurality of control lines LD1 to LDn. In the present embodiment, the control lines LD1 to LDn are extended in parallel to the scanning lines Y1 to Yn. The control lines LD1 to LDn are connected to the pixel circuits 20 and to the display control circuit 15. The control lines LD1 to LDn supply a control signal DS (described later) output from the display control circuit 15 to the corresponding pixel circuit 20.
[0059]
The scanning line driving circuit 13 selects one scanning line among the scanning lines Y1 to Yn extended to the display panel unit 12 based on the scanning line driving signal SK output from the signal generation circuit 11. Scan signals SC1 to SCn (n is a natural number) are output to the selected scanning line.
[0060]
In addition, the scanning line driving circuit 13 generates timing signals SY1 to SYn (n is a natural number) for controlling the light emission period of the organic EL element OLED formed in each pixel circuit 20 based on the scanning line driving signal SK. At the same time, the generated timing signals SY1 to SYn are output to the respective pixel circuits 20 via the corresponding signal lines LS1 to LSn.
[0061]
As shown in FIG. 2, the data line driving circuit 14 includes a plurality of single line drivers 23. Each single line driver 23 is electrically connected to the corresponding pixel circuit 20 via the data lines X1 to Xm. Each single line driver 23 generates each data signal Idata based on the data line drive signal DK output from the signal generation circuit 11. Each single line driver 23 outputs the generated data signal Idata to the corresponding pixel circuit 20 via the corresponding data lines X1 to Xm. In the present embodiment, each data signal Idata is a current signal. Accordingly, each single line driver 23 generates a current value based on the data line drive signal DK, and the generated current value corresponds as the data signal Idata via the corresponding data lines X1 to Xm. Output to the pixel circuit 20.
[0062]
When the display control signal GK indicating that the image displayed on the display panel unit 12 is a still image is supplied from the signal generation circuit 11, the display control circuit 15 performs control switching described later that configures each pixel circuit 20. A control signal DS for turning off the transistor Qx is created. Further, when the display control signal GK that the image displayed on the display panel unit 12 is a moving image is supplied from the signal generation circuit 11, the display control circuit 15 turns on the control switching transistor Qx. A control signal DS is generated. Further, the display control circuit 15 outputs the created control signals DS to the pixel circuits 20 via the control lines LD1 to LDn, respectively.
[0063]
Next, the pixel circuit 20 of the organic EL display 10 configured as described above will be described with reference to FIG. Since the circuit configuration of each pixel circuit 20 is the same, only the pixel circuit 20 arranged at a position corresponding to the intersection of the nth scanning line Yn and the mth data line Xm is described for convenience of explanation. explain.
[0064]
As shown in FIG. 3, the pixel circuit 20 includes first and second drive transistors Qd1, Qd2, first and second switching transistors Qsw1, Qsw2, a start transistor Qst, and a control switching transistor Qx. The pixel circuit 20 includes a holding capacitor Co and an organic EL element OLED.
[0065]
The first and second drive transistors Qd1 and Qd2 are transistors that function as current sources for supplying current, respectively. The first and second switching transistors Qsw1 and Qsw2, the start transistor Qst, and the control switching transistor Qx are transistors that function as switching elements, respectively.
[0066]
The conductivity types of the first and second drive transistors Qd1 and Qd2 are each a p-type in this embodiment. Further, the conductivity types of the first and second switching transistors Qsw1, Qsw2, the start transistor Qst, and the control switching transistor Qx are n-type in this embodiment.
[0067]
The first and second drive transistors Qd1 and Qd2, the first and second switching transistors Qsw1 and Qsw2, the start transistor Qst, and the control switching transistor Qx are each usually composed of a TFT (thin film transistor). Yes.
[0068]
More specifically, the drain of the first drive transistor Qd1 is connected to the drain of the start transistor Qst. The source of the start transistor Qst is connected to the anode of the organic EL element OLED whose light emitting layer is made of an organic material, and the cathode of the organic EL element OLED is grounded. The gate of the start transistor Qst is connected to the signal line LSn together with the gates of the start transistors Qst of other pixel circuits 20 arranged in the row direction. That is, the start transistor Qst is ON / OFF controlled in accordance with the timing signal SYn output from the scanning line driving circuit 13 via the signal line LSn.
[0069]
The drain of the first drive transistor Qd1 is connected to the source of the first switching transistor Qsw1. The drain of the first switching transistor Qsw1 is connected to the data line Xm together with the drain of the first switching transistor Qsw1 of another pixel circuit 20 arranged in the column direction.
[0070]
Further, a second switching transistor Qsw2 is connected between the drain / gate of the first driving transistor Qd1. The gate of the second switching transistor Qsw2 is connected to the gate of the first switching transistor Qsw1 and to the scanning line Yn. Therefore, the first switching transistor Qsw1 and the second switching transistor Qsw2 are simultaneously turned on / off according to the scanning signal SCn output from the scanning line driving circuit 13 through the scanning line Yn.
[0071]
The gate of the first driving transistor Qd1 is connected to the first connection terminal E1 of the holding capacitor Co, and the second connection terminal E2 of the holding capacitor Co is connected to the source of the first driving transistor Qd1. . The holding capacitor Co accumulates charges according to the current level of the data signal Idata. The source of the first drive transistor Qd1 is connected to the power supply line VL so that the drive voltage Voel is supplied.
[0072]
Further, a second drive transistor Qd2 is connected to the first drive transistor Qd1 in parallel with the first drive transistor Qd1. Specifically, the gate of the first drive transistor Qd1 is connected to the gate of the second drive transistor Qd2. The source of the first drive transistor Qd1 is connected to the source of the second drive transistor Qd2. That is, the holding capacitor Co is connected between the gate and source of the second drive transistor Qd2. As a result, the electric charge accumulated in the holding capacitor Co is supplied equally to the first and second drive transistors Qd1 and Qd2.
[0073]
Further, the gain coefficient as the drive capability of the second drive transistor Qd2 is set according to the light emission period when the organic EL element OLED is used in the impulse display mode. For example, in the impulse display system according to the present embodiment, the light emission period of the organic EL element OLED is set to ¼ frame period, and the gain coefficient of the second drive transistor Qd2 is set to the gain coefficient of the first drive transistor Qd1. Is set to be three times as large.
[0074]
That is, the ratio of the gain coefficient of the first drive transistor Qd1 to the sum of the gain coefficients of the first drive transistor Qd1 and the second drive transistor Qd2 is one frame period and the organic EL element. It sets so that it may become the same as the ratio of the light emission period of OLED. In other words, the ratio between the gain coefficient of the first drive transistor Qd1 and the sum of the gain coefficients of the first drive transistor Qd1 and the second drive transistor Qd2 is the hold drive and the impulse. The duty ratio is set to be the same as that of the drive. By doing so, the current per frame period of the drive current Iel (see FIG. 3) passing through the start transistor Qst when using the hold type display method and the drive current Iel passing through the start transistor Qst when using the impulse type display method. The level can be the same. As a result, the luminance of the organic EL element OLED when using the hold type display method and the luminance of the organic EL element OLED when using the impulse type display method can be made the same.
[0075]
The drain of the second drive transistor Qd2 is connected to the drain of the control switching transistor Qx. The source of the control switching transistor Qx is connected to the drain of the start transistor Qst. The gate of the control switching transistor Qx is connected to the control line LDn together with the gate of the control switching transistor Qx of another pixel circuit 20 arranged along the row direction.
[0076]
The pixel circuit 20 configured as described above has the single line driver 23 via the data line Xm by simultaneously turning on the first switching transistor Qsw1 and the second switching transistor Qsw2. The generated data signal Idata is supplied to the pixel circuit 20. Then, charges corresponding to the current level of the data signal Idata can be accumulated in the holding capacitor Co. As a result, a current having a current level corresponding to the electric charge accumulated in the holding capacitor Co can flow between the source / drain of the first and second drive transistors Qd1 and Qd2. At this time, by turning on the start transistor Qst, the current flowing between the source / drain of the first drive transistor Qd1 can be supplied to the organic EL element OLED as the drive current Iel.
[0077]
Further, by turning on the control switching transistor Qx with the start transistor Qst turned on, a current flowing between the source / drain of the second driving transistor Qd2 is supplied to the organic EL element OLED. Can be supplied. That is, when the start transistor Qst is turned on and the control switching transistor Qx is turned off, the current flowing between the source / drain of the first drive transistor Qd1 is supplied to the organic EL element OLED as the drive current Iel. The When both the start transistor Qst and the control switching transistor Qx are turned on, the current flowing between the source / drain of the first drive transistor Qd1 and the second drive transistor Qd2 in the organic EL element OLED. A combined current obtained by combining the currents flowing between the source / drain of each is supplied as the drive current Iel.
[0078]
At this time, in this embodiment, as described above, the gain coefficient of the second drive transistor Qd2 is set to be three times the gain coefficient of the first drive transistor Qd1. As a result, the current level of the drive current Iel supplied to the organic EL element OLED is four times that in the case where the control switching transistor Qx is turned off. Therefore, the organic EL element OLED can emit light with four times the luminance by turning on the start transistor Qst and turning on the control switching transistor Qx.
[0079]
From the above, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image, the display control circuit 15 turns off each control switching transistor Qx. It is set to output a level control signal DSn. When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image, the display control circuit 15 controls the H level to turn on each of the control switching transistors Qx. The signal DSn is set to be output.
[0080]
In other words, when a still image is displayed by the hold-type display method, the display control circuit 15 is set to output an L level control signal DSn for turning off each of the control switching transistors Qx. When displaying a moving image by the impulse display method, the display control circuit 15 is set to output an H level control signal DS for turning on each of the control switching transistors Qx.
[0081]
By doing in this way, even if the light emission period of the organic EL element OLED in the impulse type display method is 1/4 of the light emission period of the organic EL element OLED in the hold type display method, the luminance of the organic EL element OLED Can be quadrupled. Therefore, the average luminance per frame period of the organic EL element OLED can be made equal when the impulse type display method is used and when the hold type display method is used. As a result, there is provided an organic EL display 10 that suppresses the difference in average luminance per frame period of the organic EL element OLED between the case where an image is displayed by an impulse type display method and the case where an image is displayed by a hold type display method. can do.
[0082]
Moreover, in the organic EL display 10 of the present invention, by controlling the current level of the image data D and the data signal Idata, one frame is obtained when the impulse type display method is used and when the hold type display method is used. The change in the luminance of the organic EL element OLED can be suppressed only by controlling the on / off of the control switching transistor Qx instead of equalizing the average average luminance. Therefore, it is possible to easily suppress the difference in luminance between when the impulse type display method is used and when the hold type display method is used.
[0083]
Next, a method for driving the organic EL display 10 will be described with reference to FIGS.
FIG. 4 is a timing chart for explaining a driving method of the organic EL display 10 when the hold type display method is used. FIG. 5 is a timing chart for explaining a method of driving the organic EL display 10 when the impulse display method is used.
[0084]
Hereinafter, for convenience of explanation, the driving method of the organic EL display 10 when the hold type display method is used and when the impulse type display method is used will be described separately.
[0085]
(Hold type display method)
First, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image based on the image data D, a display control signal GK to that effect is displayed from the signal generation circuit 11. It is output to the circuit 15.
[0086]
Then, the display control circuit 15 creates an L-level control signal DS based on the display control signal GK, and the created L-level control signal DS is sent to all the pixels via the control lines LD1 to LDn. Output to the circuit 20. As a result, the control switching transistors Qx of all the pixel circuits 20 are turned off.
[0087]
Then, in a state where the display control circuit 15 outputs the L level control signal DS to each pixel circuit 20, the scanning line driving circuit 13 is based on the scanning line driving signal SK output from the signal generating circuit 11. The scanning line Y1 is selected. Then, the scanning line driving circuit 13 outputs an H level scanning signal SC1 that simultaneously turns on the first and second switching transistors Qsw1 and Qsw2. As a result, the first and second switching transistors Qsw1 and Qsw2 are simultaneously turned on, and the data signal Idata is supplied to the holding capacitors Co via the data lines X1 to Xm. As a result, charges corresponding to the data signal Idata are accumulated in the holding capacitor Co. That is, data is written to each pixel circuit 20 on the selected scanning line Y1.
[0088]
At this time, the scanning line driving circuit 13 outputs an L level timing signal SY1. As a result, the start transistor Qst of each pixel circuit 20 on the scanning line Y1 is turned off. Therefore, the drive current Iel is not supplied to the organic EL element OLED, and the organic EL element OLED does not emit light yet.
[0089]
Thereafter, an L level scanning signal SC1 is supplied from the scanning line driving circuit 13. As a result, since the first and second switching transistors Qsw1 and Qsw2 are turned off, the data signal Idata is not supplied to the pixel circuit 20. Accordingly, the writing of data to the pixel circuit 20 is completed.
[0090]
Subsequently, the scanning line driving circuit 13 outputs an H level timing signal SY1. As a result, the start transistor Qst is turned on, and the organic EL element OLED and the first drive transistor Qd1 are electrically connected. As a result, the current flowing through the first drive transistor Qd1 is supplied to the organic EL element OLED as the drive current Iel, and the organic EL element OLED emits light according to the current level of the current flowing through the first drive transistor Qd1. .
[0091]
Subsequently, the scanning line driving circuit 13 selects the next scanning line Y2 based on the scanning line driving signal SK, and scans the pixel circuit 20 on the selected scanning line Y2 in the same manner as described above. The signal SC2 and the timing signal SY2 are sequentially supplied. Then, the organic EL element OLED of the pixel circuit 20 connected to the scanning line Y2 emits light according to the current level of the current flowing through the first drive transistor Qd1. Thereafter, in the same manner as described above, the scanning line driving circuit 13 sequentially selects scanning lines based on the scanning line driving signal SK, and sends a scanning signal to the pixel circuit 20 connected to the selected scanning line. And providing a timing signal. As a result, the organic EL element OLED emits light sequentially according to the current level of the current flowing through the first drive transistor Qd1. When the last scanning line Yn is selected and light is emitted based on the data signal Idata, an image for one frame is displayed on the display panel unit 12.
[0092]
Subsequently, after the end of one frame period, the scanning line driving circuit 13 selects the scanning line Y1 based on the scanning line driving signal SK, and an L level timing signal SY1 is sent from the scanning line driving circuit 13 to the signal line LS1. Is supplied to each pixel circuit 20 via the. As a result, all the start transistors Qst of the pixel circuits 20 on the scanning line Y1 are turned off, and the light emission of the organic EL elements OLED of the pixel circuits 20 on the scanning line Y1 is stopped. As a result, the light emission period of the organic EL element OLED on the scanning line Y1 ends.
[0093]
At the same time as the L-level timing signal SY1 is supplied from the scanning line driving circuit 13, the H-level scanning signal SC1 is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the scanning line Y1. . As a result, the first and second switching transistors Qsw1 and Qsw2 of the pixel circuit 20 on the scanning line Y1 are turned on, and data is written again.
[0094]
As described above, after the end of one frame period, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK, and the same operation as described above is performed to obtain an image. Is displayed.
[0095]
As described above, when displaying an image using the hold-type display method, the display control circuit 15 outputs the L level control signal DS to each pixel circuit 20. In this state, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK, and supplies the scanning signal and timing to the pixel circuit 20 connected to the selected scanning line. Output signals sequentially. Further, the data signal Idata is supplied to the pixel circuit 20 connected to the selected scanning line, and data is written. In this way, a desired image (still image) is displayed on the display panel unit 12.
[0096]
(Impulse type display method)
When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image based on the image data, a display control signal GK to that effect is sent from the signal generation circuit 11 to the display control circuit 15. Is output.
[0097]
Then, the display control circuit 15 generates an H level control signal DS based on the display control signal GK, and the generated H level control signal DS is supplied to each pixel circuit via the control lines LD1 to LDn. 20 is output. As a result, the control switching transistors Qx of all the pixel circuits 20 are turned on.
[0098]
Then, the scanning line driving circuit 13 is based on the scanning line driving signal SK output from the signal generating circuit 11 with the H level control signal DS output from the display control circuit 15 to each pixel circuit 20. First, the scanning line Y1 is selected. Then, the scanning line driving circuit 13 outputs an H level scanning signal SC1. As a result, the first and second switching transistors Qsw1 and Qsw2 are simultaneously turned on, and the data signal Idata is supplied to the respective holding capacitors Co via the data lines X1 to Xm. Accordingly, charges corresponding to the data signal Idata are stored in the holding capacitors Co, respectively. That is, data is written to each pixel circuit 20 on the scanning line Y1.
[0099]
At this time, an L level timing signal SY1 is output from the scanning line driving circuit 13. As a result, the start transistor Qst is turned off. Therefore, the drive current Iel is not supplied to the organic EL element OLED, and the organic EL element OLED does not emit light yet.
[0100]
Thereafter, the scanning line driving circuit 13 outputs an L level scanning signal SC1. As a result, the first and second switching transistors Qsw1 and Qsw2 are simultaneously turned off, and the data signal Idata is not supplied to each pixel circuit 20 on the scanning line Y1. Therefore, data writing to each pixel circuit 20 is completed.
[0101]
Subsequently, the scanning line driving circuit 13 outputs an H level timing signal SY1 for turning on the start transistor Qst. As a result, the start transistor Qst is turned on, and the organic EL element OLED and the first and second drive transistors Qd1, Qd2 are electrically connected. As a result, a combined current of the currents flowing in the first and second drive transistors Qd1 and Qd2 is supplied to the organic EL element OLED as the drive current Iel. The organic EL element OLED emits light according to the current level of the combined current of the currents flowing through the first and second drive transistors Qd1 and Qd2. At this time, the current level of the current flowing through the first driving transistor Qd1 is three times the current level of the current flowing through the second driving transistor Qd2, so that the current level is four times that when the hold type display method is used. The organic EL element OLED can emit light with a luminance of.
[0102]
Thereafter, after a ¼ frame period elapses, an L level timing signal SY1 is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the signal line LS1. As a result, the start transistor Qst of each pixel circuit 20 on the scanning line Y1 is turned off, and the light emission of the organic EL element OLED is stopped. As a result, the light emission period of the organic EL element OLED on the scanning line Y1 ends.
[0103]
The scanning line driving circuit 13 selects the next scanning line Y2 based on the scanning line driving signal SK output from the signal generation circuit 11, and each pixel circuit 20 connected to the selected scanning line Y2. Similarly, the scanning signal SC2 and the timing signal SY2 are sequentially supplied in the same manner as described above. Thereafter, after a ¼ frame period has elapsed, an L level timing signal SY2 is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the signal line LS2.
[0104]
As described above, when an image is displayed using the impulse-type display method, the display control circuit 15 outputs an H level control signal DS to each pixel circuit 20. In this state, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK output from the signal generation circuit 11, and is connected to the selected scanning line. As described above, the scanning signal and the timing signal are sequentially supplied to each pixel circuit 20. Further, the data signal Idata is supplied to the pixel circuit 20 connected to the selected scanning line. Thereafter, after a ¼ frame period has elapsed, an L level timing signal is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the signal lines LS1 to LSn. In this way, a desired image (moving image) can be displayed on the display panel unit 12.
[0105]
As described above, when the image is displayed using the hold-type display method, the control signal DS of the L level is displayed from the display control circuit 15, and when the image is displayed using the impulse-type display method, the display control is performed. An H level control signal DS is output from the circuit 15. By doing so, it is possible to suppress a difference in average luminance per frame period of the organic EL element OLED between the case where an image is displayed by an impulse type display method and the case where an image is displayed by a hold type display method. The organic EL display 10 that can be driven can be driven.
[0106]
The first transistor, the second transistor, the first switching element, and the second switching element described in the claims are, for example, the first driving transistor Qd1 and the second driving element in the present embodiment. This corresponds to the transistor Qd2, the control switching transistor Qx, and the start transistor Qst. Further, the third switching element, the fourth switching element, and the capacitor element described in the claims are, for example, the second switching transistor Qsw2, the first switching transistor Qsw1 and the holding capacitor Co in the present embodiment. Each corresponds.
[0107]
Further, the first terminal, the second terminal, and the first control terminal described in the claims are, for example, the source of the first drive transistor Qd1 and the first drive transistor Qd1 in the present embodiment. The drain corresponds to the drain and the gate of the first driving transistor Qd1. Further, the third terminal, the fourth terminal, and the second control terminal described in the claims are, for example, the source of the second drive transistor Qd2 and the second drive transistor Qd2 in the present embodiment. The drain corresponds to the drain and the gate of the second drive transistor Qd2. Further, the fifth terminal, the sixth terminal, and the third control terminal described in the claims are, for example, the drain of the control switching transistor Qx, the source of the control switching transistor Qx, and the like in the present embodiment. Each corresponds to the gate of the control switching transistor Qx. The seventh terminal, the eighth terminal, and the fourth control terminal described in the claims are, for example, the drain of the start transistor Qst, the source of the start transistor Qst, and the start transistor Qst in the present embodiment. Each corresponds to a gate.
[0108]
The ninth terminal, the tenth terminal, and the fifth control terminal described in the claims are, for example, the drain of the second switching transistor Qsw2 and the second switching transistor Qsw2 in the present embodiment. This corresponds to the source and the gate of the second switching transistor Qsw2. The eleventh terminal, the twelfth terminal, and the sixth control terminal described in the claims are, for example, the drain of the first switching transistor Qsw1 and the first switching transistor Qsw1 in the present embodiment. It corresponds to the source and the gate of the first switching transistor Qsw1, respectively. The electronic circuit or unit circuit described in the claims corresponds to, for example, the pixel circuit in the present embodiment. Furthermore, the electronic element or the current driving element and the electro-optical element described in the claims correspond to, for example, the organic EL element OLED in the present embodiment.
[0109]
According to the pixel circuit and the organic EL display of the embodiment, the following characteristics can be obtained.
(1) In the embodiment, the first and second drive transistors Qd1, Qd2, the first and second switching transistors Qsw1, Qsw2, the start transistor Qst, the control switching transistor Qx, the holding capacitor Co, and the organic EL element OLED The pixel circuit 20 was configured as described above. A second drive transistor Qd2 is connected in parallel to the first drive transistor Qd1. The second drive transistor Qd2 and the start transistor Qst are connected via a control switching transistor Qx. The gate of the control switching transistor Qx was connected to the display control circuit 15 via control lines LD1 to LDn.
[0110]
When an image is displayed by the impulse display method, the display control circuit 15 is set to output a control signal DS for turning on the control switching transistor Qx. Further, when displaying an image by the hold type display method, the display control circuit 15 is set to output a control signal DS for turning off the control switching transistor Qx. Thus, when displaying an image by the impulse display method, the organic EL element OLED has a current flowing between the source / drain of the first drive transistor Qd1 and the source / drain of the second drive transistor Qd2. A combined current obtained by combining the current flowing between the drains is supplied as the drive current Iel. That is, the current level of the drive current Iel when displaying an image by the impulse display method is set larger than that when displaying an image by the hold display method. Accordingly, it is possible to suppress a difference in luminance of the organic EL element OLED between the case where an image is displayed by the impulse type display method and the case where an image is displayed by the hold type display method. As a result, the display quality of the organic EL display 10 can be provided.
[0111]
(2) In the embodiment, the gain coefficient of the second drive transistor Qd2 is set to be three times the gain coefficient of the first drive transistor Qd1. By doing in this way, even if a light emission period is a 1/4 frame period, the organic EL display without the change of the average luminance of the organic EL element OLED per frame period can be provided.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. In this 2nd Embodiment, the code | symbol is made equal about the same structural member as the said 1st Embodiment, and the detailed description is abbreviate | omitted.
[0112]
FIG. 6 is a circuit diagram of the pixel circuit 30 arranged in the display panel unit 12 of the organic EL display 10.
In the organic EL display 10 according to the present embodiment, the data signal Vdata is a voltage signal compared to the current signal in the first embodiment. Therefore, each single line driver 23 in the present embodiment generates a data signal Vdata consisting of a voltage signal based on the data line drive signal DK, and the generated data signal Vdata is transmitted via the data lines X1 to Xm. To the corresponding pixel circuit 20 respectively.
[0113]
Since the circuit configuration of each pixel circuit 30 is the same, only the pixel circuit 30 arranged at a position corresponding to the intersection of the nth scanning line Yn and the mth data line Xm is described for convenience of explanation. explain.
[0114]
As shown in FIG. 6, the pixel circuit 30 includes first and second drive transistors Qd1 and Qd2, a switching transistor Qsw, a start transistor Qst, and a control switching transistor Qx. The pixel circuit 30 includes a holding capacitor Co and an organic EL element OLED.
[0115]
The first and second drive transistors Qd1 and Qd2 are transistors that function as current sources for supplying current, respectively. The switching transistor Qsw, the start transistor Qst, and the control switching transistor Qx are transistors that function as switching elements, respectively.
[0116]
The conductivity types of the first and second drive transistors Qd1 and Qd2 are each a p-type in this embodiment. In addition, the conductive types of the switching transistor Qsw, the start transistor Qst, and the control switching transistor Qx are n-type in this embodiment.
[0117]
More specifically, the drain of the first drive transistor Qd1 is connected to the drain of the start transistor Qst. The source of the start transistor Qst is connected to the anode of the organic EL element OLED, and the cathode of the organic EL element OLED is grounded. The gate of the start transistor Qst is connected to the signal line LSn together with the gates of the start transistors Qst of other pixel circuits 30 arranged in the row direction. That is, the start transistor Qst is ON / OFF controlled in accordance with the timing signal SYn output from the scanning line driving circuit 13 via the signal line LSn.
[0118]
The gate of the first driving transistor Qd1 is connected to the first connection terminal E1 of the holding capacitor Co, and the second connection terminal E2 of the holding capacitor Co is connected to the source of the first driving transistor Qd1. . The source of the first driving transistor Qd1 is connected to the power supply line VL so that the driving voltage Voel is supplied. The holding capacitor Co is connected to the data line Xm via a switching transistor Qsw. The gate of the switching transistor Qsw is connected to the scanning line Yn. Accordingly, the switching transistor Qsw is simultaneously turned on / off according to the scanning signal SCn output from the scanning line driving circuit 13 through the scanning line Yn.
[0119]
Further, a second drive transistor Qd2 is connected to the first drive transistor Qd1 in parallel with the first drive transistor Qd1. Specifically, the gate of the first drive transistor Qd1 is connected to the gate of the second drive transistor Qd2. The source of the first drive transistor Qd1 is connected to the source of the second drive transistor Qd2. That is, the holding capacitor Co is connected between the gate and source of the second drive transistor Qd2. As a result, the electric charge accumulated in the holding capacitor Co is supplied equally to the first and second drive transistors Qd1 and Qd2. In this embodiment, the gain coefficient of the second drive transistor Qd2 is set to be equal to the gain coefficient of the first drive transistor Qd1.
[0120]
The drain of the second drive transistor Qd2 is connected to the drain of the control switching transistor Qx. The source of the control switching transistor Qx is connected to the drain of the start transistor Qst. The gate of the control switching transistor Qx is connected to the control line LDn together with the gate of the control switching transistor Qx of another pixel circuit 20 arranged along the row direction.
[0121]
The pixel circuit 30 configured in this manner turns on the switching transistor Qsw, thereby allowing the data signal Vdata generated by the single line driver 23 to be transmitted to the pixel circuit 30 via the data line Xm. Supply. Then, charges corresponding to the voltage level of the data signal Vdata can be accumulated in the holding capacitor Co. In addition, a current having a current level corresponding to the charge accumulated in the holding capacitor Co can flow between the source / drain of the first and second drive transistors Qd1 and Qd2. At this time, by turning on the start transistor Qst, the current flowing between the source and drain of the first drive transistor Qd1 can be supplied to the organic EL element OLED as the drive current Iel.
[0122]
Further, by turning on the control switching transistor Qx with the start transistor Qst turned on, a current flowing between the source / drain of the second driving transistor Qd2 is supplied to the organic EL element OLED. Can be supplied. That is, when the start transistor Qst is turned on and the control switching transistor Qx is turned off, the current flowing between the source / drain of the first drive transistor Qd1 is supplied to the organic EL element OLED as the drive current Iel. The When both the start transistor Qst and the control switching transistor Qx are turned on, the current flowing between the source / drain of the first drive transistor Qd1 and the second drive transistor Qd2 in the organic EL element OLED. A combined current obtained by combining the currents flowing between the source / drain of each is supplied as the drive current Iel.
[0123]
In the present embodiment, as described above, since the gain coefficient of the second drive transistor Qd2 is set to be three times the gain coefficient of the first drive transistor Qd1, the organic EL element OLED The current level of the drive current Iel supplied to is quadrupled compared to when the control switching transistor Qx is turned off. As a result, when the control switching transistor Qx is turned on, the organic EL element OLED can emit light with four times the luminance as compared with the case where the control switching transistor Qx is turned off.
[0124]
From the above, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image, the display control circuit 15 turns off each of the control switching transistors Qx. It is set to output an L level control signal DS. Further, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image, the display control circuit 15 sets the control switching transistor Qx to the ON state. The control signal DS is set to be output.
[0125]
In other words, when a still image is displayed by the hold type display method, the display control circuit 15 is set to output an L level control signal DSn for turning off each of the control switching transistors Qx. When displaying a moving image by the impulse type display method, the display control circuit 15 is set to output an H level control signal DS for turning on each of the control switching transistors Qx.
[0126]
Also in the organic EL display 10 of the pixel circuit 30 configured as described above, when a still image is displayed by the hold type display method described in the first embodiment, the scanning line driving circuit is performed at the timing shown in FIG. 13. By outputting each signal from the data line driving circuit 14 and the display control circuit 15, a hold-type display method can be performed as in the first embodiment. Further, when displaying a moving image by the impulse display method, each signal is output from the scanning line driving circuit 13, the data line driving circuit 14, and the display control circuit 15 at the timing shown in FIG. As in the first embodiment, an impulse type display method can be performed.
[0127]
Accordingly, in the present embodiment as well, as in the first embodiment, when the hold type display method is used to represent an image, the L level control signal DS is used from the display control circuit 15 and the impulse type display method is used. When displaying an image, the display control circuit 15 outputs an H level control signal DSn. By doing so, it is possible to suppress a difference in average luminance per frame period of the organic EL element OLED between the case where an image is displayed by an impulse type display method and the case where an image is displayed by a hold type display method. The organic EL display 10 that can be driven can be driven.
[0128]
The fifth switching element, the thirteenth terminal, the fourteenth terminal and the seventh control terminal described in the claims are, for example, the switching transistor Qsw, the drain of the switching transistor Qsw in this embodiment, This corresponds to the source of the switching transistor Qsw and the gate of the switching transistor Qsw.
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0129]
FIG. 7 is a circuit diagram of a pixel circuit arranged in the display panel unit 12 of the organic EL display 10 in the present embodiment. FIG. 8 is a timing chart for explaining a method of driving the organic EL display 10 in the present embodiment when the hold type display method is used. FIG. 9 is a timing chart for explaining a driving method of the organic EL display 10 in the present embodiment when the impulse type display method is used.
[0130]
In the organic EL display 10 in the present embodiment, the data signal Idata is the same current signal as in the first embodiment. Therefore, each single line driver 23 in the present embodiment generates a data signal Idata based on the data line drive signal DK, and the generated pixel signal 20 corresponds to the generated data signal Idata via the data line Xm. Respectively.
[0131]
Since the circuit configuration of each pixel circuit 40 is the same, only the pixel circuit 40 arranged at the position corresponding to the intersection of the nth scanning line Yn and the mth data line Xm is described for convenience of explanation. explain. Further, the scanning lines Y1 to Yn in the present embodiment are composed of first sub-scanning lines Y11 to Yn1 and second sub-scanning lines Y12 to Yn2. The first scanning signals SC11 to SCn1 are supplied to the first sub-scanning lines Y11 to Yn1, and the second scanning signals SC12 to SCn2 are supplied to the second sub-scanning lines Y12 to Yn2, respectively. It comes to be supplied.
[0132]
As shown in FIG. 7, the pixel circuit 40 includes first and second drive transistors Qd1, Qd2, third and fourth switching transistors Qsw3, Qsw4, a start transistor Qst, a control switching transistor Qx, and a conversion transistor Qc. I have. The pixel circuit 40 includes a holding capacitor Co and an organic EL element OLED.
[0133]
The first and second drive transistors Qd1 and Qd2 and the conversion transistor Qc are transistors that function as current sources for supplying current, respectively. The third and fourth switching transistors Qsw3 and Qsw4, the start transistor Qst, and the control switching transistor Qx are transistors that function as switching elements, respectively.
[0134]
In the present embodiment, the conductivity types of the first and second drive transistors Qd1, Qd2 and the conversion transistor Qc are each p-type. The conductivity types of the third and fourth switching transistors Qsw3 and Qsw4, the start transistor Qst, and the control switching transistor Qx are each n-type in this embodiment.
[0135]
More specifically, the drain of the first drive transistor Qd1 is connected to the drain of the start transistor Qst. The source of the start transistor Qst is connected to the anode of the organic EL element OLED, and the cathode of the organic EL element OLED is grounded. The gate of the start transistor Qst is connected to the signal line LSn together with the gates of the start transistors Qst of other pixel circuits 40 arranged in the row direction. That is, the start transistor Qst is ON / OFF controlled in accordance with the timing signal SYn output from the scanning line driving circuit 13 via the signal line LSn.
[0136]
The gate of the first drive transistor Qd1 is connected to the gate of the conversion transistor Qc. The source of the first drive transistor Qd1 is connected to the source of the conversion transistor Qc. That is, the first drive transistor Qd1 and the conversion transistor Qc constitute a current mirror circuit. Further, the first connection terminal E1 of the holding capacitor Co is connected to the gate of the conversion transistor Qc, and the source of the conversion transistor Qc is connected to the second connection terminal E2 of the holding capacitor Co.
[0137]
The drain of the conversion transistor Qc is connected to the drain of the third switching transistor Qsw3. The source of the third switching transistor Qsw3 is connected to the data line Xm. The gate of the third switching transistor Qsw3 is connected to the first sub-scanning line Yn1. Accordingly, the third switching transistor Qsw3 is ON / OFF controlled in accordance with the first scanning signal SCn1 output from the scanning line driving circuit 13 through the first sub-scanning line Yn1.
[0138]
Further, a fourth switching transistor Qsw4 is connected between the drain / gate of the conversion transistor Qc. The gate of the fourth switching transistor Qsw4 is connected to the second sub-scanning line Yn2. Accordingly, the fourth switching transistor Qsw4 is on / off controlled in accordance with the second scanning signal SCn2 output from the scanning line driving circuit 13 via the second sub-scanning line Yn2.
[0139]
Each source of the first drive transistor Qd1 and the conversion transistor Qc is connected to the power supply line VL so that the drive voltage Voel is supplied.
[0140]
Further, a second drive transistor Qd2 is connected to the first drive transistor Qd1 in parallel with the first drive transistor Qd1. Specifically, the gate of the first drive transistor Qd1 is connected to the gate of the second drive transistor Qd2. The source of the first drive transistor Qd1 is connected to the source of the second drive transistor Qd2. That is, the second drive transistor Qd2 forms a current mirror circuit with the conversion transistor Qc.
[0141]
In this embodiment, the gain coefficient of the second drive transistor Qd2 is set to be equal to the gain coefficient of the first drive transistor Qd1.
[0142]
The drain of the second drive transistor Qd2 is connected to the drain of the control switching transistor Qx. The source of the control switching transistor Qx is connected to the drain of the start transistor Qst. The gate of the control switching transistor Qx is connected to the control line LDn together with the gate of the control switching transistor Qx of another pixel circuit 40 arranged along the row direction.
[0143]
In the pixel circuit 40 configured as described above, the single switching driver Qsw3 and the fourth switching transistor Qsw4 are simultaneously turned on by the single line driver 23 via the data line Xm. The generated data signal Idata is supplied to the pixel circuit 20. Then, charges corresponding to the current level of the data signal Idata can be accumulated in the holding capacitor Co. Therefore, a current having a current level corresponding to the charge accumulated in the holding capacitor Co flows between the source / drain of the conversion transistor Qc and the first driving transistor Qd1.
[0144]
At this time, by turning on the start transistor Qst, the current flowing between the source and drain of the first drive transistor Qd1 can be supplied to the organic EL element OLED as the drive current Iel.
[0145]
In addition, a current having a current level corresponding to the charge accumulated in the storage capacitor Co can flow between the source / drain of the second drive transistor Qd2. Accordingly, by turning on the control switching transistor Qx with the start transistor Qst turned on, a current flowing between the source / drain of the second drive transistor Qd2 is supplied to the organic EL element OLED. Can be supplied. That is, when the start transistor Qst is turned on and the control switching transistor Qx is turned off, the current flowing between the source / drain of the first drive transistor Qd1 is supplied to the organic EL element OLED as the drive current Iel. The When both the start transistor Qst and the control switching transistor Qx are turned on, the current flowing between the source / drain of the first drive transistor Qd1 and the second drive transistor Qd2 in the organic EL element OLED. A combined current obtained by combining the currents flowing between the source / drain of each is supplied as the drive current Iel.
[0146]
In the present embodiment, as described above, the gain coefficient of the second drive transistor Qd2 is set to be three times the gain coefficient of the first drive transistor Qd1, so that it is supplied to the organic EL element OLED. The current level of the drive current Iel is four times that in the case where the control switching transistor Qx is turned off. As a result, when the control switching transistor Qx is turned on, the organic EL element OLED can emit light with four times the luminance as compared with the case where the control switching transistor Qx is turned off.
[0147]
From the above, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image, the display control circuit 15 turns off each of the control switching transistors Qx. It is set to output an L level control signal DS. When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image, the display control circuit 15 sets the control switching transistor Qx to the on state. The control signal DS is set to be output.
[0148]
That is, when a still image is displayed by the hold-type display method, the display control circuit 15 is set to output an L level control signal DS for turning off each of the control switching transistors Qx. When displaying a moving image by the impulse type display method, the display control circuit 15 is set to output an H level control signal DS for turning on each of the control switching transistors Qx.
[0149]
Next, a method for driving the organic EL display 10 will be described with reference to FIGS.
FIG. 8 is a timing chart for explaining a method of driving the organic EL display 10 in the present embodiment when the hold type display method is used. FIG. 9 is a timing chart for explaining a driving method of the organic EL display 10 in the present embodiment when the impulse type display method is used.
[0150]
Hereinafter, for convenience of explanation, the driving method of the organic EL display 10 when the hold type display method is used and when the impulse type display method is used will be described separately.
[0151]
(Hold type display method)
First, when the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a still image based on the image data D, a display control signal GK to that effect is displayed from the signal generation circuit 11. It is output to the circuit 15.
[0152]
Then, the display control circuit 15 creates an L level control signal DS based on the display control signal GK, and the created L level control signal DS is sent to all the pixel circuits 40 via the control line LDn. Output to. As a result, the control switching transistors Qx of all the pixel circuits 40 are turned off.
[0153]
Then, in a state where the display control circuit 15 outputs an L level control signal DS to each pixel circuit 40, the scanning line driving circuit 13 is based on the scanning line driving signal SK output from the signal generating circuit 11. The scanning line Y1 is selected. Then, the scanning line driving circuit 13 outputs an H level scanning signal SC11 for turning on the third switching transistor Qsw3 via the first sub scanning line Y11 constituting the scanning line Y1. At the same time, the scanning line drive circuit 13 outputs an H level scanning signal SC12 for turning on the fourth switching transistor Qsw4 via the second sub scanning line Y12 constituting the scanning line Y1. As a result, the third and fourth switching transistors Qsw3 and Qsw4 are simultaneously turned on, and the data signal Idata is supplied to the holding capacitors Co through the data lines X1 to Xm. As a result, charges corresponding to the data signal Idata are accumulated in the holding capacitor Co. That is, data is written to each pixel circuit 40 on the selected scanning line Y1.
[0154]
At this time, the scanning line driving circuit 13 outputs an L level timing signal SY1. As a result, the start transistor Qst of each pixel circuit 40 on the scanning line Y1 is turned off. Therefore, the drive current Iel is not supplied to the organic EL element OLED, and the organic EL element OLED does not emit light yet.
[0155]
Thereafter, an L level scanning signal SC11 for turning on the third switching transistor Qsw3 is output from the scanning line driving circuit 13 via the first sub-scanning line Y11. Further, the scanning line driving circuit 13 outputs an L level scanning signal SC12 for turning on the fourth switching transistor Qsw4 via the second sub scanning line Y12. As a result, since the third and fourth switching transistors Qsw3 and Qsw4 are turned off, the data signal Idata is not supplied to the pixel circuit 40. Accordingly, the writing of data to the pixel circuit 40 is completed.
[0156]
Subsequently, the scanning line driving circuit 13 outputs an H level timing signal SY1. As a result, the start transistor Qst is turned on, and the organic EL element OLED and the first drive transistor Qd1 are electrically connected. As a result, the current flowing through the first drive transistor Qd1 is supplied to the organic EL element OLED as the drive current Iel, and the organic EL element OLED emits light according to the current level of the current flowing through the first drive transistor Qd1. .
[0157]
Subsequently, the scanning line driving circuit 13 selects the next scanning line Y2 based on the scanning line driving signal SK, and scans the pixel circuit 40 on the selected scanning line Y2 in the same manner as described above. Signals SC21 and SC22 and timing signal SY2 are sequentially supplied. Then, the organic EL element OLED of the pixel circuit 40 connected to the scanning line Y2 emits light according to the current level of the current flowing through the first drive transistor Qd1. Thereafter, in the same manner as described above, the scanning line driving circuit 13 sequentially selects scanning lines based on the scanning line driving signal SK, and sends scanning signals to the pixel circuits 40 connected to the selected scanning lines. And providing a timing signal. As a result, the organic EL element OLED emits light sequentially according to the current level of the current flowing through the first drive transistor Qd1. When the last scanning line Yn is selected and light is emitted based on the data signal Idata, an image for one frame is displayed on the display panel unit 12.
[0158]
Subsequently, after the end of one frame period, the scanning line driving circuit 13 selects the scanning line Y1 based on the scanning line driving signal SK, and an L level timing signal SY1 is sent from the scanning line driving circuit 13 to the signal line LS1. Is supplied to each pixel circuit 20 via the. As a result, all the start transistors Qst of the pixel circuits 20 on the scanning line Y1 are turned off, and the light emission of the organic EL elements OLED of the pixel circuits 20 on the scanning line Y1 is stopped. As a result, the light emission period of the organic EL element OLED on the scanning line Y1 ends.
[0159]
At the same time as the L-level timing signal SY1 is supplied from the scanning line driving circuit 13, the H-level first and second scanning signals SC1 and SC2 are respectively supplied from the scanning line driving circuit 13 to the first and second scanning signals. Are supplied to each pixel circuit 20 via the sub-scanning lines Y11 and Y12. As a result, the third and fourth switching transistors Qsw3 and Qsw4 of the pixel circuit 20 on the scanning line Y1 are turned on, and data is written again.
[0160]
As described above, after the end of one frame period, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK, and the same operation as described above is performed to obtain an image. Is displayed.
[0161]
As described above, when displaying an image using the hold-type display method, the display control circuit 15 outputs the L level control signal DS to each pixel circuit 20. In this state, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK, and supplies the scanning signal and timing to the pixel circuit 40 connected to the selected scanning line. Output signals sequentially. Further, the data signal Idata is supplied to the pixel circuit 40 connected to the selected scanning line, and data is written. In this way, a desired image (still image) is displayed on the display panel unit 12.
[0162]
(Impulse type display method)
When the signal generation circuit 11 determines that the image displayed on the display panel unit 12 is a moving image based on the image data, a display control signal GK to that effect is sent from the signal generation circuit 11 to the display control circuit 15. Is output.
[0163]
Then, the display control circuit 15 generates an H level control signal DS based on the display control signal GK, and the generated H level control signal DS is supplied to each pixel circuit via the control lines LD1 to LDn. Output to 40. As a result, the control switching transistors Qx of all the pixel circuits 40 are turned on.
[0164]
Then, the scanning line driving circuit 13 is based on the scanning line driving signal SK output from the signal generating circuit 11 in a state where the display control circuit 15 outputs the control signal DS of H level to each pixel circuit 40. First, the scanning line Y1 is selected. Then, the scanning line drive circuit 13 outputs an H level scanning signal SC11 via the first sub scanning line Y11 constituting the scanning line Y1. At the same time, the scanning line driving circuit 13 outputs an H level scanning signal SC12 via the second sub scanning line Y12 constituting the scanning line Y1. As a result, the third switching transistor Qsw3 and the fourth switching transistor Qsw4 are simultaneously turned on, and the data signal Idata is supplied to each holding capacitor Co via the data lines X1 to Xm. Accordingly, charges corresponding to the data signal Idata are stored in the holding capacitors Co, respectively. That is, data is written to each pixel circuit 20 on the scanning line Y1.
[0165]
At this time, an L level timing signal SY1 is output from the scanning line driving circuit 13. As a result, the start transistor Qst is turned off. Therefore, the drive current Iel is not supplied to the organic EL element OLED, and the organic EL element OLED does not emit light yet.
[0166]
Thereafter, an L level scanning signal SC11 is output from the scanning line driving circuit 13 via the first sub-scanning line Y11. Further, an L level scanning signal SC12 is output through the second sub-scanning line Y12. As a result, the third and fourth switching transistors Qsw3 and Qsw4 are turned off, and the data signal Idata is not supplied to each pixel circuit 20 on the scanning line Y1. Therefore, data writing to each pixel circuit 20 is completed.
[0167]
Subsequently, the scanning line driving circuit 13 outputs an H level timing signal SY1 for turning on the start transistor Qst. As a result, the start transistor Qst is turned on, and the organic EL element OLED and the first and second drive transistors Qd1, Qd2 are electrically connected. As a result, a combined current of the currents flowing in the first and second drive transistors Qd1 and Qd2 is supplied to the organic EL element OLED as the drive current Iel. The organic EL element OLED emits light according to the current level of the combined current of the currents flowing through the first and second drive transistors Qd1 and Qd2. At this time, since the current level of the current flowing through the first drive transistor Qd1 is three times the current level of the current flowing through the second drive transistor Qd2, compared with the case where the hold type display method is used. The organic EL element OLED can emit light with four times the luminance.
[0168]
Thereafter, after a ¼ frame period elapses, an L level timing signal SY1 is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the signal line LS1. As a result, the start transistor Qst of each pixel circuit 20 on the scanning line Y1 is turned off, and the organic EL element OLED is turned off.
[0169]
Subsequently, the scanning line driving circuit 13 selects the next scanning line Y2 based on the scanning line driving signal SK output from the signal generation circuit 11. Then, each pixel circuit 40 connected to the selected scanning line Y2 is connected to the selected scanning line Y2 via the first sub-scanning line Y21 and the second sub-scanning line Y22 constituting the scanning line Y2, as described above. Scan signals SC12 and SC22 and timing signal SY2 are sequentially supplied. Thereafter, after a ¼ frame period elapses, an L level timing signal SY1 is supplied from the scanning line driving circuit 13 to each pixel circuit 20 via the signal line LS1.
[0170]
As described above, when an image is displayed using the impulse display method, the display control circuit 15 outputs an H level control signal DS to each pixel circuit 40. In this state, the scanning line driving circuit 13 sequentially selects the scanning lines Y1 to Yn based on the scanning line driving signal SK output from the signal generation circuit 11, and is connected to the selected scanning line. As described above, the scanning signal and the timing signal are sequentially supplied to each pixel circuit 40. Further, the data signal Idata is supplied to the pixel circuit 40 connected to the selected scanning line. Thereafter, after a ¼ frame period has elapsed, an L level timing signal is supplied from the scanning line driving circuit 13 to the pixel circuits 40 via the signal lines LS1 to LSn. In this way, a desired image (moving image) can be displayed on the display panel unit 12.
[0171]
By doing so, it is possible to suppress a difference in average luminance per frame period of the organic EL element OLED between the case where an image is displayed by an impulse type display method and the case where an image is displayed by a hold type display method. The organic EL display 10 that can be driven can be driven.
[0172]
The third transistor, the fifteenth terminal, the sixteenth terminal, and the eighth control terminal described in the claims are, for example, the conversion transistor Qc, the source of the conversion transistor Qc, and the conversion in this embodiment. This corresponds to the drain of the transistor Qc and the gate of the conversion transistor Qc, respectively. The sixth switching element, the seventeenth terminal, the eighteenth terminal, and the ninth control terminal described in the claims are, for example, the fourth switching transistor Qsw4, the fourth switching terminal in the present embodiment, and the like. This corresponds to the drain of the switching transistor Qsw4, the source of the fourth switching transistor Qsw4, and the gate of the fourth switching transistor Qsw4. Further, the seventh switching element, the nineteenth terminal, the twentieth terminal, and the tenth control terminal described in the claims are, for example, the third switching transistor Qsw3, the third switching terminal in the present embodiment, and the like. This corresponds to the drain of the switching transistor Qsw3, the source of the third switching transistor Qsw3, and the gate of the third switching transistor Qsw3.
(Fourth embodiment)
Next, application of the electronic apparatus of the organic EL display 10 as the electro-optical device described in the first to third embodiments will be described with reference to FIG. The organic EL display 10 can be applied to various electronic devices such as a mobile personal computer, a mobile phone, a digital camera, and a digital broadcast television.
[0173]
FIG. 10 is a perspective view showing the configuration of the mobile personal computer. In FIG. 10, the personal computer 50 includes a main body 52 having a keyboard 51 and a display unit 53 using the organic EL display 10. Even in this case, the display unit 53 using the organic EL display 10 exhibits the same effect as the first to third embodiments. As a result, the mobile personal computer 50 including the organic EL display 10 with excellent display quality can be provided.
[0174]
In addition, embodiment of invention is not limited to the said embodiment, You may implement as follows.
In the first to third embodiments, each of the first and second drive transistors Qd1 and Qd2 having the same gain coefficient is provided in each pixel circuit 20. A plurality of first and second driving transistors Qd1 and Qd2 having the same gain coefficient are provided, and some of the plurality of first and second driving transistors Qd1 and Qd2 are appropriately selected and used. You may make it do. In this way, one frame of the organic EL element OLED for displaying an image by the impulse display method on the organic EL display 10 having the power save mode and displaying an image by the hold display method. A difference in average luminance per period can be suppressed.
[0175]
In the first to third embodiments, when an image is displayed by the impulse display method, the timing signal output from the scanning line drive circuit 13 in a state where the H level control signal DS is output from the display control circuit 15. The light emission period of the organic EL element OLED is controlled by SYn. Alternatively, the control signal DS may be synchronized with the timing signal SYn output from the scanning line driving circuit 13. That is, when the timing signal SYn is at the H level, the display control circuit 15 outputs the H level control signal DS, and when the timing signal SYn is at the L level, the display control circuit 15 outputs the L level control signal DS. To do. By doing in this way, the effect similar to the said 1st-3rd embodiment can be acquired.
[0176]
In the first to third embodiments, the organic EL display 10 is provided with the pixel circuits 20, 30, and 40 of the organic EL element OLED having one color. You may apply to the EL display which provided the pixel circuit 20,30,40 for each color with respect to EL element OLED.
[0177]
In the first to third embodiments, the pixel circuit 20 is embodied and a suitable effect is obtained. However, other than the organic EL element OLED, a current driving element such as a light emitting element such as LED or FED is driven. It may be embodied in an electronic circuit. The present invention may be embodied in a storage device such as a RAM (particularly MRAM).
[0178]
In the first to third embodiments, the organic EL element OLED is embodied as the current driving element, but may be embodied as an inorganic EL element. That is, you may apply to the inorganic EL display which consists of an inorganic EL element.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an electrical configuration of an organic EL display.
FIG. 2 is a block circuit diagram showing an electrical configuration of a display panel unit and a data line driving circuit.
FIG. 3 is a circuit diagram of a pixel circuit according to the first embodiment.
FIG. 4 is a timing chart for explaining a method of driving an organic EL display when a hold type display method is used.
FIG. 5 is a timing chart for explaining a method of driving an organic EL display when an impulse type display method is used.
FIG. 6 is a circuit diagram of a pixel circuit according to a second embodiment.
FIG. 7 is a circuit diagram of a pixel circuit in a third embodiment.
FIG. 8 is a timing chart for explaining a method of driving an organic EL display according to a third embodiment.
FIG. 9 is a timing chart for explaining a method of driving an organic EL display according to a third embodiment.
FIG. 10 is a perspective view showing a configuration of a mobile personal computer for explaining a fourth embodiment.
[Explanation of symbols]
Qd1: a first driving transistor as a first transistor, Qst: a start transistor Qst as a second switching element, Qsw1: a first switching transistor as a fourth transistor, Qsw2: a first transistor as a third transistor 2 switching transistors, Qd2... Second driving transistor as the second transistor, Qx... Control switching transistor as the first switching element, Qsw... Switching transistor as the fifth switching element, Qc. Conversion transistor as a transistor, Qsw3... Third switching transistor as a seventh switching element, Qsw4... Fourth switching transistor as a sixth switching element, Co. Pashita, E1 ... first connecting terminal, E2 ... second connecting terminal, 20 ... pixel circuit as an electronic circuit or unit circuits, OLED ... electronic element or the current driving device and an organic EL element as an electro-optical element.

Claims (21)

An electronic element, and a first transistor and a second transistor that are electrically connectable to the electronic element, and the electronic element is connected to the electronic element via at least one of the first transistor and the second transistor. A method of driving an electronic circuit for supplying current ,
A first method of supplying a first current to the electronic device, passing through the first transistor and not passing through the second transistor, and via the first transistor and the second transistor; And a second method of supplying a second current to the electronic element can be switched,
The period of supplying the second current in the second method is shorter than the period of supplying the first current in the first method.
The gain coefficient of the first transistor and the first current are set so that a current per frame period of the first current for a predetermined data signal is equal to a current per frame period of the second current for the data signal. A method for driving an electronic circuit, wherein a ratio with a gain coefficient of a transistor of 2 is set . The method of driving an electronic circuit according to claim 1,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A ninth terminal, a tenth terminal, and a fifth control terminal are provided, the ninth terminal is connected to the first control terminal, and the tenth terminal is the second terminal. A third switching element connected to
An eleventh terminal, a twelfth terminal, and a sixth control terminal are provided, the eleventh terminal is connected to the second terminal, and the twelfth terminal is connected to one data line. And a fourth switching element. A method for driving an electronic circuit, comprising: The method of driving an electronic circuit according to claim 1,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A thirteenth terminal, a fourteenth terminal, and a seventh control terminal, wherein the thirteenth terminal is connected to the first connection terminal, and the fourteenth terminal is connected to one data line. 5. A driving method of an electronic circuit, comprising: 5 switching elements. The method of driving an electronic circuit according to claim 1,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A fifteenth terminal, a sixteenth terminal, and an eighth control terminal; the fifteenth terminal is connected to the first terminal; and the eighth control terminal is the first control terminal. A third transistor connected to
A sixth switching element comprising a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, wherein the seventeenth terminal is connected to the first connection terminal;
19 and a terminal and twentieth terminal of the tenth control terminal of the second 18 terminal and said sixteenth terminal is connected to the terminal of the first 19 of the first 20 one terminal of the first An electronic circuit driving method comprising: a seventh switching element connected to one data line. A capacitive element that accumulates electric charge in accordance with a data signal supplied via the data line;
A first transistor whose conduction state is set according to the charge accumulated in the capacitor;
A second transistor whose conduction state is set according to the electric charge stored in the capacitor;
A first switching element that is connected to the second transistor and is turned on to pass a first current of a level corresponding to a conduction state of the second transistor;
The second transistor is connected to the first transistor and the first switching element. When the first switching element is turned on, the second current at a level corresponding to the conduction state of the first transistor together with the first current. A second switching element that passes the current of
The driving capability of the first transistor is A, the sum of the driving capability of the first transistor and the driving capability of the second transistor is B, and both the first switching element and the second switching element are on. Is set to C, and the period during which the first switching element is turned off and the second switching element is turned on is D, the first switching element is set to satisfy the relationship of A: B = C: D. An electronic circuit characterized in that a driving capability of one transistor and a driving capability of the second transistor are set. The electronic circuit according to claim 5 ,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A ninth terminal, a tenth terminal, and a fifth control terminal are provided, the ninth terminal is connected to the first control terminal, and the tenth terminal is the second terminal. A third switching element connected to
An eleventh terminal, a twelfth terminal, and a sixth control terminal; the eleventh terminal is connected to the second terminal; and the twelfth terminal is connected to one data line. And a fourth switching element. The electronic circuit according to claim 5 ,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A thirteenth terminal, a fourteenth terminal, and a seventh control terminal, wherein the thirteenth terminal is connected to the first connection terminal, and the fourteenth terminal is connected to one data line. 5. An electronic circuit comprising 5 switching elements. The electronic circuit according to claim 5 ,
The electronic circuit is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A fifteenth terminal, a sixteenth terminal, and an eighth control terminal; the fifteenth terminal is connected to the first terminal; and the eighth control terminal is the first control terminal. A third transistor connected to
A sixth switching element comprising a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, wherein the seventeenth terminal is connected to the first connection terminal;
A nineteenth terminal, a twentieth terminal, and a tenth control terminal, wherein the eighteenth terminal and the sixteenth terminal are connected to the nineteenth terminal, and the twentieth terminal is one data An electronic circuit comprising: a seventh switching element connected to the line. The electronic circuit according to any one of claims 6 to 8 ,
An electronic circuit, wherein an electronic element or a current driving element is connected to the eighth terminal. A driving method for an electro-optical device, comprising: a plurality of scanning lines; a plurality of data lines; and a plurality of unit circuits having electro-optical elements arranged corresponding to intersections of the scanning lines and the data lines. And
Each of the plurality of unit circuits further includes a first transistor and a second transistor whose conduction state is set according to the charge accumulated in the capacitor element,
Accumulating charges according to image data supplied via the data lines to the capacitive elements of the unit circuits connected to the selected scanning line among the plurality of scanning lines;
It is determined whether the image data is data for displaying a moving image or data for displaying a still image, and when it is determined that the image data is a still image display, the electro-optic element and the A current corresponding to the electric charge accumulated in the capacitive element is supplied to the electro-optic element in a predetermined period with the second transistor electrically disconnected, or the image data is determined to be a moving image display. In this case, a current corresponding to the electric charge accumulated in the capacitor element is supplied to the electro-optic element in a period shorter than the predetermined period in a state where the electro-optic element and the second transistor are electrically connected. A method for driving the electro-optical device. The method of driving an electro-optical device according to claim 10 .
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
A first switching element comprising a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A ninth terminal, a tenth terminal, and a fifth control terminal are provided, the ninth terminal is connected to the first control terminal, and the tenth terminal is the second terminal. A third switching element connected to
An eleventh terminal, a twelfth terminal, and a sixth control terminal, wherein the eleventh terminal is connected to the second terminal, and the twelfth terminal is included in the plurality of data lines. And a fourth switching element connected to one data line of the electro-optical device. The method of driving an electro-optical device according to claim 10 .
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
A first switching element comprising a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A thirteenth terminal, a fourteenth terminal, and a seventh control terminal; the thirteenth terminal is connected to the first connection terminal; and the fourteenth terminal is one of the plurality of data lines. A driving method for an electro-optical device, comprising: a fifth switching element connected to two data lines. The method of driving an electro-optical device according to claim 10 .
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
A first switching element comprising a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A fifteenth terminal, a sixteenth terminal, and an eighth control terminal; the fifteenth terminal is connected to the first terminal; and the eighth control terminal is the first control terminal. A third transistor connected to
A sixth switching element comprising a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, wherein the seventeenth terminal is connected to the first connection terminal;
A nineteenth terminal, a twentieth terminal, and a tenth control terminal, wherein the eighteenth terminal and the sixteenth terminal are connected to the nineteenth terminal, and the twentieth terminal is the plurality of terminals. An electro-optical device driving method comprising: a seventh switching element connected to one of the data lines. An electro-optical device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits each including an electro-optic element arranged corresponding to an intersection of the scanning lines and the data lines,
Each of the plurality of unit circuits is
A capacitive element that accumulates electric charge in accordance with a data signal supplied through the data line;
A first transistor whose conduction state is set according to the charge accumulated in the capacitor;
A second transistor whose conduction state is set according to the electric charge stored in the capacitor;
A first switching element that is connected to the second transistor and is turned on to pass a first current of a level corresponding to a conduction state of the second transistor;
The second transistor is connected to the first transistor and the first switching element, and is turned on together with the first switching element, so that the second current having a level corresponding to the conduction state of the first transistor together with the first current. A second switching element that passes the current and supplies the current to the electro-optic element,
The driving capability of the first transistor is A, the sum of the driving capability of the first transistor and the driving capability of the second transistor is B, and both the first switching element and the second switching element are turned on. Is set to C, and the period during which the first switching element is turned off and the second switching element is turned on is D, so that the relationship of A: B = C: D is satisfied. An electro-optical device , wherein a driving capability of one transistor and a driving capability of the second transistor are set . The electro-optical device according to claim 14,
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A ninth terminal, a tenth terminal, and a fifth control terminal are provided, the ninth terminal is connected to the first control terminal, and the tenth terminal is the second terminal. A third switching element connected to
An eleventh terminal, a twelfth terminal, and a sixth control terminal, wherein the eleventh terminal is connected to the second terminal, and the twelfth terminal is included in the plurality of data lines. And a fourth switching element connected to one of the data lines. The electro-optical device according to claim 14,
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A thirteenth terminal, a fourteenth terminal, and a seventh control terminal; the thirteenth terminal is connected to the first connection terminal; and the fourteenth terminal is one of the plurality of data lines. An electro-optical device comprising: a fifth switching element connected to two data lines. The electro-optical device according to claim 14,
Each of the plurality of unit circuits is
The first transistor comprising a first terminal, a second terminal, and a first control terminal;
A third terminal; a fourth terminal; and a second control terminal, wherein the third terminal is connected to the first terminal, and the second control terminal is the first control terminal. The second transistor connected to
The first switching element including a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal;
A second switching element comprising a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is connected to the second terminal and the sixth terminal;
The capacitive element comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is connected to the first control terminal, and the second connection terminal is connected to the first terminal. When,
A fifteenth terminal, a sixteenth terminal, and an eighth control terminal; the fifteenth terminal is connected to the first terminal; and the eighth control terminal is the first control terminal. A third transistor connected to
A sixth switching element comprising a seventeenth terminal, an eighteenth terminal, and a ninth control terminal, wherein the seventeenth terminal is connected to the first connection terminal;
A nineteenth terminal, a twentieth terminal, and a tenth control terminal, wherein the eighteenth terminal and the sixteenth terminal are connected to the nineteenth terminal, and the twentieth terminal is the plurality of terminals. An electro-optical device comprising: a seventh switching element connected to one of the data lines. The electro-optical device according to any one of claims 1 4 to 17,
The electro-optical device, wherein the electro-optical element is an EL element. The electro-optical device according to claim 18 ,
The electro-optical device, wherein the EL element is an organic EL element having a light emitting layer made of an organic material. An electronic apparatus comprising the electronic circuit according to any one of claims 5 to 9. An electronic apparatus comprising the electro-optical device according to any one of claims 14 to 19.

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