JP4121109B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a manufacturing method thereof. In particular, the present invention is effective for a semiconductor device using a thin film transistor (TFT) provided over a substrate having an insulating surface, and is an active matrix liquid crystal display device, a contact image sensor, an organic EL display device, a three-dimensional display. It can be used for IC and the like.
[0002]
[Prior art]
In recent years, high-performance semiconductor elements on insulating substrates such as glass, insulating films, etc. have been developed to realize large-sized, high-resolution liquid crystal display devices, high-speed, high-resolution contact image sensors, and three-dimensional ICs. Attempts have been made to form. As a semiconductor element used in these devices, a thin film silicon semiconductor is generally used. Thin film silicon semiconductors are roughly classified into two types: amorphous silicon semiconductors (a-Si) and crystalline silicon semiconductors.
[0003]
Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a vapor phase method, and are excellent in mass productivity. However, since this amorphous silicon semiconductor is inferior in physical properties such as conductivity compared to a silicon semiconductor having crystallinity, in order to obtain further high-speed characteristics in the future, a semiconductor device made of a silicon semiconductor having crystallinity can be simplified. There is a strong demand to establish a simple manufacturing method.
[0004]
As a method for producing a thin film silicon semiconductor having crystallinity, the following methods (1) and (2) are known.
[0005]
(1) After forming an amorphous silicon film, the amorphous silicon film is irradiated with an energy beam such as a laser beam, and the amorphous silicon film is crystallized by the light energy to have a crystalline silicon. A membrane.
[0006]
(2) After the amorphous silicon film is formed, it is heated and the amorphous silicon film is crystallized in the solid phase by the heat energy to obtain a crystalline silicon film.
[0007]
Generally, the above method (1) is used. In this method, since the crystallization phenomenon in the melting and solidifying process is used, the crystal grains are small, but there are few crystal defects in the crystal grains, and a relatively high-quality crystalline silicon film can be obtained. However, in the crystalline silicon film manufactured by the method (1), the defect density at the grain boundary portion becomes high, so that the defect at the grain boundary portion acts as a large trap with respect to carriers, and as a semiconductor device. Sufficient performance cannot be obtained. Also, for example, when using an excimer laser that is currently most commonly used as a laser light source, since the stability of the laser light is not sufficient, the entire surface of the substrate is uniformly processed over the entire semiconductor film. May not be applied, and there may be variations in characteristics among semiconductor elements.
[0008]
The method (2) is superior in uniformity and stability in the substrate as compared with the method (1), but it requires a heat treatment for about 30 hours under a high temperature condition of 600 ° C. or higher. There is a problem that the processing time becomes long and the throughput cannot be improved. Furthermore, in the method (2), since the crystal structure to be crystallized is a twin crystal structure, relatively large crystal grains of about several μm can be obtained, but a large number of twin defects are formed in one crystal grain. Therefore, the crystallinity is inferior to the crystallinity of the silicon semiconductor film produced by the method (1).
[0009]
On the other hand, a method for improving the method (2) to obtain a high-quality crystalline silicon film has been developed, and a catalyst element for promoting crystallization of the amorphous silicon film is introduced. Thus, a method for reducing the heating temperature, shortening the treatment time, and improving the crystallinity has attracted attention. Specifically, a crystalline silicon film is obtained by introducing a trace amount of a metal element such as nickel into the surface of the amorphous silicon film and then performing heat treatment.
[0010]
In such a method using a catalytic element, a crystal nucleus with an introduced metal element as a nucleus is generated early in an amorphous silicon film, and then crystallization progresses rapidly around this crystal nucleus. To do.
[0011]
Furthermore, in this method, the crystalline silicon film grown by crystal has a twin structure in which the crystalline silicon film grown by a normal solid phase growth method (method (2) above) has many crystal defects. In contrast, a plurality of columnar crystals have a structure connected by a network, and each columnar crystal is small but has a substantially single crystal inside.
[0012]
[Problems to be solved by the invention]
The method of crystallizing an amorphous silicon film by introducing a catalytic element into the amorphous silicon film and heat-treating can reduce the heating temperature and shorten the heating time, Furthermore, it has an advantage that the crystallinity of the silicon film obtained by heat treatment is superior to the crystalline silicon film obtained by other crystallization methods.
[0013]
However, if a large amount of catalytic elements mainly composed of these metals remain in the semiconductor film, the reliability, electrical stability, etc. of the semiconductor device using the silicon film obtained by this method are lowered. For this reason, it is necessary to prevent the catalyst element such as nickel that promotes crystallization of the amorphous silicon film from being contained as much as possible after crystallization. For this reason, a method of reducing the amount of catalyst element contained in the crystallized silicon film by minimizing the amount of catalyst element introduced for crystallization of the amorphous silicon film is the first. One method is considered. However, when the amount of the catalytic element introduced into the amorphous silicon film is reduced, the crystal growth state becomes extremely unstable, and the crystalline silicon film produced in such an unstable state is crystalline. There is a risk that the variation in the thickness of the semiconductor device becomes unusable as a film constituting the active region of the semiconductor device.
[0014]
In addition, after introducing a catalytic element into the amorphous silicon film and heat-treating it to grow an amorphous silicon film, the catalytic element is moved (gettering) to thereby move the catalytic element in the element region. A method of removing or reducing the above is considered as a second method.
[0015]
Japanese Patent Laid-Open No. 10-270363 discloses that a silicon film crystallized with a catalytic element is partly made into a region in which a group 5 B element such as phosphorus is selectively introduced and is subjected to heat treatment. A method is disclosed in which the amount of catalyst element in the region other than the group 5 B element is reduced by moving (gettering) the catalyst element to the region in which the group 5 B element is introduced. In this publication, a region in which no group 5 B element is introduced and the catalytic element is reduced by gettering is used as an active region of a semiconductor device.
[0016]
Japanese Laid-Open Patent Publication No. 11-31660 discloses a silicon film in which a thermal oxide film is formed on the surface of a silicon film crystallized by introducing a catalytic element, and phosphorus is contained in a high concentration on the thermal oxide film. After the film is provided, heat treatment is performed to move the catalytic element contained in the crystallized silicon film through the thermal oxide film to the silicon film containing a high concentration of phosphorus in the upper layer. Disclosed is a method for reducing the amount of catalytic element contained in a formed silicon film. In this publication, after removing the silicon film containing phosphorus in the upper layer, the silicon film having crystallinity in the lower layer is used as the active region of the semiconductor device.
[0017]
However, when the present inventor actually manufactured a thin film transistor (TFT) element by using the method of the above publication, the remaining catalytic element has an adverse effect on the TFT element, and is disclosed in the above publication. It has been clarified that the method cannot obtain a sufficiently high gettering effect, and the residual amount of the catalytic element in the active region of the semiconductor device cannot be sufficiently reduced.
[0018]
Specifically, the TFTs prototyped according to the above-mentioned publications show a slight difference, but a defective TFT having a very large leakage current at the time of off operation occurs with a probability of about several percent. When the cause of the increase in leakage current in the TFT in which the defect occurred was analyzed, it was confirmed that silicide due to the catalytic element was present at the junction between the channel portion and the drain portion. As a result, the method according to the above two publications has a high defect rate at which defective TFTs are generated, so that the reliability is low and the method is not capable of mass production.
[0019]
In the method according to the above two publications, heat treatment is performed for several hours to several tens of hours under a heating temperature condition of 550 ° C. or higher. Such heat treatment does not cause a problem when a small glass substrate of about 100 mm × 100 mm (100 mm □) size, an expensive quartz substrate, or the like is used.
[0020]
However, in an active matrix substrate for liquid crystal display or organic EL display for forming a semiconductor element to be a semiconductor device, the mother board (glass substrate) tends to be enlarged in order to reduce the cost. In order to reduce the size and weight of the glass substrate, there is a tendency to make it thinner, and it is very difficult to perform heat treatment for a long time on a large and thin glass substrate.
[0021]
Actually, the present inventor conducted heat treatment using a glass substrate of Corning Code 1737 having a size of 600 mm × 720 mm and a thickness of 0.7 mm as a commonly used glass substrate, It was clarified that the heat treatment for several hours under the heating condition of about 500 ° C. is almost limit. The biggest problem caused by this heat treatment is deflection and warpage due to the weight of the substrate. Furthermore, since the heat treatment is performed after the pattern is formed on the substrate, shrinkage (shrinkage) peculiar to the glass substrate occurs, and it is very difficult to align the pattern before and after the heat treatment step. It has become.
[0022]
In addition, the method disclosed in Japanese Patent Application Laid-Open No. 11-31660 provides a silicon film containing phosphorus at a high concentration over the entire surface of a crystalline silicon film serving as an active region. Since the contained catalytic element is moved in the vertical direction (film thickness direction) to the upper silicon film, the gettering distance (distance to which the catalytic element should move) is the length of the film thickness. Yes. For this reason, compared with the case where the catalyst element is moved in the lateral direction, the gettering distance is shortened, and a high gettering effect can be obtained.
[0023]
However, as a result of experiments conducted by the inventors of the present invention using a TFT fabricated by this method, this method has the same level or rather inferior results compared to the above method, and has excellent gettering ability. It was clarified that the concentration of the catalytic element could not be reduced sufficiently. In the method according to this publication, a thermal oxide film is interposed between a crystalline silicon film and a silicon film containing a high concentration of phosphorus in the upper layer. Under the heat treatment conditions at a low temperature and in a short time as expected, a gettering effect could not be obtained at all.
[0024]
The present invention has been made in order to solve the above-mentioned problems, and the crystallinity grown by introducing a catalytic element into an amorphous silicon film formed on a large glass substrate to be mass-produced. An object of the present invention is to provide a semiconductor device in which the catalytic element contained in the element region of the silicon film is sufficiently reduced and a method for manufacturing the same.
[0025]
[Means for Solving the Problems]
  In order to solve the above problems, the semiconductor device of the present inventionThe manufacturing method includes the steps of forming an amorphous silicon film on a substrate having an insulating surface, introducing nickel on the amorphous silicon film as a catalytic element for promoting crystallization of the amorphous silicon film, Performing a first heat treatment for crystallizing the crystalline silicon film to crystallize the amorphous silicon film into a crystalline silicon film, and performing a plasma CVD method on the crystalline silicon film; A step of forming an amorphous silicon film containing an element selected from rare gases, and a second heat treatment for transferring nickel contained in the crystalline silicon film to the amorphous silicon film. And moving nickel contained in the crystalline silicon film to the amorphous silicon film, and then removing the amorphous silicon film and forming an active region by the crystalline silicon film. A crystallinity comprising The step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the silicon film includes at least a silane gas-based gas and a gas containing an element selected from the rare gas. Is used as a source gas, and the amorphous silicon film is different from the RF bias on the insulating substrate side in addition to the RF bias supplied from the CVD electrode arranged to face the insulating substrate. The film is formed by the dual bias to which the RF bias is applied.
[0026]
  Further, the method for manufacturing a semiconductor device of the present invention includes forming an amorphous silicon film on a substrate having an insulating surface, and nickel as a catalytic element for promoting crystallization of the amorphous silicon film on the amorphous silicon film. A step of crystallizing the amorphous silicon film into a crystalline silicon film by performing a first heat treatment for crystallizing the amorphous silicon film, and the crystalline silicon film Further, an amorphous silicon film containing an element selected from rare gases is formed using a plasma CVD method with a concentration distribution such that the concentration of the element selected from the rare gases changes in the film thickness direction. And performing a second heat treatment for transferring nickel contained in the crystalline silicon film to the amorphous silicon film, and converting the nickel contained in the crystalline silicon film into the amorphous silicon. Moving to the membrane, then The amorphous silicon film is removed, characterized in that it comprises a step of forming an active region by the crystalline silicon film.
[0027]
  Further, the method for manufacturing a semiconductor device of the present invention includes forming an amorphous silicon film on a substrate having an insulating surface, and nickel as a catalytic element for promoting crystallization of the amorphous silicon film on the amorphous silicon film. A step of crystallizing the amorphous silicon film into a crystalline silicon film by performing a first heat treatment for crystallizing the amorphous silicon film, and the crystalline silicon film Further, a step of forming an amorphous silicon film containing an element selected from rare gases using a plasma CVD method and nickel contained in the crystalline silicon film are transferred to the amorphous silicon film Performing the second heat treatment to move nickel contained in the crystalline silicon film to the amorphous silicon film, and then removing the amorphous silicon film to obtain the crystalline silicon. Process to form active area by membrane And the step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the crystalline silicon film is selected from a silane gas-based gas and a rare gas A gas containing at least a gas containing an element is used as a source gas, and the amorphous silicon film is selected from the rare gases by a bias supplied from a CVD electrode disposed to face the insulating substrate. After the formation of the lower layer film having a low element concentration, in addition to the bias supplied from the CVD electrode, the insulating substrate side is selected from the rare gases by a dual bias in which another bias different from this bias is applied. It is formed by forming an upper layer film having a high concentration of the above elements.
[0028]
  The element selected from the rare gases is preferably one or more of Ar, Kr, and Xe..
[0029]
  Ar is preferably contained as an element selected from the rare gases..
[0030]
  The concentration of the element selected from the rare gases is 1 × 10 ¹⁹ ~ 2x10 ^{twenty one} atoms / cm ^Three Is preferably within the range of.
[0031]
  The concentration of the element selected from the rare gases is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three Is preferably within the range of.
[0032]
  The step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the crystalline silicon film includes a silane gas and a gas containing an element selected from a rare gas. Is used as a source gas, and in addition to the bias supplied from the CVD electrode disposed opposite to the insulating substrate, the amorphous silicon film has a bias on the insulating substrate side. It is preferable that the film is formed by a dual bias to which another different bias is applied..
[0033]
  Containing an element selected from the rare gasesAmorphous silicon filmThe process of forming a filmAn RF bias is applied to the CVD electrode, and another RF bias is applied to the insulating substrate.Is preferable.
[0034]
  The frequency of the RF bias applied to the insulating substrate is preferably smaller than the frequency of the RF bias supplied from the CVD electrode..
[0035]
  The amorphous silicon film containing an element selected from the rare gases preferably has a concentration distribution such that the concentration of the element selected from the rare gases changes in the film thickness direction..
[0036]
  The amorphous silicon film containing an element selected from the rare gases is preferably formed such that the concentration of the element selected from the rare gases is high on the upper surface side and low on the lower surface side..
[0037]
  The amorphous silicon film containing an element selected from the rare gases is formed into a two-layer structure of a lower layer film having a low concentration of the element selected from the rare gases and an upper layer film having a high concentration of the element. It is preferred that
[0038]
  An amorphous silicon film containing an element selected from the rare gases forms the lower layer film only by a bias supplied from the CVD electrode, and in addition to the bias supplied from the CVD electrode on the lower layer film Preferably, the upper layer film is formed on the insulating substrate side by a dual bias to which a different bias from this bias is applied..
[0039]
  The amorphous silicon film containing an element selected from the rare gases is preferably formed continuously using the same chamber..
[0040]
  The step of moving the nickel contained in the crystalline silicon film to the amorphous silicon film containing an element selected from the rare gases by the second heat treatment includes the step of moving the nickel contained in the crystalline silicon film. It is preferable that the concentration and the concentration of the nickel contained in the amorphous silicon film are performed under heating conditions of heating temperature and heating time so that at least a segregation state in a thermal equilibrium state is obtained..
[0041]
  The step of transferring the nickel contained in the crystalline silicon film to the amorphous silicon film containing an element selected from the rare gases by the second heat treatment includes at least crystallization of the amorphous silicon film. It is preferable to be carried out under heating conditions such as heating temperature and heating time.
[0042]
  The heating condition of the second heat treatment is preferably a treatment time ranging from 30 minutes to 4 hours, with the temperature range of 450 to 550 ° C. being the heating temperature..
[0044]
  The second heat treatment is preferably performed by a rapid thermal annealing treatment in a temperature range of 600 to 700 ° C. with a treatment time of 10 seconds to 10 minutes..
[0045]
  The rapid thermal annealing treatment is preferably performed by spraying an inert gas heated to a high temperature toward the surface of the insulating substrate..
[0046]
  A barrier thin film serving as an etching stopper when removing the amorphous silicon film is preferably provided between the crystalline silicon film and the amorphous silicon film containing an element selected from the rare gases..
[0047]
  The barrier thin film is preferably a silicon oxide film having a thickness of 50 mm or less..
[0048]
  Before performing the step of forming an amorphous silicon film containing an element selected from the rare gases, the step of irradiating the crystalline silicon film with laser light to further improve the crystallinity may be performed. preferable.
[0056]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor device and the manufacturing method thereof according to the present invention will be described in detail.
[0057]
The gist of the semiconductor device manufacturing method of the present invention is to sequentially perform the following steps (1) and (2).
[0058]
(1) After introducing a catalytic element for promoting crystallization into an amorphous silicon film formed on an insulating substrate, the amorphous silicon film is crystal-grown by performing a heat treatment (first heating) processing).
[0059]
(2) After an amorphous silicon film containing an element selected from rare gases is formed on the crystalline silicon film crystallized by the first heat treatment by using a plasma CVD method, heating is performed. Treatment is performed (second heat treatment).
[0060]
In the method for manufacturing a semiconductor device of the present invention, the catalytic element contained in the lower crystalline silicon film is moved to the upper amorphous silicon film by performing the second heat treatment. Then, after the catalytic element is moved in the upper amorphous silicon film, the upper amorphous silicon film is removed, and the semiconductor device is formed using the crystalline silicon semiconductor film with the lower lower catalytic element as an active region. Form.
[0061]
By moving the catalyst element by performing the step (2), the amount of the catalyst element remaining in the active region of the semiconductor device can be greatly reduced as compared with the conventional method using the catalyst element. As a result, it is possible to obtain a high-performance semiconductor device having a high current driving capability in which the abnormality of the leakage current during the off operation, which has been a problem in the semiconductor device manufactured using the conventional method, is not observed.
[0062]
Generally, as one of the mechanisms for moving (gettering) a catalytic element to a desired region (hereinafter referred to as a gettering region), the solid solubility of the catalytic element in the gettering region is determined by the region to be gettered ( Hereinafter, there is a method (first gettering action) in which the catalytic element is gettered in the gettering region by making it higher than the solid solubility of the gettering region).
[0063]
In the above-mentioned publications (Japanese Patent Laid-Open Nos. 10-270363 and 11-31660), the solid solubility of the catalytic element in the amorphous silicon film is dramatically improved by introducing phosphorus into the amorphous silicon film. Since the movement of the catalytic element, that is, the first gettering action is performed due to the difference in solid solubility, phosphorus is all used as a gettering element for gettering the catalytic element. Used. In addition, in the method disclosed in Japanese Patent Application Laid-Open No. 11-54760, it is attempted to improve the gettering ability by further introducing a Group 3 B element, but even if a Group 3 B element is used alone, gettering is performed. There is no effect, and the catalyst element is basically gettered by the gettering effect of phosphorus.
[0064]
As another mechanism for gettering the catalyst element, a defect or a local segregation site that traps the catalyst element is formed in the gettering region, and the catalyst element is moved to the defect or segregation site and trapped. There is a (second gettering action) method.
[0065]
According to recent research, when some elements selected from rare gases are present in the amorphous silicon film as gettering elements other than the group 5 B elements such as phosphorus, the portion where the rare gas elements are present is large. Since interstitial distortion occurs and the second gettering action due to local defects / segregation sites works very strongly, some elements selected from rare gases other than Group 5 B elements such as phosphorus described above It has been shown to be effective as a gettering element.
[0066]
Elements selected from such rare gases having a gettering effect include Ar, Kr, and Xe, and any one or more of these elements can be used. Furthermore, it has been found that Ar has the highest effect among these elements.
[0067]
Such a second gettering action has higher gettering ability than the first gettering action utilizing the difference in solid solubility. In addition, as a gettering element, a rare gas element that is inert even if contained in a semiconductor film is used instead of an element that greatly affects the characteristics of a semiconductor device such as phosphorus. Problems such as reverse diffusion and contamination of gettering elements into the region do not occur.
[0068]
Furthermore, the above rare gas elements are present in the amorphous silicon film, thereby inhibiting the crystal growth of the amorphous silicon film. As a result, the crystal growth of this amorphous silicon film (generation of crystal nuclei) It has the effect of delaying the crystal growth rate. Therefore, the amorphous silicon semiconductor film is maintained in an amorphous state during the second heat treatment for gettering the catalytic element contained in the crystalline silicon film to the amorphous silicon film. And a larger second gettering action can be obtained.
[0069]
Further, in the method for manufacturing a semiconductor device of the present invention, an amorphous silicon film containing a rare gas element on a crystalline silicon film serving as an active region, as in the method described in Japanese Patent Application Laid-Open No. 11-31660. The catalytic element contained in the crystalline silicon semiconductor film is gettered in the vertical direction (film thickness direction).
[0070]
In such gettering of the catalytic element in the film thickness direction, the gettering distance is only a distance corresponding to the film thickness of the crystalline silicon film. The gettering distance can be set shorter than the general gettering in the horizontal direction as described in each of Japanese Patent Nos. 11-54760. This makes it possible to lower the heating temperature or shorten the heating time in the second heat treatment for gettering the catalytic element, and is used as a motherboard for liquid crystal display devices and organic EL display devices. This means that it is possible to cope with a large-sized inexpensive glass substrate having the size of
[0071]
FIG. 3 shows the concentration of Ar contained in the amorphous silicon film (horizontal axis) and the catalytic element (Ni) remaining in the crystalline silicon film after the second heat treatment for gettering the catalytic element. It is a graph which shows the relationship with a density | concentration (vertical axis | shaft).
[0072]
Referring to FIG. 3, the initial Ni concentration before gettering the catalytic element is 1.2 × 10.¹⁸atoms / cm^ThreeIt has become. In this case, the Ar concentration contained in the amorphous silicon film is 3 × 10¹⁸atoms / cm^ThreeIn the following cases, it is shown that the effect of reducing the Ni concentration is not seen at all, and the gettering of the catalytic element to the amorphous silicon film does not occur. On the other hand, the Ar concentration contained in the amorphous silicon film is 1 × 10¹⁹atoms / cm^ThreeWhen this is the case, a gettering effect appears abruptly with this value as a boundary, and a reduction in Ni concentration is observed. As the gettering action, it cannot be said that it is an obvious effect unless a decrease in Ni concentration of an order of magnitude or more is shown at least. In this respect, the lower limit of the Ar concentration contained in the amorphous silicon film is 1 × 10¹⁹atoms / cm^ThreeIn order to obtain a clear gettering action, it is necessary that Ar with an Ar concentration higher than this be contained in the amorphous silicon film. The Ar concentration in the amorphous silicon film is 1 × 10.²⁰atoms / cm^ThreeWhen it is more than about, a saturation tendency is seen in the decrease of the Ni concentration remaining in the crystalline silicon film. Therefore, in order to maximize the gettering effect of the catalytic element according to the present invention, the Ar concentration in the amorphous silicon film is 1 × 10²⁰atoms / cm^ThreeThe above is more desirable.
[0073]
On the other hand, the upper limit of the Ar concentration contained in the amorphous silicon film is limited by the problem of film peeling, and the Ar concentration is 2 × 10.^{twenty one}atoms / cm^ThreeIf it becomes above, a film | membrane will become very porous and film | membrane peeling and peeling will arise. Therefore, the upper limit of Ar concentration is at least 2 × 10^{twenty one}atoms / cm^ThreeMust be: Further, in order to more reliably suppress film peeling and peeling, 1 × 10^{twenty one}atoms / cm^ThreeThe following is desirable.
[0074]
In the semiconductor manufacturing method of the present invention, the concentration of the element selected from the rare gases contained in the amorphous silicon semiconductor film is 1 × 10 5 according to the above description.¹⁹~ 2x10^{twenty one}atoms / cm^ThreeIt is desirable to be within the range. 1 × 10²⁰~ 1x10^{twenty one}atoms / cm^ThreeMore preferably, it is within the range.
[0075]
The silicon film having crystallinity obtained by using the method for manufacturing a semiconductor device of the present invention is subjected to a light etching process using a fluorine-based etchant, which has been conventionally used as a method for easily confirming the remaining of a catalytic element. Even when an evaluation test for revealing the remaining catalytic elements is performed, no etch pits that have been seen in the conventional method are observed. Further, as a severe evaluation test, even if an evaluation test for detecting the catalyst element in the silicide state by recondensing the remaining catalyst by performing heat treatment at a high temperature to form a silicide state, reaggregation of the catalyst element Unlike the crystalline silicon film obtained by the method of the above-mentioned three publications, in which no re-aggregation of the catalytic element was observed.
[0076]
When the inventor of the present application actually manufactured a thin film transistor (TFT) using the method for manufacturing a semiconductor device of the present invention, no abnormal increase phenomenon of leakage current that might occur at the time of the TFT off-operation was found at all. 0%. On the other hand, in the TFT manufactured by the conventional method described in the above-mentioned publication, an abnormal increase phenomenon of the leakage current was observed with a probability of 3% or more when the TFT was turned off. Further, in a liquid crystal display device using TFTs manufactured by the semiconductor manufacturing method of the present invention, linear display unevenness (sampling in the driver section) frequently occurred in liquid crystal display devices using TFTs manufactured by conventional methods. There was no pixel defect due to the leakage current during the off operation due to the TFT), the display quality could be greatly improved, and the yield rate could be dramatically increased.
[0077]
In the method for manufacturing a semiconductor device of the present invention, the amorphous silicon semiconductor film containing a rare gas element is formed by using a plasma CVD method.
[0078]
Conventionally, as a method of forming an amorphous silicon film containing such a rare gas element, a non-doped amorphous silicon film is formed and an ion doping method is used for the amorphous silicon film. A method of implanting rare gas ions and a method of forming an amorphous silicon film by sputtering using a Si target with these rare gases as sputtering gases are known.
[0079]
However, in the method of implanting rare gas ions using the ion doping method, it is necessary to prepare an expensive doping apparatus in addition to the film forming apparatus, and the film forming and the doping are performed in separate processes. Productivity is poor and costs are high. Further, it is not easy to implant a large amount of ions by using the ion doping method, and the tact time (processing time per substrate) becomes long, and the productivity is deteriorated. On the other hand, when a sputtering method using a Si target is used, discharge by RF or pulse DC is essential, but it is not easy to stably discharge by such a method, and abnormal discharge may occur frequently. is there. In particular, when the size of the substrate is increased, it is more difficult to generate a stable discharge, and no mass production apparatus having sufficient performance is commercially available even with a substrate having a size of 500 mm × 500 mm (500 mm □). In addition, there is a problem that the number of particles unique to sputtering becomes very large.
[0080]
In contrast, the inventor of the present application succeeded in forming an amorphous silicon film containing a rare gas element by using a plasma CVD method. In the plasma CVD method, mass production apparatuses for metric size glass substrates are generally commercially available, and chamber cleaning with a cleaning gas can be performed, so that particle countermeasures are good. However, since this plasma CVD method is a film formation based on a chemical reaction, a rare gas element that is inert to the chemical reaction is merely introduced as a film formation gas, but only acts as a carrier gas. The amorphous silicon semiconductor film is not included at all.
[0081]
The present inventor uses a source gas containing at least a silane-based gas and a rare gas as a source gas in the step of forming an amorphous silicon semiconductor film using a plasma CVD method. In addition, it has been found that when a film forming process is performed by a dual bias in which another bias is applied, a large amount of a rare gas element is contained in the formed amorphous silicon film. In this case, it is most effective to apply an RF bias (voltage) to the CVD electrode and separately apply an RF bias (voltage) to the substrate side, which is more amorphous than when a DC bias is applied to the substrate side. It has been found that the content of rare gas elements contained in the porous silicon semiconductor film is increased. However, it is shown that even when a DC voltage is applied to the substrate side, an effect including a rare gas element can be obtained as compared with a case where no bias voltage is applied. In this case, the frequency of the RF bias applied to the CVD electrode is different from the frequency of the RF bias applied to the substrate side, and the RF bias applied to the substrate side is higher than the frequency of the RF bias applied to the CVD electrode. If the frequency is made smaller, it is desirable because plasma matching is good and stable discharge can be obtained.
[0082]
FIG. 4 shows the relationship between the concentration of Ar contained in the amorphous silicon semiconductor film obtained by applying 100 W of RF power to the CVD electrode and displacing the RF power applied to the substrate side. It is a graph showing the result. In this experiment, SiH was used as the film forming gas._FourAnd Ar, and the RF frequency was 27.12 MHz on the CVD electrode side and 1.6 MHz on the substrate side. The substrate temperature during film formation varies depending on the film formation pressure. Referring to FIG. 4, the Ar concentration of Ar contained in the amorphous silicon semiconductor film is dramatically increased by applying a bias to the substrate side. When the bias power on the substrate side is 0 W, the conditions are the same as those in a general plasma CVD film forming process. In this case, Ar merely acts as a carrier gas, and only a minimal amount of Ar is present. It was found that a large amount of Ar element was included in the film by applying a bias to the substrate side.
[0083]
FIG. 5 is a schematic view for explaining a plasma CVD apparatus used in the step of forming an amorphous silicon film containing a rare gas element in the method for manufacturing a semiconductor device of the present invention. FIG. 1 shows a normal plasma CVD apparatus, and (b) shows a plasma CVD apparatus used in the present invention.
[0084]
The normal plasma CVD apparatus shown in FIG. 5A has a chamber 503 for performing a film forming reaction on a substrate, and the substrate 501 is placed in a horizontal state in the chamber 503. The substrate 501 is grounded together with the chamber 503 so as to have the same potential as the chamber 503. A CVD electrode 502 is provided on the substrate 501 placed in the chamber 503 so as to face the substrate 501. The CVD electrode 502 is connected to an RF power source 504 provided outside the chamber 503, and RF power is supplied from the RF power source 504 to the CVD electrode 502 when forming a film on the substrate 501 in the chamber 503. It has become.
[0085]
On the other hand, the plasma CVD apparatus shown in FIG. 5B has a chamber 503, a CVD electrode 502, and an RF power source 504, similarly to the plasma CVD apparatus shown in FIG. A second RF power source 505 is provided outside the chamber 503 for supplying the substrate 501 with RF power having a completely different frequency from the RF power supplied to the CVD electrode 502. In this plasma CVD apparatus, a substrate 501 placed in a chamber 503 is connected to a second RF power source 505 and is independent of the potential of the grounded chamber 503. In this manner, by supplying an RF power having a frequency different from the RF power supplied from the CVD electrode 502 to the substrate 501, a film-forming gas containing a rare gas element is used, so that a large amount of a rare gas element is used. An amorphous silicon film containing a gas element can be obtained.
[0086]
When the plasma CVD method is performed using the plasma CVD apparatus having the above structure, a slight amount of rare gas element may be injected into the crystalline silicon film formed on the substrate. Although the rare gas element itself does not adversely affect the characteristics of the semiconductor device, in the present invention, since the catalyst element is used as a gettering element for gettering, a crystalline silicon film serving as an active layer If a rare gas element is introduced into the substrate, the gettering effect of gettering the catalyst element is reduced, and the possibility that the catalyst element remains on the surface of the crystalline silicon film is increased. From this point, in the present invention, the concentration of the element selected from the rare gases contained in the amorphous silicon film is not uniformly distributed in the amorphous silicon film. It is desirable that the distribution be such that the concentration increases with increasing distance from the surface of the crystalline silicon film along the thickness direction.
[0087]
By setting the concentration of the rare gas contained in the amorphous silicon film to such a distribution, a getter for gettering the catalytic element is formed on the upper layer side of the amorphous silicon film having a high concentration distribution of the rare gas element. On the lower layer side of the amorphous silicon film where the ring capacity is high and there is a high concentration of catalytic elements and the concentration distribution of the rare gas elements is low, the concentration of the gettered catalytic elements is low and the crystal Concentration distribution occurs in the catalytic element gettered from the conductive silicon film. For this reason, after the gettering of the catalyst element, the residual amount of the catalyst element, particularly in the vicinity of the surface of the crystalline silicon film, can be reduced.
[0088]
As a specific method for forming an amorphous silicon film having a high concentration gradient of the rare gas element on the upper layer side with respect to the film thickness direction, the amorphous silicon film is composed of two layers consisting of an upper layer and a lower layer. As the structure, the method of forming the upper layer film so that the concentration containing the rare gas element is higher than that of the lower layer film is the simplest, and stable processing can be performed in terms of process and apparatus.
[0089]
  In the plasma CVD process in this case, a mixed gas containing at least a silane-based gas and a rare gas is used as a source gas, and the lower layer film having a low rare gas concentration is shown in FIG.InAs shown in the plasma CVD apparatus shown in FIG. 5, the upper film formed by supplying a single bias to the CVD electrode and having a high rare gas concentration is formed on both the CVD electrode and the substrate of the plasma CVD apparatus shown in FIG. Are formed by supplying different biases. That is, the lower layer film is formed by a normal plasma CVD method that does not supply a bias to the substrate side, and the upper layer film is formed by a dual bias plasma CVD method unique to the present invention that supplies a bias to both the CVD electrode and the substrate. A two-layered amorphous silicon film is formed. Note that in this case, continuous two-layer film formation can be performed without exposure to the air by using a plasma CVD apparatus having a multi-chamber in which a plurality of chambers are continuous.
[0090]
Further, using the plasma CVD apparatus shown in FIG. 5 (b), the lower layer and the upper layer are continuously formed by turning on and off the second RF power source for supplying the RF power to the substrate side in the same chamber. For example, a two-layer film can be formed with the same number of steps as when forming a single-layer film, and there is no demerit when forming a two-layer structure such as a reduction in processing capability in a plasma CVD apparatus, and it is stable. Thus, a film can be formed.
[0091]
In the method for manufacturing a semiconductor device of the present invention, the second heat treatment for gettering the catalytic element is a large parameter that affects the effect of the present invention. In order to get the catalytic element contained in the crystalline silicon film to getter to the amorphous silicon film, a certain amount of heat treatment time and time are required, but the concentration of the catalytic element contained in the crystalline silicon film And the concentration of the catalytic element in the amorphous silicon film are most preferably carried out in a heat treatment time and a heat time so that at least a segregation state occurs in a thermal equilibrium state. When heat treatment is performed so as to achieve such a segregation state, the gettering action is saturated, and the highest and stable gettering effect can be obtained. On the other hand, if the heat treatment is performed in a state in which such a segregation state has not been reached, the catalyst element becomes a halfway movement state, and an unstable state from the process aspect.
[0092]
Further, the amorphous silicon film serving as a gettering sink of the catalytic element is heated in a state where it is not crystallized at least completely, preferably in a state where no crystal nucleus is generated, by performing the second heat treatment. It is desirable to perform processing. By adopting such heat treatment conditions, in addition to the rare gas element contained in the amorphous silicon film, defects such as dangling bonds in the amorphous silicon film become segregation sites for the catalytic element, and the catalytic element is made amorphous. Move to the silicon film and trap. That is, the maximum gettering segregation sites can be maintained throughout the second heat treatment step in which the catalytic element contained in the crystalline silicon film is transferred to the amorphous silicon film. The effect can be maximized.
[0093]
From the above viewpoints, it is desirable that the actual second heat treatment condition is that the heating temperature is in the range of 450 ° C. to 550 ° C. and the treatment time is 30 minutes to 4 hours. If the second heat treatment is performed under such conditions, the concentration of the catalytic element contained in the crystalline silicon film and the concentration of the catalytic element in the amorphous silicon film are segregated at least in a thermal equilibrium state, Further, the amorphous silicon film is not crystallized, and both of the above two conditions can be satisfied.
[0094]
In the present invention, since the catalytic element is gettered in the direction of the film thickness, the gettering distance is very short as much as the thickness of the film thickness, so the heat treatment temperature in the heat treatment is low as in the above range. And the processing time can be shortened.
[0095]
Even if the heating temperature is set to 450 ° C. or lower, it is possible to satisfy the above two conditions if the processing time is lengthened. However, the processing time becomes longer and the throughput deteriorates and the number of devices and footprint increase. It is difficult to adopt as a mass production process.
[0096]
In the method for manufacturing a semiconductor device of the present invention, in order to improve the process margin when the second heat treatment for gettering the catalytic element is applied even to a large glass substrate having a metric size, The structure of the heat treatment apparatus for performing the heat treatment 2 is important.
[0097]
In the present invention, as the apparatus for performing the second heating treatment in the above temperature range, there is a core tube formed in a cross-sectional shape having a substantially similar shape to a substrate having a planar shape (rectangular shape). However, it is possible to use a furnace in which the substrate placed in the core tube is arranged so that the substrate surface is directed in the core direction and the space between the core tube and the substrate is minimized. desirable.
[0098]
6A to 6D schematically illustrate a furnace for use in the second heat treatment in the method for manufacturing a semiconductor device of the present invention.
[0099]
As shown in FIG. 6 (a), this furnace furnace has a quartz board 602 on which a plurality of substrates 601 are placed horizontally so as to be equidistant from each other (indicated by 605 in the figure). The quartz board 602 on which a plurality of substrates 601 are placed is fitted from below into a hollow quartz tube (core tube) 603 that accommodates the quartz board 602, and the substrate 601 is in this state. The heat treatment is performed.
[0100]
As shown in FIG. 6B, the cross-sectional shape of the quartz tube 603 is a rectangular shape that is a substantially similar shape that is slightly larger than the outer shape of the substrate 601.
[0101]
Conventionally, silicon wafers such as ICs have been formed in a circular shape, and a furnace that heats such a wafer is formed to have a circular cross-sectional shape as shown in FIG. The On the other hand, since the glass substrate which becomes a mother board such as an active matrix substrate for liquid crystal display is all formed in a rectangular shape, when a rectangular substrate is set in a quartz tube of a conventional furnace, A large gap 606 is generated between the substrate 601 and the quartz tube 603. When such a gap 606 is generated, a temperature distribution generated in the substrate 601 at the time of temperature increase / decrease during the heat treatment is large, for example, a temperature exceeding 200 ° C. between the peripheral portion and the central portion of the substrate 601. Distribution occurs, and the substrate is warped or cracked frequently due to the influence of the temperature distribution.
[0102]
The present inventor has found that the gap 606 formed between the side peripheral portion of the quartz tube 603 and the side portion of the substrate 601 and the substrate pitch 605 between the substrates 601 are increased or decreased during the heat treatment in the furnace. It was found that this is a large parameter for the temperature distribution in the substrate 601. Furthermore, it has also been found that by making such parameters appropriate, the temperature raising / lowering speed of the substrate 601 can be improved as compared with the conventional apparatus, and the processing capability can be improved.
[0103]
The gas flow of the atmospheric gas supplied from the upper part of the quartz tube 603 and circulated in the furnace is the inner peripheral part of the quartz tube 603 and the side edge of the substrate 601 as indicated by arrows 609 to 611 in FIG. The flow follows the surface of each substrate 601 through the gap 606 formed between the two. The gas supply amount of the atmospheric gas supplied onto the substrate 601 by the flow indicated by the arrow 611 is proportional to the flow rate of the atmospheric gas 610 flowing through the gap 606 between the substrate 601 and the quartz tube 603, It is proportional to the square of the substrate pitch 605 between the substrates. Therefore, in order to increase the flow rate of the atmospheric gas indicated by the arrow 610, it is not sufficient to increase the gas supply amount of the supply gas, and by minimizing the gap 606 between the quartz tube 603 and the substrate 601. The flow rate of the atmospheric gas can be improved.
[0104]
In the furnace for use in the method for manufacturing a semiconductor device of the present invention, a furnace core tube (quartz tube) 603 having a rectangular cross section having a substantially similar shape slightly larger than that of the substrate 601 is used. The gap 606 between them can be minimized over the entire outer periphery of the substrate 601. Accordingly, in addition to the optimization of the substrate pitch 605 formed between the substrates 601, the temperature distribution generated in the substrate 601 at the time of raising and lowering temperature can be kept substantially constant, and a large size having a metric size. Even if the glass substrate is subjected to the second heat treatment, it is possible to perform a stable treatment without cracking, warping or the like. Such a thing can be realized even if the conventional circular quartz tube 603 shown in FIG. 6C is used, because a portion where the gap between the substrate 601 and the quartz tube 603 is wide is generated. Can not.
[0105]
The quartz board 602 on which a plurality of substrates 601 are set is located at a home position 607 below the quartz tube 603 before the start of heat treatment, and a certain amount of residual heat of about 200 ° C. is performed at the home position 607. . When heat treatment is performed, the quartz tube 603 is fitted in the direction indicated by the arrow 604, and the quartz tube 603 is heated at the same time as the quartz tube 603 is fitted. Is inserted into the quartz tube 603 and enters a predetermined position (annealing zone) 608 for performing the heat treatment, and the heat treatment is started. On the other hand, the temperature lowering after the heat treatment is performed by moving the quartz board 602 to the home position 607 which is the remaining heat zone.
[0106]
Note that the furnace shown in FIG. 6A includes a quartz tube 603 having a multi-chamber configuration in which a plurality of quartz boards 602 connected in a cluster shape are accommodated, and a plurality of quartz substrates in which a large number of substrates 601 are set. By allowing the board 602 to be heat-treated at the same time, a heating device having a very high processing capability can be obtained.
[0107]
In addition, as the second heat treatment in the method for manufacturing a semiconductor device of the present invention, the heating temperature is set to 600 ° C. to 750 ° C. by high-speed thermal annealing in addition to the heat treatment using the furnace. Processing may be performed within a range of 10 seconds to 10 minutes. If it is within the range of such heating temperature and treatment time, as the second heat treatment, the concentration of the catalytic element contained in the crystalline silicon film and the concentration of the catalytic element in the amorphous silicon film are: At least in the thermal equilibrium state, the segregation state occurs, and the amorphous silicon film does not crystallize, and both of the above two conditions can be satisfied. Furthermore, if the heat treatment is performed under such high-speed thermal annealing conditions, the processing temperature becomes high, but the processing time is greatly shortened, so that the substrate (glass substrate) is increased in size and thickness. The present inventors have confirmed through experiments that the thermal deformation of can be suppressed and can be sufficiently applied.
[0108]
As an apparatus for performing such rapid thermal annealing, there is generally a lamp irradiation method using a tungsten-halogen lamp, an arc lamp or the like. However, in an apparatus using such a lamp method, unevenness in lamp illuminance occurs, and when the substrate is transferred by the conveyor method, heat unevenness occurs in the substrate when the heating process is raised or lowered by the transfer of the substrate, Uniform heat treatment is not easy for a large metric glass substrate, and thermal changes such as warping and cracking are likely to occur in the substrate. In addition, when the temperature uniformity on the substrate is not maintained using the rapid thermal annealing method, the region where the catalytic element is not sufficiently gettered on the substrate, the amorphous silicon semiconductor film is crystallized, Since a region where the gettering effect is reduced is generated, high temperature uniformity is required when the high-speed thermal annealing method is used.
[0109]
Therefore, the rapid thermal annealing apparatus in the present invention is preferably performed by spraying an inert gas such as nitrogen heated to a high temperature uniformly on the substrate surface.
[0110]
FIG. 7 is a schematic view showing such a rapid thermal annealing apparatus.
[0111]
This high-speed thermal annealing apparatus uses a single-wafer method in which substrates are sequentially processed one by one. The rapid thermal annealing apparatus includes a quartz tube 703 that is provided so as to cover the surface and side portions of the substrate 701 and that makes the surface of the substrate 701 a thermal annealing atmosphere. A lower side of the quartz tube 703 is open, and a quartz table 702 that supports the substrate 701 in a state of being accommodated in the quartz tube 703 in a horizontal state is provided. The quartz table 702 has a horizontal plate-like flat portion 702a and a plurality of protruding portions 702b protruding upward from a desired position of the flat portion 702a, and the substrate 701 protrudes from the flat portion 702a. The plurality of protrusions 702b are point-supported. The quartz table 702 is provided so as to be movable up and down, and when performing thermal annealing on the substrate 701, the quartz table 702 is moved upward along an arrow 704 in the drawing.
[0112]
  A gas introduction passage 703a is provided at a substantially central portion of the upper portion of the quartz tube 703, and nitrogen gas is introduced into the quartz tube 703 through the gas introduction passage 703a. In the quartz tube 703, the substrate is opposed to the substrate 701 supported by the quartz table 702.701A shower plate 705 having a large number of minute holes for uniformly blowing nitrogen gas onto the surface is provided. Outside the quartz tube 703, heaters 706 for heating the nitrogen gas introduced into the quartz tube 703 are provided on each of the side part and the upper part. A heater 706 provided on the upper part of the quartz tube 703 is provided as a main heater for heating nitrogen gas for performing heat treatment on the substrate 701. A heater 706 provided on a side portion of the quartz tube 703 includes: This is provided to keep the temperature in the substrate 701 uniform by preventing heat from escaping to the outside.
[0113]
In this rapid thermal annealing apparatus, the nitrogen gas introduced from the gas introduction passage 703a is heated in the quartz tube 703, and the heated nitrogen gas is directed from the minute holes formed in the shower plate 705 toward the surface of the substrate 701. And evenly sprayed. The substrate 701 supported by the quartz table 702 is moved above the quartz tube 703 as indicated by an arrow 704, and is held at a position where the distance between the substrate 701 and the shower plate 705 is about 1 cm. The raising / lowering speed of the substrate 701 is controlled by adjusting the raising / lowering speed of the quartz table 702.
[0114]
By using the high-speed thermal annealing apparatus configured as described above, the substrate 701 is heat-treated, whereby the temperature distribution in the substrate 701 at the time of temperature rise and fall can be kept substantially constant, and a large glass having a metric size. A stable heat treatment without cracking or warping can be realized for the substrate. In addition, when a large substrate is heat-treated, the temperature distribution in the substrate becomes extremely good, and good temperature uniformity equivalent to that when a furnace is used can be ensured. Furthermore, when this rapid thermal annealing apparatus is used, the temperature of the substrate rises and the temperature cannot be controlled over the entire period of lamp irradiation in the conventional lamp type annealing apparatus. The apparatus can perform stable heat treatment at a constant treatment temperature with a set temperature profile.
[0115]
  The rapid thermal annealing apparatus shown in FIG. 7 uses a single-wafer method that sequentially processes a single substrate. However, a multi-tube that simultaneously processes a plurality of substrates by connecting the quartz tubes having the above configuration in a cluster shape. By creating a chamber, a thermal annealing device with extremely high processing capacity can be reduced in size.FootprintCan be realized.
[0116]
In the method for manufacturing a semiconductor device according to the present invention, the amorphous silicon film provided on the crystalline silicon semiconductor film serving as the active region of the semiconductor device is unnecessary after gettering the catalytic element by the second heat treatment. Need to be removed. When the amorphous silicon film is removed, it is necessary to remove only the upper amorphous silicon film while leaving the crystalline silicon film serving as the lower active region.
[0117]
Therefore, in order to remove only the upper amorphous silicon film, an etching process having an etching selectivity of almost 100% between the lower crystalline silicon film and the upper amorphous silicon film is performed. In practice, however, the selective etching process is impossible because the upper amorphous silicon film and the lower crystalline silicon film are similar silicon-based materials.
[0118]
For this reason, in the method of manufacturing a semiconductor device of the present invention, a barrier thin film serving as an etching stopper when removing the amorphous silicon film is provided between the crystalline silicon film serving as the active region and the amorphous silicon film. It is effective to provide it. The barrier thin film must have a sufficient etching selectivity as an etching stopper when removing the amorphous silicon film. In the present invention, the second thin film for gettering the catalytic element is used. When performing the heat treatment, the catalytic element contained in the lower crystalline silicon film must be moved to the upper amorphous silicon film through the barrier thin film. It is necessary to use one that does not hinder gettering. Therefore, it is desirable to use a silicon oxide film having a thickness of 50 mm or less as the barrier thin film provided between the crystalline silicon film and the amorphous silicon film. If such a film is used, it has sufficient etching selectivity with respect to the amorphous silicon film, and in the second heat treatment, a catalytic element from the crystalline silicon film to the amorphous silicon film. Does not interfere with gettering. On the other hand, if the thickness of the silicon oxide film is greater than 50 mm, the catalytic element is not sufficiently gettered from the crystalline silicon film to the amorphous silicon film, and a high gettering effect cannot be obtained.
[0119]
Further, in the method for manufacturing a semiconductor device of the present invention, the crystallinity of the crystalline silicon film whose crystallization is promoted by the introduction of the catalytic element is further improved, and the performance of the semiconductor device, particularly the current driving capability is improved. As a method, it is effective to add a step of irradiating laser light to a crystalline silicon film whose crystallization has been promoted by introducing a catalytic element. The crystalline silicon film formed by the usual solid phase growth method has a twin crystal structure, so the inside of the crystal grains remains as twin defects even after intense light irradiation, but crystallization is promoted by the introduction of catalytic elements. When the crystallized silicon semiconductor film is irradiated with laser light, the crystalline silicon film crystallized by introducing a catalytic element is formed of columnar crystals, and the inside is in a single crystal state. When the grain boundary part is processed by the irradiation, the grain boundary part and minute residual amorphous region (uncrystallized region) are concentrated due to the difference in melting point between the crystalline silicon film and the amorphous silicon film. As a result, a high-quality crystalline silicon film close to a single crystal state is obtained over the entire surface of the substrate. The crystalline silicon film thus obtained is very effective from the viewpoint of crystallinity. In addition, since this laser light irradiation is originally performed on a silicon film having crystallinity, unlike the method of crystallizing an amorphous silicon film by direct laser irradiation, there is no variation in the laser light irradiation. It is greatly relaxed and there is no problem with uniformity.
[0120]
When a crystalline silicon film obtained by solid phase crystallization by introducing a catalytic element is irradiated with laser light, the presence form of the catalytic element changes. Specifically, the change in the existence form of the catalytic element is aggregation / reaggregation as silicide. The gettering process for removing the catalytic element from the crystalline silicon film serving as the active region is ideal gettering if the crystalline state of the crystalline silicon film constituting the active region is completely solidified. It is desirable because it can. In other words, when gettering of the catalytic element is followed by laser light irradiation to promote crystallinity, after the gettering, the catalyst element remaining in the crystalline silicon film and solid-solved is regenerated. Aggregation and silicidation may cause an electrical adverse effect on the semiconductor element. Therefore, in the present invention, the step of performing such laser light irradiation treatment is performed before the step of providing the amorphous silicon film on the crystalline silicon film to be the active region, that is, the catalytic element is an amorphous silicon film. It is desirable to do this before gettering.
[0121]
  Further, in the method for manufacturing a semiconductor device of the present invention, the kind of catalytic element that promotes crystallization of the amorphous silicon film is one of Ni, Co, Fe, Pd, Pt, Cu, Au, or the like, or these Multiple types of elements selected from can be used,theseWhen used as a catalytic element, crystallization can be promoted in a small amount.
[0122]
These catalytic elements do not act alone, but combine with the silicon atoms of the amorphous silicon film to promote crystal growth by silicidation. Therefore, the lattice constant in the silicide compound of the catalytic element is the lattice constant of single crystal silicon. It is preferable that Ni is diatomic Si and NiSi which is a silicide compound.₂Form. NiSi₂Has a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Furthermore, NiSi has a crystal structure with a diamond structure having a lattice constant of 5.430Å.₂Has a lattice constant of 5.406Å, which is closest to the lattice constant of silicon. Therefore, NiSi₂Is the most excellent template for crystallization of an amorphous silicon film, and crystallization of the amorphous silicon film is most promoted, so Ni is suitable as a catalyst element.
[0123]
A semiconductor device obtained by using the method for manufacturing a semiconductor device according to the present invention is a semiconductor device having a crystalline silicon film formed on a substrate having an insulating surface as an active region, and is used for this active region. The crystalline silicon film is formed by introducing a catalytic element that promotes crystallization into an amorphous silicon film formed on an insulating surface and heating the amorphous silicon film. This is obtained by gettering a catalytic element by heat treatment to an amorphous silicon film containing rare gases formed on the film. In the crystalline silicon film serving as the active region, the catalytic element is dissolved in the crystalline silicon lattice over the entire region, and the catalytic element is uniformly distributed over the entire active region. It is characterized by that. In other words, in this semiconductor device, the catalytic element is in a solid solution between the lattices of the silicon film and is uniformly distributed over the channel region and the source / drain regions.
[0124]
Such a feature can be obtained only by the semiconductor device of the present invention. A semiconductor device having such characteristics is a semiconductor device in which adverse effects such as an increase in off-current and deterioration in reliability due to a catalytic element do not occur. By containing the catalytic element in a crystalline silicon film in a solid solution between silicon lattices, it can maintain a better crystalline state than a conventional semiconductor device fabricated without using a conventional catalytic element. And high current drive capability can be obtained.
[0125]
The concentration of the catalytic element uniformly distributed over the entire active region of such a semiconductor device is 1 × 10¹⁵~ 1x10¹⁷atoms / cm^ThreeIt is preferable to be within the range. The concentration of the catalytic element in the active region is 1 × 10¹⁷atoms / cm^ThreeBy making the following, no adverse effect of the catalytic element on the characteristics of the semiconductor element is observed. Conversely, when a catalytic element is introduced to crystallize an amorphous silicon semiconductor, 1 × 10¹⁵atoms / cm^ThreeThe catalyst element at a concentration that minimizes the residual amount remains in the active region and cannot be reduced to a concentration lower than this.
[0126]
Further, when the catalyst element remains at a concentration within the above range, the catalyst element is combined with crystal defects, dangling bonds, and the like, and the trap density is reduced. Therefore, the semiconductor device of the present invention has a higher current driving capability than that in which no catalytic element is present. In this case, if the catalytic element contained in the active region is Ni element, in addition to high crystallization action, even if it exists between the lattices of silicon crystals, it hardly causes interstitial distortion and is scattered to carriers. It is most desirable to use Ni because it does not cause a problem.
[0127]
Another feature of the semiconductor device of the present invention is that an element selected from a trace amount of rare gases is contained in the vicinity of the surface of the active region. This is because when an amorphous silicon film for gettering a catalytic element is formed on a crystalline silicon film, a rare gas is injected into a part of the surface of the lower crystalline silicon film. to cause. This is a structural feature of the semiconductor device obtained as a result of using the present invention.
[0128]
The surface concentration of the rare gas element contained in the vicinity of the surface of the crystalline silicon semiconductor film which becomes the active region of such a semiconductor device is 1 × 10^Ten~ 1x10¹²atoms / cm²It is desirable to be within the range. The element of the rare gas does not affect the electrical characteristics of the semiconductor device, but becomes a scattering center for the carrier, and the concentration of the element of the rare gas is 1 × 10.¹²atoms / cm²If it exceeds, current drive capability is reduced due to the inclusion of a rare gas element. Further, the gettering of the catalytic element to the amorphous silicon film is not sufficiently performed, and the 5 × 10 5 is formed in the vicinity of the surface of the crystalline silicon film serving as an active region.¹⁶atoms / cm²There is a possibility that the catalyst element may remain beyond the upper limit of the appropriate concentration. Conversely, the concentration of rare gas elements is 1 × 10.^Tenatoms / cm²If it is below, it becomes the measurement lower limit in the total reflection fluorescent X-ray method that seems to have the highest accuracy in the current measurement technique, and it cannot be determined as a sufficient measurement value unless it is above this concentration.
[0129]
As the rare gas elements contained in the vicinity of the surface of the crystalline silicon film serving as the active region, the Ar element is desirable because it has the highest ability as a gettering element as described above.
[0130]
Hereinafter, specific examples using the method for manufacturing a semiconductor device of the present invention will be described.
[0131]
Example 1
In Embodiment 1, a process of manufacturing an N-type TFT used for a driver circuit, a pixel portion, and a thin film integrated circuit of an active matrix liquid crystal display device over a glass substrate will be described.
[0132]
1A to 1G are cross-sectional views illustrating a process for manufacturing the N-channel TFT of Example 1 for each process.
[0133]
In order to manufacture the N-channel TFT of Example 1, first, as shown in FIG. 1A, in order to prevent impurities from diffusing from the glass substrate 101 in a later step, the N channel TFT is formed on the glass substrate 101. For example, the base film 102 made of silicon oxide having a film thickness of about 300 to 500 nm is formed by plasma CVD. Next, an intrinsic (I-type) amorphous silicon semiconductor film (a-Si film) 103 having a thickness of 20 to 80 nm, for example, 40 nm is formed by plasma CVD. In Example 1, a non-annealed glass substrate of Corning Code 1737 having a size of 320 mm × 400 mm and a thickness of 0.7 mmt is used as the glass substrate 101, and a parallel plate type plasma CVD device is used as the plasma CVD device. The heating temperature is 300 ° C. and the material gas is SiH._FourGas and H₂Gas was used. The power density of the RF power supplied to the CVD electrode is 10 to 200 mW / cm.^ThreeRange, for example, 80 mW / cm^ThreeAs a result, an a-Si film 103 was formed.
[0134]
Next, a small amount of nickel 104 is added on the surface of the a-Si film 103. The nickel 104 was added by holding a solution in which the nickel 104 was dissolved on the a-Si film 103, and uniformly spreading the nickel solution on the substrate 101 with a spinner and drying it. In Example 1, nickel acetate was used as the solute, water was used as the solvent, and the nickel concentration in the solution was adjusted to 10 ppm. The concentration of the added nickel 104 is 7 × 10 4 by measurement using a total reflection X-ray fluorescence (TRXRF) method.¹²atoms / m^ThreeIt was about.
[0135]
Next, the a-Si film 103 to which a small amount of nickel 104 is added is subjected to heat treatment in an inert gas atmosphere, for example, a nitrogen gas atmosphere. In this heat treatment, during the temperature increase, first, the hydrogen contained in the a-Si film 103 was removed, and then the a-Si film 103 was crystallized under a higher temperature condition. Specifically, annealing treatment is performed for 1 to 2 hours as a temperature condition of 450 ° C. to 520 ° C. as a heat treatment in the first step, and a temperature condition of 520 ° C. to 570 ° C. as a heat treatment in the second step. The annealing process is performed for a processing time of 2 to 8 hours. In Example 1, after heat treatment for 1 hour under a temperature condition of 500 ° C., heat treatment for 4 hours was performed under a temperature condition of 550 ° C. In this heat treatment, nickel 104 added to the surface of the a-Si film 103 diffuses into the a-Si film 103 and silicidation occurs, and the a-Si film 103 is crystallized using the silicide as a nucleus. Progresses. As a result, as shown in FIG. 1B, the a-Si film 103 is crystallized to become a crystalline silicon semiconductor film 103.
[0136]
  Next, as shown in FIG. 1B, the crystalline silicon film 103 is recrystallized by irradiating the crystalline silicon film 103 with a laser beam 105 to improve its crystallinity. In this example, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used as the pulse laser beam at this time. The irradiation condition of the laser beam 105 is that the substrate 101 is heated to 200 to 450 ° C., for example, 400 ° C. during irradiation, and the energy density is 250 to 450 mJ / cm.^ThreeFor example, 350 mJ / cm^ThreeThe irradiation conditions were as follows. The beam size of the laser beam 105 is a long shape of 150 mm × 1 mm on the surface of the substrate 101.likeThe sample was formed into a beam spot, and sequentially scanned with a step width of 0.5 mm in a direction perpendicular to the longitudinal direction of the beam spot. As a result, a total of 20 times of irradiation with the laser beam 105 are performed on an arbitrary point of the crystalline silicon film 103. By repeatedly irradiating such laser beam 105, the crystalline silicon film 103 obtained by solid-phase crystallization has a crystal defect reduced by the melting and solidifying process by irradiation of the laser beam 105. It becomes a quality crystalline silicon film.
[0137]
Next, as shown in FIG. 1C, a silicon oxide film 106 is formed which becomes an etching stopper when the amorphous silicon film formed in a later step is removed by etching. The silicon oxide film 106 was formed by holding ozone water on the surface of the crystalline silicon film 103. The ozone water at this time desirably has an ozone concentration of 5 mg / L or more. In Example 1, the ozone water was 8 mg / L. The retention time of ozone water on the surface of the crystalline silicon film 103 was 1 minute. In this case, in order to form a denser silicon oxide film 106, it is desirable to remove the natural oxide film on the surface of the crystalline silicon film 103 before the treatment with ozone water. After cleaning with hydrofluoric acid to expose the surface of the active silicon film 103, treatment with ozone water was performed. The film thickness of the silicon oxide film 106 formed in this way was about 30 mm as a result of measurement by spectroscopic ellipso.
[0138]
Next, an Ar-containing a-Si film 107 is formed over the entire upper surface of the silicon oxide film 106 by plasma CVD. The film thickness of the a-Si film 107 is desirably in the range of 30 to 150 nm, and in this example 1, it was set to 50 nm.
[0139]
The a-Si film 107 was formed using a dual-bias dual-frequency plasma CVD apparatus shown in FIG. The deposition conditions for the a-Si film 107 at this time are as follows._FourGas and Ar gas are used as material gases, and the flow rate of each material gas is SiH._FourWas set to 100 sccm and Ar was set to 5000 sccm. Further, as the deposition pressure is lower, the content of Ar contained in the deposited a-Si film 107 tends to increase, and is supplied to the substrate side in the plasma CVD apparatus shown in FIG. The RF frequency is desirably set to be about 1/10 to 1/50 of the CVD electrode lower than the RF frequency supplied to the CVD electrode, and as the RF power supplied to the substrate side is larger, a Although the content of Ar contained in the Si film 107 is increased, it is preferably 1 to 5 times the RF power of the CVD electrode from the trade-off with the deterioration of the film thickness distribution. In Example 1, 0.7 Torr was set. Further, the RF frequency supplied to the CVD electrode of the plasma CVD apparatus shown in FIG. 5B is 27.1 MHz, the RF power is 100 W, the RF frequency supplied to the substrate side is 1.6 MHz, and the RF power is 300 W. did.
[0140]
The concentration of argon contained in the a-Si film 107 thus obtained is 1 × 10¹⁹~ 2x10^{twenty one}atoms / cm^ThreeWhen the film is formed under the film forming conditions of the first embodiment, the Ar concentration is 2 × 10.²⁰atoms / cm^ThreeConcentration of about.
[0141]
Next, as shown in FIG. 1D, heat treatment is performed in an inert gas atmosphere, for example, in a nitrogen atmosphere. The treatment temperature and treatment time of this heat treatment are preferably set to a treatment time of 30 minutes to 4 hours within a temperature range of 450 to 550 ° C. In Example 1, heat treatment was performed at a treatment temperature of 520 ° C. and a treatment time of 2 hours. As the rate of temperature increase, the temperature of the substrate 101 was increased from about 200 ° C. to 520 ° C. in 30 minutes (temperature increase rate: about 10 ° C./min), and after the treatment, the temperature increased from 520 ° C. to 200 ° C. for 30 minutes. The temperature dropped.
[0142]
In this heat treatment, no crystal nucleus is generated in the upper a-Si film 107 for gettering the catalytic element, and the amorphous state is maintained. For this reason, the gettering effect in which the strain and defect caused by argon are segregation sites is further promoted, and the gettering effect can be maximized.
[0143]
In Example 1, a non-annealed glass substrate of Corning code 1737 having a thickness of 320 mm × 400 mm and a thickness of 0.7 mmt is used as the glass substrate 101, but no warpage, deflection, cracking, or the like is caused by this heat treatment. It was. Furthermore, in the experiments by the present inventors, it has been confirmed that even a large glass substrate of another metric size can be used without being warped, bent, cracked, or the like by the above heat treatment.
[0144]
Further, in the first embodiment, as shown in FIG. 6, in a core tube having a cross-sectional shape substantially similar to the planar shape of the substrate 101, the substrate surface is directed in the core direction, and the core tube and the substrate are Heat treatment was performed using a furnace that was arranged to minimize the space between them. The core tube is configured in a cross section having a rectangular shape slightly larger than the glass substrate size of 320 mm × 400 mm used in the first embodiment, and the size of the space inside the core tube for storing the substrate is 400 mm. × 480mm. In order to carry out one heat treatment at the same time, the number of charged substrates in the furnace core tube is 20. Nitrogen gas is supplied from above the furnace core tube and diffused between the substrates, so that the substrates can be uniformly heated in the plane. In FIG. 6, the quartz tube (core tube) 603 is heated to 520 ° C. by a heater provided outside the quartz tube 603, and is preheated to 200 ° C. at the home position 607 below the tube 603. Then, as indicated by an arrow 604, the quartz boat 602 charged with the substrate 601 enters the tube 603 and the temperature is raised, and the entire quartz board 602 is completely inserted into the annealing zone 608. Then, the heat treatment of the substrate 601 is started. The temperature is lowered by lowering the quartz boat 602 to a home position 607 that is a residual heat zone. By using such an apparatus, the temperature raising / lowering speed can be increased, and the temperature distribution in the substrate at the time of temperature raising / lowering can be kept substantially constant, even for a large sized glass substrate, Stable processing without cracking or warping can be realized.
[0145]
By the heat treatment using the apparatus shown in FIG. 6, the a-Si film 107 containing argon is not crystallized at all, and the lattice distortion / defects in the a-Si film 107 generated by containing argon are caused by nickel. Nickel 104 in the lower crystalline silicon film 103 as a segregation trap is moved toward the upper a-Si film 107 as indicated by an arrow 108 in FIG. At this time, the nickel 104 moves through the thin silicon oxide film 106. However, in the first embodiment, since the silicon oxide film 106 is formed as a thin film, the nickel 104 does not hinder the movement. As a result, most of the nickel 104 contained in the crystalline silicon film 103 is transferred to the a-Si film 107 containing argon as the upper layer, and the nickel concentration is increased in the a-Si film 107. The nickel concentration contained in the lower crystalline silicon film 103 is significantly reduced, and the remaining nickel 104 is reduced, so that a high-quality crystalline silicon film 103 with a low nickel concentration can be obtained.
[0146]
In this way, when the heat treatment is performed at a heating temperature of 520 ° C. for a treatment time of 2 hours, the a-Si film containing the nickel concentration contained in the crystalline silicon film 103 and the upper layer argon as a gettering sink The nickel concentration contained in 107 is a segregation state in a thermal equilibrium state, and even if the treatment time is further increased, the nickel 104 is not gettered and is in a stable state. When the nickel concentration contained in the actual crystalline silicon film 103 at this time was measured by secondary ion mass spectrometry (SIMS), the nickel concentration was 1 × 10 5.¹⁶atoms / cm^ThreeIt was reduced to the extent. At this stage, the nickel 104 remaining in the crystalline silicon film 103 is not in a silicide state but exists in a solid solution state between silicon lattices, so that there is no problem in terms of electrical characteristics of the TFT.
[0147]
Next, gettering of the nickel 104 is performed, and the entire a-Si film 107 having a high nickel concentration is removed by etching. As the etching at this time, an etchant having a sufficient etching selectivity with respect to the silicon oxide film is required so that the silicon oxide film 106 under the a-Si film 107 sufficiently functions as an etching stopper. In Example 1, a strong alkaline solution such as a developer was used. Then, after removing the a-Si film 107 by etching, the silicon oxide film 106 is removed by etching. As an etchant at this time, a silicon oxide film 106 which is an upper layer with respect to a crystalline silicon film and a 1: 100 buffered hydrofluoric acid (BHF) having selectivity are used and removed by wet etching. When the surface of the crystalline silicon film 103 is measured by the total reflection fluorescent X-ray method in this state, it is about 1 × 10¹¹atoms / cm^ThreeOf the Ar element was confirmed. This indicates that some Ar element was implanted into the lower crystalline silicon film 103 when the a-Si film 107 containing argon was formed.
[0148]
Thereafter, unnecessary portions of the crystalline silicon film 103 are removed by etching, and element isolation is performed. Through such a process, as shown in FIG. 1E, an island-shaped crystalline silicon film 109 that becomes an active region (source / drain region, channel region) of the TFT is formed in a later step.
[0149]
Next, as shown in FIG. 1 (f), a silicon oxide which is a gate insulating film having a thickness of 20 to 150 nm, for example, 100 nm, is formed so as to cover the crystalline silicon film 109 serving as an active region. A film 110 is formed. In the first embodiment, the silicon oxide film 110 is formed by using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material and heating the substrate to 150 to 600 ° C., preferably 300 to 450 ° C. in the presence of oxygen. Then, it was decomposed and deposited by the RF plasma CVD method. Alternatively, TEOS is used as a raw material, and the substrate temperature is heated to 350 to 600 ° C., preferably 400 to 550 ° C. in the presence of ozone gas, and the silicon oxide film 110 is formed by a low pressure CVD method or an atmospheric pressure CVD method. Good. After the formation of the silicon oxide film 110, in order to improve the bulk characteristics of the silicon oxide film 110 itself and the interface characteristics between the crystalline silicon film 109 and the silicon oxide film 110, the temperature is 500 to 600 ° C. in an inert gas atmosphere. Thermal annealing was performed for 1 to 4 hours under temperature conditions.
[0150]
Subsequently, aluminum is formed into a film thickness of 400 to 800 nm, for example, 600 nm by sputtering, and this is patterned to form a gate electrode located at a predetermined portion on the crystalline silicon 109 film. 111 is formed. Next, the oxide layer 112 is formed on the surface of the gate electrode 111 by anodizing the surface of the gate electrode 111 made of aluminum. When the TFT fabricated in the first embodiment is a pixel TFT of an active matrix substrate, the gate electrode 111 is simultaneously formed on the same plane when forming the gate bus line. Become. The anodic oxidation of the gate electrode 111 can be obtained by first raising a voltage to 220 V in an ethylene glycol solution containing 1 to 5% tartaric acid and then maintaining that state for 1 hour. The thickness of the obtained oxide layer 112 was 200 nm. Note that since the oxide layer 112 has a thickness for forming an offset gate region in a subsequent ion doping step, the length of the offset gate region can be determined by the anodic oxidation step.
[0151]
Subsequently, phosphorus, which is an impurity, is implanted using an ion doping method. In this case, the gate electrode 111 and the oxide layer 112 formed on the silicon oxide film 110 serve as a mask, and phosphorus is not implanted into the crystalline silicon film 109 corresponding to a portion under the gate electrode 111. In the first embodiment, phosphine (PH) is used as a doping gas for doping phosphorus._ThreeAs the doping conditions, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10¹⁵~ 8x10¹⁵cm^-2For example, 2 × 10¹⁵cm^-2It was.
[0152]
By this step, the region of the crystalline silicon film 109 that is masked by the gate electrode 111 and is not implanted with phosphorus becomes the channel region 114 of the TFT later. The region of the crystalline silicon film 109 into which phosphorus is implanted without being masked by the gate electrode 111 will later become the source / drain regions 116 of the TFT.
[0153]
Next, as shown in FIG. 1 (f), annealing is performed by irradiating laser light 119, thereby activating the ion-implanted impurity and simultaneously reducing the crystallinity of the portion deteriorated by the impurity introduction step. Improve crystallinity.
[0154]
At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) is used as the laser beam 119, and the energy density is 150 to 400 mJ / cm.², Preferably 200 to 250 mJ / cm²It was. The sheet resistance of the N-type impurity region thus formed was 200 to 500Ω / □.
[0155]
Next, as shown in FIG. 1G, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed to form an interlayer insulating film 120. When a silicon oxide film is formed as the interlayer insulating film 120, a step coverage is formed by using TEOS as a raw material, a plasma CVD method in the presence of oxygen, a low pressure CVD method in the presence of ozone, or an atmospheric pressure CVD method. A good silicon oxide film having excellent properties is formed. When a silicon nitride film is formed as an interlayer insulating film, SiH_FourAnd NH_ThreeA silicon nitride film is formed by using a plasma CVD method using as a source gas. This silicon nitride film can reduce dangling bonds that deteriorate TFT characteristics by supplying hydrogen atoms to the interface between the crystalline silicon film 109 serving as an active region and the gate insulating film 110.
[0156]
Next, contact holes reaching these regions are formed in portions corresponding to the source / drain regions 116 on the crystalline silicon film 109 of the TFT of the interlayer insulating film 120. In the contact hole formed in the interlayer insulating film 120, an electrode / wiring 121 that is electrically connected to the source region and the drain region of the TFT is formed by a two-layer film of a metal material, for example, titanium nitride and aluminum. . The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Further, when this TFT is used for pixel switching of a liquid crystal display device, a pixel electrode made of a transparent conductive film such as ITO may be used for the drain electrode. Further, in this case, the other source electrode constitutes a source bus line, and an electric signal such as a video signal is supplied through this source bus line, and based on the gate signal of the gate bus line, A necessary charge is written in the pixel electrode.
[0157]
Finally, annealing is performed for 1 hour under a temperature condition of 350 ° C. in a water vapor atmosphere of 1 atm to complete a desired TFT 122. In order to protect the TFT 122, a protective film such as a silicon nitride film may be further provided.
[0158]
The TFT manufactured through the steps described above has a field effect mobility of 250 cm.²/ Vs and the threshold voltage were about 1.5 V, and very high performance was obtained. Such performance was not significantly different from the conventional TFT manufactured without using a catalytic element, and the production yield could be greatly improved. Further, in this TFT, there is no abnormal increase in leakage current at the time of turning off the TFT, which is frequently seen in TFTs manufactured by the conventional method, and a very low value of 1 pA or less per unit W can be stably achieved. Indicated.
[0159]
Furthermore, the TFT of Example 1 shows almost no deterioration in characteristics even after repeated tests, a bias, and a durability test by temperature stress, and is very reliable as compared with a TFT manufactured by a conventional method. Is expensive.
[0160]
When the active matrix substrate for liquid crystal display using the TFT of Example 1 was actually evaluated for lighting, the display unevenness was clearly smaller than that using the TFT manufactured by the conventional method, and the pixel defect due to the TFT leak. Therefore, a liquid crystal panel with a high contrast ratio and a high display quality could be obtained.
[0161]
Although the TFT manufacturing process of the first embodiment described above has been described for the pixel electrode of the active matrix substrate, the TFT of the first embodiment can be applied to a thin film integrated circuit or the like. In that case, a contact hole may be formed on the gate electrode and necessary wiring may be provided.
(Example 2)
In the second embodiment, a peripheral driving circuit of an active matrix type liquid crystal display device, a circuit having a CMOS structure in which an N channel TFT and a P channel TFT forming a general thin film integrated circuit are complementarily formed is a glass substrate. A process for manufacturing the above will be described.
[0162]
FIGS. 2A to 2G are cross-sectional views illustrating, for each process, a process for manufacturing a CMOS structure in which an N-channel TFT and a P-channel TFT of Example 2 are complementarily configured. .
[0163]
When manufacturing the CMOS structure of the second embodiment, first, as shown in FIG. 2A, in order to prevent impurities from diffusing from the glass substrate 201 in a later step, on the glass substrate 201, For example, the base film 202 made of silicon oxide having a thickness of about 300 to 500 nm is formed by plasma CVD. Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 203 having a thickness of 20 to 80 nm, for example, 40 nm is formed by plasma CVD. In the second embodiment, a non-annealed glass substrate of Corning Code 1737 having a size of 320 mm × 400 mm and a thickness of 0.7 mmt is used as the glass substrate 201, and a parallel plate type plasma CVD device is used as the plasma CVD device. The heating temperature is 300 ° C., and the material gas is SiH._FourGas and H₂Gas was used. The power density of the RF power supplied to the CVD electrode is 10 to 200 mW / cm.²Range, for example, 80 mW / cm²As a result, an a-Si film 203 was formed.
[0164]
Next, a small amount of nickel 204 is added on the surface of the a-Si film 203. The nickel 204 was added by holding a solution in which the nickel 204 was dissolved on the a-Si film 203, and uniformly spreading the nickel solution on the substrate 201 with a spinner and drying it. In Example 2, nickel acetate was used as the solute, ethanol was used as the solvent, and the nickel concentration in the solution was adjusted to 1 ppm. The concentration of the added nickel is 5 × 10 5 by measurement using a total reflection X-ray fluorescence analysis (TRXRF) method.¹²atoma / cm^ThreeIt was about.
[0165]
Next, the a-Si film 203 to which a small amount of nickel 204 is added is subjected to heat treatment in an inert gas atmosphere, for example, a nitrogen gas atmosphere. In this heat treatment, it is desirable to perform an annealing treatment for 2 to 8 hours under a temperature condition of 520 to 570 ° C. In Example 2, the heat treatment was carried out for 4 hours under a temperature condition of 550 ° C. In this heat treatment, nickel 204 added to the surface of the a-Si film 203 diffuses into the a-Si film 203 and silicidation occurs, and the a-Si film 203 is crystallized using the silicide as a nucleus. Progresses. However, the amount of nickel 204 added in the second embodiment is insufficient to crystallize the entire a-Si film 203, and a small amorphous region of about several μm is partially formed. Crystal growth stops in the remaining state. Further, when the heating temperature is 570 ° C. or lower, the silicon film itself does not grow, so that the uncrystallized region where the crystal growth does not reach remains in an amorphous state. As a result, the crystalline silicon film 203 obtained under the crystallization conditions of Example 2 is in a state where minute amorphous regions are mixed in the crystallization region.
[0166]
Next, as shown in FIG. 2B, the crystalline silicon film 203 is recrystallized by irradiating the crystalline silicon film 203 with a laser beam 205 to improve its crystallinity. In this example, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used as the laser light at this time. The irradiation condition of the laser beam 205 is that the substrate 201 is heated to 200 to 450 ° C., for example, 400 ° C. at the time of irradiation, and the energy density is 200 to 450 mJ / cm.²For example, 350 mJ / cm²The irradiation conditions were as follows. The beam size of the laser beam 205 is formed into a beam spot having a long shape of 150 mm × 1 mm on the surface of the substrate 201, and 0.05 mm in a direction perpendicular to the long direction of the beam spot. Were sequentially scanned at the step width. As a result, a total of 20 times of irradiation with the laser beam 205 are performed on an arbitrary point of the crystalline silicon film 203. By repeatedly irradiating such laser light 205, the amorphous region remaining in the silicon film is preferentially melted, and only the good crystal component of the crystallized region is reflected, and the entire film is crystallized. It becomes.
[0167]
Next, as shown in FIG. 2C, when the amorphous silicon semiconductor film (a-Si film) 207 formed in a later step is removed by etching, a silicon oxide film 206 serving as an etching stopper is removed. The crystalline silicon film 203 is formed by thin film oxidation. The silicon oxide film 206 was formed by irradiating the surface of the crystalline silicon film 203 with excimer UV light. The treatment time by irradiating this excimer UV light was 1 minute. The film thickness of the silicon oxide film 206 formed in this way was about 30 mm as a result of measurement by spectroscopic ellipso.
[0168]
Next, as illustrated in FIG. 2C, an a-Si film 207 containing Ar is formed by plasma CVD so as to cover the entire surface of the silicon oxide film 206. In the second embodiment, as shown in FIG. 5 (b), a parallel plate type, a dual bias dual frequency system that can apply another bias (RF power) to the substrate side in addition to the CVD electrode is used. The a-Si film 207 was formed using a plasma CVD apparatus. Further, in the second embodiment, the a-Si film 207 is formed to be a two-layer film having different argon concentrations. Since the formation of such a two-layer film was performed continuously in the same CVD chamber without being exposed to the atmosphere, there is no difference between the case of forming a single-layer film and the ease of manufacturing.
[0169]
When such an a-Si film 207 is formed as a two-layer film, the lower layer portion is turned off or has a small value in the RF power applied to the substrate side of the plasma CVD apparatus, and the upper layer portion is formed. In addition, the RF power applied to the substrate side is turned on or set to a value larger than that when the lower layer is formed. Thus, when the RF power applied to the substrate side is formed in the upper layer and the lower layer, the lower layer film formation and the upper layer film formation can be performed continuously by setting different outputs. It is possible to easily obtain a-Si films 207 having different argon contents.
[0170]
In the two-layer a-Si films 207 having different argon contents formed in this way, the lower layer portion having a low argon concentration is provided to reduce the injection of argon into the crystalline silicon film 203. The upper layer portion having a high argon concentration mainly acts to getter the catalytic element.
[0171]
In the second embodiment, in order to form the a-Si film 207, the heating temperature of the substrate 201 is set to 300 ° C., and the material gas is SiH._FourGas and Ar gas are used, and each gas flow rate is changed to SiH._FourWas set to 100 sccm and Ar was set to 5000 sccm. The RF frequency of the RF power supplied to the CVD electrode is 27.12 MHz, the RF frequency of the RF power supplied to the substrate side is 1.6 MHz, and the RF power supplied to the CVD electrode is constant at 100 W, The RF power supplied to the substrate side was off (0 W) at the initial stage of film formation, and 300 W was applied during the film formation. The lower layer with a low argon concentration formed when the RF power on the substrate side was turned off had a thickness of about 10 to 30 nm, and the upper layer with a high argon concentration was formed with a thickness of 30 to 100 nm. The argon concentration contained in the a-Si film 207 thus obtained is 7 × 10 5 in the lower layer.¹⁶atoms / cm^Three2x10 in the upper layer²⁰atoms / cm^ThreeIt was about.
[0172]
  next, NoHeat treatment is performed under an active gas atmosphere, for example, under a nitrogen gas atmosphere. The treatment temperature and treatment time for this heat treatment are preferably set to a treatment time of 10 seconds to 10 minutes within a temperature range of 600 to 750 ° C. In Example 2, heat treatment was performed at a treatment temperature of 650 ° C. and a treatment time of 3 minutes. As the rate of temperature increase, the temperature is raised from 650 ° C. to 650 ° C. in 2 minutes (temperature increase rate: 125 ° C./min) from the state where the substrate was preheated to 400 ° C. The temperature dropped.
[0173]
In this heat treatment, the a-Si film 207 for gettering the catalytic element does not generate crystal nuclei and is maintained in an amorphous state. For this reason, the gettering effect in which the strain and defect caused by argon are segregation sites is further promoted, and the gettering effect can be maximized.
[0174]
In Example 2, a non-annealed glass substrate of Corning code 1737 having a size of 320 mm × 400 mm and a thickness of 0.7 mmt is used as the glass substrate 201, but warpage, deflection, cracks, etc. are generated by this heat treatment. I did not. Further, the inventors of the present application have confirmed that other large sized glass substrates can be used without warping, bending, cracking, or the like due to the above heat treatment.
[0175]
In Example 2, the heat treatment was performed using a single-wafer type rapid thermal annealing apparatus that uniformly sprays a high-temperature gas onto the surface of the substrate as shown in FIG.
[0176]
The substrate 701 to be heat-treated is set at a position below the apparatus by the protrusion 702b of the quartz table 702, and preheats to about 400 ° C. at this position. Inside the quartz tube 703, high-temperature nitrogen gas introduced from the gas introduction passage 707 and heated to the processing temperature by the heater 706 is blown out from the shower plate 705 toward the surface of the substrate 701 along the arrow 708. The Then, the quartz table 702 on which the substrate 701 is set is moved upward as indicated by an arrow 704 so that the distance between the substrate 701 and the shower plate 705 blowing out high-temperature nitrogen gas is 10 mm. The temperature is moved to the vicinity of the temperature. Then, the substrate 701 is held at this position, and a rapid thermal annealing process is performed with a high-temperature nitrogen gas blown out from the shower plate 705.
[0177]
In this high-speed thermal annealing apparatus, the temperature rising / falling temperature of the substrate 701 is controlled by the lifting / lowering speed of the quartz table 702 on which the substrate 701 is set. Therefore, a high temperature rising / falling speed comparable to lamp annealing can be realized. At the same time, the temperature distribution in the substrate 701 at the time of raising and lowering temperature can be kept almost constant, and a stable heat treatment without cracking, warping, etc. can be performed even on a large sized glass substrate.
[0178]
The a-Si film 207 containing argon is not crystallized by the thermal annealing process using the above rapid thermal annealing apparatus, and the lattice distortion and defects in the a-Si film 207 due to containing argon are nickel. As a segregation trap, nickel 204 contained in the lower crystalline silicon film 203 is drawn upward as indicated by an arrow 208 in FIG. At this time, the nickel 204 passes through the thin silicon oxide film 206 and moves to the upper a-Si film 207. However, in the second embodiment, since the silicon oxide film 206 is formed into a thin film, the nickel 204 It will not hinder the movement. As a result, most of the nickel contained in the crystalline silicon film 207 is transferred to the a-Si film 207 containing argon in the upper layer, and in this a-Si film 207, the nickel concentration increases and the lower layer The nickel concentration contained in the crystalline silicon film 207 is greatly reduced, and the remaining nickel is reduced, so that a high-quality crystalline silicon semiconductor film having a low nickel concentration can be obtained.
[0179]
In this way, the nickel concentration contained in the crystalline silicon film 203 and the a-Si film 207 containing argon as an upper layer as a gettering sink are included by rapid thermal annealing for 3 minutes under a heating condition of 650 ° C. The nickel concentration is a segregation state in a thermal equilibrium state, and even if the treatment time is further increased, nickel is not gettered and is in a stable state. When the nickel concentration contained in the actual crystalline silicon film 203 at this time was measured by secondary ion mass spectrometry (SIMS), the nickel concentration was 7 × 10.¹⁵atoms / cm^ThreeIt was reduced to the extent. At this stage, the nickel remaining in the crystalline silicon film 203 is not in a silicide state but exists in a solid solution state between silicon lattices, so that there is no problem in the electrical characteristics of the TFT.
[0180]
Next, the nickel 204 is gettered, and the entire a-Si film 207 having a high nickel concentration is removed by etching. As the etching at this time, an etchant having a sufficient etching selectivity with respect to the silicon oxide film 206 is required so that the silicon oxide film 206 under the a-Si film 207 sufficiently functions as an etching stopper. In Example 2, a strong alkaline solution such as a developer was used. Then, after removing the a-Si film 207 by etching, the silicon oxide film 206 is removed by etching. As an etchant at this time, a silicon oxide 206 film as an upper layer with respect to the crystalline silicon film 203 and a 1: 100 buffered hydrofluoric acid (BHF) having selectivity were used and removed by wet etching.
[0181]
Thereafter, unnecessary portions of the crystalline silicon film 203 are removed by etching, and element isolation is performed. Through these steps, as shown in FIG. 2D, island-like crystalline silicon semiconductor films 209n and 209p that become active regions (source / drain regions, channel regions) of the TFTs after the subsequent steps are formed. It is formed.
[0182]
Next, as shown in FIG. 2E, the gate insulating film is formed to a thickness of 20 to 150 nm, for example, 100 nm so as to cover the crystalline silicon films 209n and 209p serving as active regions. A silicon oxide film 210 is formed. In the second embodiment, the silicon oxide film 210 is formed by using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material and heating the substrate to 150 to 600 ° C., preferably 300 to 450 ° C. in the presence of oxygen. Then, it was decomposed and deposited by the RF plasma CVD method.
[0183]
Subsequently, a refractory metal is deposited by a sputtering method and patterned to form gate electrodes 211n and 211p located at predetermined portions on the crystalline silicon films 209n and 209p, respectively. As the refractory metal, tantalum (Ta), molybdenum (Mo), or tungsten (W) is preferably used. In Example 2, tantalum to which a small amount of nitrogen was added was used, and the thickness was set to 300 to 600 nm, for example, 450 nm.
[0184]
Next, phosphorus, which is an impurity, is implanted using an ion doping method. In this case, so-called through doping, which is performed through the gate insulating film 210, was applied. In this case, the gate electrodes 211n and 211p formed on the silicon oxide film 210 serve as a mask, and phosphorus is not implanted into the crystalline silicon films 209n and 209p corresponding to the portions under the gate electrodes 211n and 211p. In the second embodiment, phosphine (PH) is used as a doping gas for doping phosphorus._ThreeAs the doping conditions, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 2 × 10¹⁵~ 8x10¹⁵cm^-2It was.
[0185]
By this step, the regions of the crystalline silicon films 209n and 209p that are masked by the gate electrodes 211n and 211p and are not implanted with phosphorus become channel regions of the TFT later. The regions of the crystalline silicon films 209n and 209p into which phosphorus is implanted without being masked by the gate electrodes 211n and 211p will later become source / drain regions of the TFT. However, in the P-channel TFT, the region to be the source / drain region is an N-type impurity region at this stage by doping with phosphorus.
[0186]
Next, as shown in FIG. 2F, a photoresist 217 covering the gate insulating film 210 and the gate electrode 211n on the crystalline silicon film 209n to be the N-channel TFT 222 is provided by a photolithography process, and P A mask for selective doping to prevent implantation of a type impurity.
[0187]
In this state, boron is implanted by an ion doping method. In the present embodiment 2, diborane (B₂H₆1 × 10¹⁶~ 5x10¹⁶cm^-2For example, 2 × 10¹⁶cm^-2The doping was performed by applying an acceleration voltage of 40 to 80 kV, for example, 65 kV, at a high dose.
[0188]
In this step, boron is not implanted into the crystalline silicon film 209p below the gate electrode 212p because the gate electrode 212p serves as a mask. Further, boron is doped through the gate insulating film 210 into the crystalline silicon film 209p in the region where the gate electrode 212p is not formed. As a result, the source region and the drain region, which are N-type by implanting phosphorus, which is an N-type impurity in the previous step, are so-called counter-doping as a result of so-called counter doping. The phosphorus, which is an N-type impurity doped in, is canceled and the characteristics are inverted to become P-type impurity regions 215p and 216p. In this manner, the N-channel TFT 222 and the P-channel TFT 223 can be formed on the same substrate.
[0189]
Next, after removing the photoresist 217 provided as a mask for selective doping, high-speed heat for several minutes in the temperature range of 600 to 650 ° C. in an inert gas atmosphere, for example, a nitrogen gas atmosphere. Annealing treatment was performed. In Example 2, the rapid thermal annealing apparatus shown in FIG. 7 was used. By this treatment, the source / drain regions of the N-type and P-type TFTs are activated. The sheet resistance value of the N-type impurity region obtained by this treatment is 0.4 to 0.8 kΩ / □. The sheet resistance values of the P-type impurity regions 215p and 216p were 1 to 2 kΩ / □. In addition, the baking treatment of the gate insulating film 211 is performed at the same time, so that the bulk characteristics of the gate insulating film itself and the interface characteristics between the crystalline silicon semiconductor film and the gate insulating film can be improved.
[0190]
Next, as shown in FIG. 2G, a silicon oxide film having a thickness of about 900 nm is formed by a plasma CVD method to form an interlayer insulating film 220. Then, contact holes reaching these regions are formed in portions corresponding to the source region and the drain region on the crystalline silicon film of the TFT of the interlayer insulating film 220. In this contact hole, an electrode / wiring 221 that is electrically connected to the source region and the drain region of the TFT is formed by a two-layer film of a metal material, for example, titanium nitride and aluminum.
[0191]
Finally, annealing is performed for 1 hour under a temperature condition of 350 ° C. in a hydrogen atmosphere of 1 atm to complete the N-channel TFT 222 and the P-channel TFT 223. Furthermore, if necessary, contact holes can also be provided on the gate electrodes 211n and 211p of the N-type and P-type TFTs to connect the wirings. Further, in order to protect the TFT, a protective film such as silicon nitride may be further provided on the TFT.
[0192]
In the CMOS structure circuit manufactured through the steps described above, the field effect mobility of each TFT is 250 to 300 cm for an N-type TFT.²/ Vs, 100-130cm with P-type TFT²A high value of / Vs was obtained, and the threshold voltage was about 1 V for the N-type TFT and about −2 V for the P-type TFT, and very good characteristics were obtained. In addition, there is no abnormal increase in leakage current that frequently occurs in TFTs manufactured by conventional methods, and the leakage current itself is stable at a very low value of 1 pA or less per unit W. Indicated. This value has no difference even when compared with a conventional TFT manufactured without using a catalyst element, and the manufacturing yield can be greatly improved.
[0193]
Further, the TFT of this Example 2 shows almost no deterioration in characteristics even after repeated tests, bias and temperature durability tests, and is very reliable as compared with a TFT manufactured by a conventional method. And stable circuit characteristics.
[0194]
The two embodiments based on the present invention have been specifically described above. However, the present invention is not limited to the two embodiments, and various modifications based on the technical idea of the present invention are possible. .
[0195]
For example, in the above two embodiments, when the a-Si film containing argon is formed by the plasma CVD method, the dual frequency method in which RF power is also applied to the substrate side is used. It is also possible to forcibly introduce argon ions into the a-Si film by applying power and applying DC power to the substrate side.
[0196]
  Moreover, in said Example 2, the two-layer film structure from which the density | concentration of argon containing the a-Si film containing argon differs from each otherWhenHowever, it may be formed as a multilayer film of three or more layers, or may be a film in which the argon concentration is continuously different along the film thickness direction.
[0197]
Furthermore, in the above two embodiments, argon is used as the gettering element, but the same effect can be obtained even if krypton, xenon, or the like is used.
[0198]
In addition, as the heat treatment for moving nickel to the upper a-Si film serving as a gettering sink, the method of using a core tube having an inner periphery substantially similar to the outer shape of the substrate has been shown in the first embodiment. The same treatment can be performed using a resistance heating furnace (furnace furnace) having a normal shape. In the second embodiment, the rapid thermal annealing process is performed by blowing high-temperature nitrogen gas. However, the same process can be performed by performing an annealing process using a general lamp method.
[0199]
In addition, as a method for introducing nickel, a method in which a solution in which a nickel salt is dissolved is applied to the surface of the amorphous silicon film is used, but before the amorphous silicon film is formed, the surface of the base film is used. Alternatively, nickel may be introduced and crystal growth may be performed by diffusing nickel from the lower layer side of the amorphous silicon film. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film.
[0200]
As a method for introducing nickel, various methods can be used in addition to the method of the above embodiment. For example, SOG (spin on glass) material is used as a solvent for dissolving nickel salt,₂A method of diffusing from a film, a sputtering method, a vapor deposition method, a method of forming a thin film by a plating method, a method of directly introducing by an ion doping method, or the like can be used.
[0201]
Furthermore, the same effect can be obtained even if nickel, cobalt, iron, palladium, platinum, copper, gold, or the like is used as a catalyst element for promoting crystallization.
[0202]
As an etching stopper for removing the a-Si film serving as a gettering sink, various films such as a silicon nitride film as well as the silicon oxide film described in the above embodiment can be used. As for the method for forming the silicon oxide film, methods other than the thin film oxidation method such as ozone water treatment and excimer UV treatment described in this embodiment, for example, thin film formation by CVD, oxygen plasma treatment, thermal oxidation method, sulfuric acid An oxidation method or the like may be used.
[0203]
In the above embodiment, as a method for further improving the crystallinity of the crystalline silicon film crystallized with nickel, a heating method by irradiation with excimer laser light, which is a pulse laser, is used. The same processing can be performed by irradiating other laser light such as irradiation.
[0204]
In addition to the active matrix substrate for liquid crystal display, the device to which the semiconductor device of the present invention is applied includes, for example, a contact type image sensor, a driver built-in thermal head, a driver with an organic EL as a light emitting element. Even when applied to an optical writing element or display element of a type, a three-dimensional IC, etc., these elements can be realized at high speed and high performance corresponding to the degree of disclosure.
[0205]
Furthermore, the present invention is not limited to the MOS transistors described in the above embodiments, but can be applied to a wide variety of semiconductor processes such as bipolar transistors and electrostatic induction transistors using crystalline semiconductors.
[0206]
【The invention's effect】
The semiconductor device and the manufacturing method thereof according to the present invention are obtained by applying a rare gas to the upper surface of a crystalline silicon film crystallized by heat-treating an amorphous silicon film into which a small amount of a catalytic element for promoting crystallization is introduced. A crystalline silicon film that becomes an active region of a semiconductor device is formed by forming an amorphous silicon film containing the selected element and gettering a catalytic element to the amorphous silicon film by heat treatment. ing. The crystalline silicon film thus formed is in a state where the catalytic element is greatly reduced by gettering and is in solid solution between the lattices of the silicon film over the entire active region. Therefore, a semiconductor device using this crystalline silicon film as an active region becomes a stable high-performance semiconductor device with little variation in characteristics such as an abnormal increase in leakage current.
[0207]
Moreover, such a high-performance semiconductor device with a high degree of integration can be manufactured by a simple manufacturing process, the yield rate can be greatly improved in the manufacturing process, and the cost can be reduced. In particular, when the semiconductor device of the present invention is applied to a liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved, and the high performance and high integration required for the TFT constituting the peripheral drive circuit section The driver monolithic type active matrix substrate that constitutes the active matrix portion and the peripheral drive circuit portion on the same substrate can be realized, and the module can be made compact, high performance, and low in cost.
[Brief description of the drawings]
FIGS. 1A to 1G are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Example 1 of the present invention for each step.
FIGS. 2A to 2G are cross-sectional views illustrating, for each step, a method for manufacturing a semiconductor device according to Example 2 of the present invention.
FIG. 3 shows the concentration of Ar contained in an amorphous silicon film (horizontal axis) and the catalytic element (Ni) remaining in the crystalline silicon film after the second heat treatment for gettering the catalytic element. It is a graph which shows the relationship with a density | concentration (vertical axis).
FIG. 4 shows the result of determining the relationship with the Ar concentration contained in the amorphous silicon semiconductor film obtained when 100 W RF power is applied to the CVD electrode and the RF power applied to the substrate side is displaced. It is a graph to represent.
FIGS. 5A and 5B are schematic views showing an outline of a plasma CVD apparatus for forming an amorphous silicon film in the present invention, respectively.
6A to 6D are schematic views showing a heat treatment apparatus for performing a second heat treatment in the present invention, respectively.
FIG. 7 is a schematic view showing an outline of a rapid thermal annealing apparatus for performing a second heat treatment in the present invention.
[Explanation of symbols]
101, 201 glass substrate
102, 202 Base film
103, 203 Silicon film
104, 204 Nickel
105, 205 Laser light
106,206 Silicon oxide film
107, 207 a-Si film
108,208 Nickel gettering direction
109, 209n, 209p TFT active region (element region)
110, 210 Silicon oxide film
111, 211n, 211p gate electrode
112 Oxide layer
213 Phosphorus
114, 214n, 214p channel region
115, 215n, 215p source region
116, 216n, 216p drain region
217 photoresist
218 Boron
119 Laser light
120, 220 interlayer insulation film
121,221 Electrode / Wiring
122, 222 N-channel TFT
223 P-channel TFT

Claims (23)

Forming an amorphous silicon film on a substrate having an insulating surface, and introducing nickel as a catalytic element for promoting crystallization of the amorphous silicon film on the amorphous silicon film;
Performing a first heat treatment for crystallizing the amorphous silicon film to crystallize the amorphous silicon film into a crystalline silicon film;
Forming an amorphous silicon film containing an element selected from rare gases on the crystalline silicon film using a plasma CVD method;
A second heat treatment is performed to move nickel contained in the crystalline silicon film to the amorphous silicon film, and nickel contained in the crystalline silicon film is moved to the amorphous silicon film. A process of
Next, removing the amorphous silicon film and forming an active region with the crystalline silicon film;
Including
The step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the crystalline silicon film includes a silane gas and a gas containing an element selected from a rare gas. Is used as a source gas, and the amorphous silicon film is formed on the insulating substrate side in addition to the RF bias supplied from the CVD electrode disposed to face the insulating substrate. A method of manufacturing a semiconductor device, wherein a film is formed by a dual bias to which another RF bias different from the above is applied. Forming an amorphous silicon film on a substrate having an insulating surface, and introducing nickel as a catalytic element for promoting crystallization of the amorphous silicon film on the amorphous silicon film;
Performing a first heat treatment for crystallizing the amorphous silicon film to crystallize the amorphous silicon film into a crystalline silicon film;
On the crystalline silicon film, an amorphous silicon film containing an element selected from rare gases using a plasma CVD method is used, such that the concentration of the element selected from the rare gases changes with respect to the film thickness direction. Forming a film with a concentration distribution;
A second heat treatment is performed to move nickel contained in the crystalline silicon film to the amorphous silicon film, and nickel contained in the crystalline silicon film is moved to the amorphous silicon film. A process of
Next, removing the amorphous silicon film and forming an active region with the crystalline silicon film;
A method for manufacturing a semiconductor device, comprising: Forming an amorphous silicon film on a substrate having an insulating surface, and introducing nickel as a catalytic element for promoting crystallization of the amorphous silicon film on the amorphous silicon film;
Performing a first heat treatment for crystallizing the amorphous silicon film to crystallize the amorphous silicon film into a crystalline silicon film;
Forming an amorphous silicon film containing an element selected from rare gases on the crystalline silicon film using a plasma CVD method;
A second heat treatment is performed to move nickel contained in the crystalline silicon film to the amorphous silicon film, and nickel contained in the crystalline silicon film is moved to the amorphous silicon film. A process of
Next, removing the amorphous silicon film and forming an active region with the crystalline silicon film;
Including
The step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the crystalline silicon film includes a silane gas and a gas containing an element selected from a rare gas. Is used as a source gas, and the amorphous silicon film is a lower layer in which the concentration of an element selected from the rare gases is low by a bias supplied from a CVD electrode disposed to face the insulating substrate. After the film is formed, the concentration of the element selected from the rare gases is high by the dual bias in which another bias different from this bias is applied to the insulating substrate side in addition to the bias supplied from the CVD electrode. A method for manufacturing a semiconductor device, comprising forming an upper layer film.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the element selected from the rare gases is one or more of Ar, Kr, and Xe.   The method for manufacturing a semiconductor device according to claim 4, wherein Ar is included as an element selected from the rare gases. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of the element selected from the rare gases is in the range of 1 × 10 ¹⁹ to 2 × 10 ²¹ atoms / cm ³ . The concentration of elements selected from rare gases is, 1 × a 10 ²⁰ ~1 × 10 ²¹ in the range of atoms / cm ^3, The method of manufacturing a semiconductor device according to claim 6.   The step of forming an amorphous silicon film containing an element selected from a rare gas using a plasma CVD method on the crystalline silicon film includes a silane gas and a gas containing an element selected from a rare gas. Is used as a source gas, and the amorphous silicon film has a bias supplied to the insulating substrate side in addition to the bias supplied from the CVD electrode disposed to face the insulating substrate. The method of manufacturing a semiconductor device according to claim 2, wherein the film is formed by a dual bias to which another different bias is applied.   The step of forming an amorphous silicon film containing an element selected from the rare gases applies an RF bias to the CVD electrode, and applies another RF bias to the insulating substrate. The manufacturing method of the semiconductor device as described in any one of.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the RF bias applied to the insulating-side substrate has a frequency lower than a frequency of the RF bias supplied from the CVD electrode.   2. The semiconductor according to claim 1, wherein the amorphous silicon film containing an element selected from the rare gases has a concentration distribution such that the concentration of the element selected from the rare gases changes in the film thickness direction. Device manufacturing method.   The amorphous silicon film containing an element selected from the rare gases is formed such that the concentration of the element selected from the rare gases is high on the upper surface side and low on the lower surface side. The manufacturing method of the semiconductor device of description.   The amorphous silicon film containing an element selected from the rare gases is formed into a two-layer structure of a lower layer film having a low concentration of the element selected from the rare gases and an upper layer film having a high concentration of the element. A method of manufacturing a semiconductor device according to claim 12.   An amorphous silicon film containing an element selected from the rare gases forms the lower layer film only by a bias supplied from the CVD electrode, and in addition to the bias supplied from the CVD electrode on the lower layer film The method of manufacturing a semiconductor device according to claim 13, wherein the upper layer film is formed on the insulating substrate side by a dual bias to which another bias different from the bias is applied.   The method for manufacturing a semiconductor device according to claim 3, wherein the amorphous silicon film containing an element selected from the rare gases is continuously formed using the same chamber.   The step of moving the nickel contained in the crystalline silicon film to the amorphous silicon film containing an element selected from the rare gases by the second heat treatment includes the step of moving the nickel contained in the crystalline silicon film. The concentration and the concentration of nickel contained in the amorphous silicon film are performed under heating conditions of heating temperature and heating time so that at least a segregation state in a thermal equilibrium state is obtained. The manufacturing method of the semiconductor device in any one.   The step of transferring the nickel contained in the crystalline silicon film to the amorphous silicon film containing an element selected from the rare gases by the second heat treatment includes at least crystallization of the amorphous silicon film. The manufacturing method of the semiconductor device in any one of Claims 1-3 performed on the heating conditions made into heating temperature and heating time which do not.   4. The manufacturing of a semiconductor device according to claim 1, wherein the heating condition of the second heat treatment is a treatment time of 30 minutes to 4 hours with a temperature range of 450 to 550 ° C. as a heating temperature. Method.   4. The semiconductor device according to claim 1, wherein the second heat treatment is performed by a rapid thermal annealing treatment with a treatment time of 10 seconds to 10 minutes within a temperature range of 600 to 700 ° C. 5. Production method. The method of manufacturing a semiconductor device according to claim 19 , wherein the rapid thermal annealing treatment is performed by spraying an inert gas heated to a high temperature toward the surface of the insulating substrate.   A barrier thin film serving as an etching stopper when removing the amorphous silicon film is provided between the crystalline silicon film and an amorphous silicon film containing an element selected from the rare gases. The manufacturing method of the semiconductor device in any one of -3. The method of manufacturing a semiconductor device according to claim 21 , wherein the barrier thin film is a silicon oxide film formed to a thickness of 50 mm or less. Before performing the step of forming an amorphous silicon film containing an element selected from the rare gases,
4. The method for manufacturing a semiconductor device according to any one of 1 to 3, further comprising a step of irradiating the crystalline silicon film with laser light to improve the crystallinity.

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