JP4122551B2 - Control device for gaming machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device for a gaming machine, and relates to a technique for preventing unauthorized gaming.
[0002]
[Prior art]
In a gaming machine such as a pachinko machine or a slot machine machine, whether it is “winning” or “out of” is determined by a random value. The value of the random number matches the value of the counter (that is, the count value) and is changed within a predetermined range every predetermined period (for example, 4 milliseconds). That is, normally, the counter value is incremented by 1, and when the counter value is the upper limit value, the counter is cleared and circulated. For example, assuming that the predetermined range is 0 to 299, the counter value is incremented by 1 when the counter value is 0 to 298, and cleared to 0 when the counter value is 299. Therefore, the counter continues to be updated periodically from when the gaming machine is powered on (or reset).
[0003]
The count value is often used for symbol display of a symbol display provided in a gaming machine. That is, when a game ball wins at the starting port where the symbol variation starts, the count value when the winning is detected is read. Then, according to the read count value (hereinafter referred to as “read value”), the content of the symbol displayed on the symbol display device is controlled.
For example, it is assumed that only “7” is a winning in the predetermined range. If the read value is “7”, control is performed so that the content of the symbol displayed on the symbol display is stopped in a “winning” manner (specifically, a winning symbol such as “777”). Further, if the read value is a value other than “7”, the content of the symbol displayed on the symbol display device is controlled to stop in a “displacement” mode according to the value.
[0004]
Here, in the pachinko machine, the timing at which the game ball wins the start opening (hereinafter referred to as “winning timing”) is not uniform because the game ball behaves randomly due to many obstacle nails arranged on the game board surface. Therefore, even if the count value of the counter updated every predetermined period is read at the winning timing, the read value eventually becomes a random value.
However, since the counter is updated every predetermined period, the period from when a “winning” comes out until the next “winning” comes out is also constant. The period is equal to a period during which the count value makes a round of the predetermined range, and is hereinafter referred to as a “count period”. In the example of the predetermined range, when 300 values are updated every 4 milliseconds, the count cycle becomes 1.2 seconds. Therefore, if the game ball wins the starting opening 1.2 seconds after the reading value once becomes a winning value, the reading value at that time also becomes a winning value.
[0005]
By the way, there is a so-called “sensory sensation device” that generates signals such as vibrations and sounds at regular intervals. If the player turns on / off the launching device according to the signal generated by the sensor, the game ball can be fired at regular intervals.
Moreover, depending on the operation pattern of a member, a player may know the said fixed period irrespective of a body sensor. As an operation pattern of this member, there are, for example, a blinking pattern of a lamp provided on the game board surface, a sound effect emitted from a speaker, an operation pattern of an accessory, and the like. Further, the operation pattern of the members is generally operated at a timing unrelated to one cycle of the counter. However, if it operates in synchronism with one cycle of the counter due to a cause such as a design or manufacturing error, it becomes possible for the player to know the fixed cycle. If the player turns on / off the launching device according to the operation pattern of this member, the game ball can be fired at regular intervals.
However, as described above, since a number of obstacle nails are provided on the game board surface, the winning timing does not necessarily occur periodically.
[0006]
[Problems to be solved by the invention]
However, if the game ball is fired at every cycle of the counter (1.2 seconds in the above example), the winning timing can be generated periodically. Therefore, it is possible to increase the probability of “winning” when winning at the start opening. Therefore, it is possible to generate “hit” almost certainly if a game is played with a sensory device or the like. Such illegal games are intentionally aimed at “winning”, and are unfair and should not be allowed in consideration of general players who play for “winning” due to chance.
The present invention has been made in view of these points, and an object of the present invention is to provide a control device for a gaming machine that prevents unauthorized gaming by unauthorized means such as a sensory device.
[0007]
The present invention A CPU that controls the gaming machine, a counter that changes a count value within a predetermined range, and an input processing circuit that receives a winning signal output from the winning sensor and sends an operating signal to the CPU. In the control device of the gaming machine that switches the gaming state based on the count value read by the received CPU with reference to the counter, the input processing circuit operates on the CPU after being delayed in time after receiving the winning signal It is characterized by sending a signal. Here, the “winning sensor” is a sensor for detecting a game ball that wins or passes a specific area.
This way The operation signal sent from the input processing circuit to the CPU is delayed in time compared to the winning signal output from the winning sensor. That is, the timing of winning and the timing at which the CPU switches the gaming state are shifted. Since the timing for switching the gaming state is different from one cycle of the counter, unauthorized gaming can be prevented.
[0008]
In the present invention, The input processing circuit includes an oscillator, and a latch circuit that receives a pulse and a winning signal output from the oscillator and sends an operation signal when the pulse transits to a predetermined state. The latch circuit When the pulse output from the oscillator changes to a predetermined state, an operation signal is sent to the CPU. By making the timing at which the pulse transitions to a predetermined state differ from one cycle of the counter, the timing of “hit” cannot be matched. Since the player cannot know the timing at which this pulse makes a transition to a predetermined state, illegal games can be prevented.
[0009]
In the present invention, The oscillator is a self-excited oscillation circuit It may be configured. This way Although the self-excited oscillation circuit periodically outputs pulses, the interval between pulses cannot be obtained with high accuracy and becomes non-uniform. For this reason, the timing for referring to the count value of the counter is also non-uniform, and hence the timing for hitting is also non-uniform. Therefore, illegal games can be prevented more reliably.
[0010]
In the present invention, The oscillator has a different period for each gaming machine. It may oscillate. This way The oscillation period of the oscillator is different for each gaming machine Can be different . Therefore, even if it is possible to synchronize with the period of the oscillator of a certain gaming machine by an improper means such as a sensory device, it is not possible to synchronize with other gaming machines, and the possibility of being “winning” is extremely low. Therefore, fraudulent games can be minimized.
[0011]
In the present invention, Oscillators have different periods over time You may make it oscillate. This way The oscillation period of the oscillator changes with time. For this reason, even if the period based on the oscillator can be synchronized by a fraudulent means such as a sensory sensor at a certain time, it cannot be synchronized at a later time, and the possibility of being “winning” is extremely low. Therefore, illegal games can be prevented more reliably.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the present invention is applied to a pachinko machine that is one of gaming machines.
[0013]
[Embodiment 1]
First, a first embodiment for realizing signal delay processing in an input processing circuit will be described with reference to FIGS. Here, FIG. 1 shows a front view of the appearance of the pachinko machine. FIG. 2 is a block diagram showing the configuration of the control unit. FIG. 3 shows the configuration of the first input processing circuit. FIG. 4 is a flowchart showing the hit determination process. FIG. 5 is a time chart showing changes in the operation signal with respect to the winning signal.
[0014]
First, in FIG. 1, on the game board surface 12 of the pachinko machine 10, a composite device 14, a first type starting port 18, a grand prize winning port 20, and the like are appropriately arranged and provided. The composite device 14 is provided with a gate sensor 38, a normal symbol display 40, a special symbol display 42, and the like. The first type starting port 18 is one of the specific areas, and operates in the same manner as a normal winning port to pay out a prize ball (prize ball). On the other hand, the gate only detects the passage of the pachinko ball (game ball) by the gate sensor 38 and does not pay out the prize ball. The gate sensor 38 corresponds to a winning sensor.
The normal symbol display 40 displays normal symbols (for example, alphanumeric characters and symbols). This normal symbol starts to change when the pachinko ball passes the gate and then stops. The special symbol display 42 displays special symbols (for example, patterns, alphanumeric characters, symbols, etc.). The special symbol starts to change when the pachinko ball wins the first type starting port 18 and then stops.
[0015]
The first type starting port 18 is provided with a starting port sensor 34. The starting port sensor 34 corresponds to a winning sensor, and outputs a winning signal P2 when a pachinko ball winning in the first type starting port 18 is detected.
The special winning opening 20 is provided with a lid 20 a, which is opened and closed by a solenoid 32. The special winning opening 20 is provided with a V zone 20b as a special area. If the pachinko ball wins the V zone 20b at a certain time, the big hit gaming state can be continued within a certain limit (for example, 16 times).
Other than the game board surface 12, a lower plate 26 for temporarily storing a pachinko ball including a prize ball, a speaker 28 for producing sound effects and music, and whether or not the player's hand is touching the handle 22 are detected. A touch sensor 24, a firing motor 21 for operating the handle 22 to launch a pachinko ball, and a metal frame sensor 36 for detecting the opening of the glass frame 17 are provided. The speaker 28 is provided inside an upper plate 30 that is a tray for receiving a prize ball, and the touch sensor 24 and the metal frame sensor 36 are respectively provided at predetermined positions. Moreover, LED, a light bulb, etc. are used for the lamps 16 and are arrange | positioned in a suitable position according to the game content of the pachinko machine 10, etc.
[0016]
Next, the main controller 100 will be described with reference to FIG. The main control unit 100 includes a CPU (processor) 110, a ROM 102, a RAM 104, an input processing circuit 108, an output processing circuit 112, a display control circuit 114, a communication control circuit 116, and the like. The CPU 110 controls the pachinko machine 10 by executing a game control program recorded in the ROM 102. The game control program includes a program for realizing a hit determination process described later. The ROM 102 is an EPROM, but an EEPROM or a flash memory may be used. In addition to the counter 106, the RAM 104 stores various data or input / output signals. A DRAM is used as the RAM 104. SRAM, A nonvolatile memory such as a flash memory may be used. The counter 106 changes its count value within a predetermined range (for example, a value from 0 to 299).
[0017]
The input processing circuit 108 receives a winning signal P2 sent from the start port sensor 34 or the gate sensor 38. Then, the input processing circuit 108 delays a part or all of the winning signals P2 in terms of time, converts them into a data format that can be processed in the main control unit 100, and sends the operation signal P6 to the CPU 110 and the RAM 104 via the bus 118. Or send data.
Specifically, as shown in FIG. 3A, the input processing circuit 108 includes an oscillator 108a and a latch circuit 108b. The oscillator 108a periodically outputs a pulse signal P4. The latch circuit 108b receives the winning signal P2 sent from the start port sensor 34 or the gate sensor 38 and the pulse signal P4 outputted from the oscillator 108a, and the activation signal P6 when the pulse signal P4 transitions to a predetermined state. Is output.
[0018]
For example, as shown in FIG. 3B, the oscillator 108a includes a resistor R2, a capacitor C2, and a multivibrator 108c. The resistor R2 and the capacitor C2 are connected in series, the resistor R2 side is connected to the power supply Vcc, and the capacitor C2 side is connected to the ground. The multivibrator 108c has a connection point between the resistor R2 and the capacitor C2 and ground as inputs. The type of multivibrator 108c may be monostable, bistable, or non-stable. Here, the resistance value and the capacitance of the resistor R2 and the capacitor C2 change to some extent according to the ambient temperature. Since this change becomes larger in accordance with the allowable error, it is desirable to use one having a large allowable error. Furthermore, it is more desirable to use a machine having a different tolerance for each pachinko machine 10. Thus, the voltage input to the multivibrator 108c changes with time (or for each pachinko machine 10), and the period of the output pulses also changes.
Instead of the multivibrator 108c, a voltage controlled oscillation circuit (VCO) that can control the oscillation frequency by an input voltage may be used. According to the voltage controlled oscillation circuit, the cycle of the pulse signal P4 reliably changes over time.
[0019]
The latch circuit 108b uses a D flip-flop 108d as shown in FIG. 3C, for example. When the winning signal P2 is input to the D terminal and the pulse signal P4 is input to the CK terminal, an operation signal P6 obtained by delaying the winning signal P2 in time is output from the Q terminal. The latch circuit 108b is not limited to the D flip-flop 108d, and any of SR latch, SR latch with gate, D latch, and JK flip-flop may be used. Alternatively, a signal delay circuit (or a signal delay element) such as a buffer may be used instead of the latch circuit 108b.
[0020]
Returning to FIG. 2, the output processing circuit 112 receives the operation data sent from the CPU 110 via the bus 118, and operates various operation devices provided in the pachinko machine 10 such as the lamps 16 and the solenoid 32. Operate. The display control circuit 114 receives display data sent from the CPU 110 via the bus 118 and performs control for displaying characters, symbols, images, etc. on the normal symbol display 40 and the special symbol display 42. .
The communication control circuit 116 is a circuit for transmitting / receiving data to / from the frame control unit 200. The frame control unit 200 is configured around a CPU as in the case of the main control unit 100, and since the configuration is known, detailed description thereof is omitted. The frame control unit 200 controls the launch of a pachinko ball and the payout of a prize ball necessary for playing a pachinko game, outputs sound effects and music from the speaker 28, or opens the door by a metal frame sensor 36. The inspection is performed at a predetermined timing.
Note that each of the above components is coupled to the bus 118.
[0021]
Next, the hit determination process for determining the hit / miss is described with reference to FIG. This hit determination process is executed every predetermined period (for example, 4 milliseconds). In order to simplify the description, the winning signal P2 output from the start port sensor 34 will be described.
In FIG. 4, when the start port sensor 34 detects a pachinko ball, a winning signal P2 is output. The input processing circuit 108 that has received the winning signal P2 is delayed in time and outputs the operation signal P6.
[0022]
First, the CPU 110 updates the count value of the counter 106 stored in the RAM 104 shown in FIG. 2 [Step S10]. Specifically, the count value is counted up (or counted down) within a predetermined range.
And it is discriminate | determined whether the pachinko ball won to the 1st type starting port 18 [step S12]. Specifically, the determination is made based on whether or not the operation signal P6 is received from the input processing circuit 108. If the CPU 110 receives the operation signal P6 (YES), the count value of the counter 106 is acquired [step S14].
[0023]
Thereafter, it is determined whether or not the acquired count value matches the winning value [step S16]. If the acquired count value matches the winning value (YES), the jackpot processing is performed [step S18]. This jackpot processing is performed so that, for example, the contents of the special symbol displayed on the special symbol indicator 42 are controlled to stop in a “hit” mode, or the opening / closing control of the lid 20a of the big prize opening 20 is performed. Various processes are performed.
On the other hand, when the CPU 110 does not receive the operation signal P6 in step S12 (NO), the hit determination process is terminated without doing anything. In this case, only the count value is updated. When the count value acquired in step S14 does not match the winning value (NO), the winning determination process is terminated without performing the jackpot process.
[0024]
In the pachinko machine 10 configured as described above, a change in the operation signal P6 with respect to the winning signal P2 will be described with reference to FIG. In FIG. 5, the period of the interrupt signal INT supplied to the CPU 110 is substantially equal to the period Δt2 (the predetermined period, that is, 4 milliseconds).
When the winning signal P2 changes from the low level to the high level at time t2, the pulse signal P4 is in the high level state. Thereafter, at time t4 when the pulse signal P4 changes from the low level to the high level, the operation signal P6 changes from the low level to the high level. Accordingly, there is a time lag of the period Δt4 from when the winning signal P2 is output from the start port sensor 34 until the CPU 110 receives the operation signal P6. That is, the operation signal P6 is output with a time delay.
When the above steps S12 to S18 are executed based on the operation signal P6, the timing for each cycle of the counter 106 is shifted from the timing at which the CPU 110 acquires the count value. Therefore, even if the pachinko ball is fired at every cycle of the counter 106, it does not switch to a gaming state (in this example, a big hit state) as intended by the player trying to cheat. Therefore, illegal games can be prevented.
[0025]
Here, it is desirable that the period (period Δt6) of the pulse signal P4 is larger than the period (period Δt2) of the interrupt signal INT. By doing so, the time lag (period Δt4) becomes larger than the period of the interrupt signal INT (period Δt2), and it becomes easy to remove the timing of the player who tries to cheat. Therefore, illegal games can be prevented more reliably.
Then, when the winning signal P2 transitions from the high level to the low level at time t6, the activation signal P6 transitions from the high level to the low level at time t8, which is delayed in time, as in the transition from the low level to the high level. To do.
[0026]
Therefore, according to the first embodiment, the operation signal P6 sent from the input processing circuit 108 to the CPU 110 is delayed in time compared to the winning signal P2 output from the start port sensor 34 (winning sensor). That is, the timing for each cycle of the counter 106 is different from the timing at which the CPU 110 acquires the count value. For this reason, even if the pachinko ball is fired at every cycle of the counter 106, it does not switch to a gaming state intended by the player who intends to cheat. Therefore, illegal games can be prevented.
The latch circuit 108b that has received the winning signal P2 sends an operation signal P6 to the CPU 110 when the pulse signal P4 (pulse) output from the oscillator 108a transitions from a low level to a high level (to a predetermined state). By making the timing at which the pulse signal P4 transitions from the low level to the high level is different from one cycle of the counter 106, the timing of “hit” cannot be matched. Since the player cannot know the timing at which the pulse signal P4 transitions from the low level to the high level, illegal games can be prevented.
[0027]
Furthermore, the oscillation period of the oscillator 108a differs depending on the pachinko machine 10 (game machine) depending on the resistor R2 and the capacitor C2 used. Therefore, even if it can synchronize with the period of the oscillator 108a of a certain pachinko machine 10 by improper means such as a sensory sensor, it cannot be synchronized with other pachinko machines 10, and the possibility of being “winning” is extremely low. . Therefore, fraudulent games can be minimized.
In the first embodiment, the winning signal P2 output from the start sensor 34 has been described. However, the winning signal P2 output from the gate sensor 38 can be similarly applied. Therefore, it is possible to prevent not only “big hit” by the special symbol display 42 but also illegal games aimed at “winning” by the normal symbol display 40.
[0028]
[Embodiment 2]
Next, a second embodiment in which a self-excited oscillation circuit is applied to the oscillator 108a constituting the input processing circuit 108 will be described with reference to FIG. 6A shows an oscillator circuit configuration using a crystal resonator, FIG. 6B shows an oscillator circuit configuration using a resistor and a capacitor, and FIG. 6C shows an inverter. The circuit configurations of the oscillators connected in multiple stages are shown respectively.
[0029]
The oscillator shown in FIG. 6A includes inverters (NOT circuits) Q10 and Q12, a resistor R10, a crystal resonator XL, and capacitors C10 and C12. A resistor R10 and a crystal resonator XL are connected in parallel to both ends of the inverter Q10, and are further connected to ground via capacitors C10 and C12. An inverter Q12 is connected in series to the inverter Q10, and a pulse signal P4 is periodically output from the output side of the inverter Q12. In this oscillator, the period of the pulse signal P4 depends on the oscillation frequency of the crystal unit XL.
Note that other types of vibrators such as ceramic vibrators may be used in place of the quartz crystal vibrator XL.
[0030]
The oscillator shown in FIG. 6B includes inverters Q14 and Q16, a resistor R12, and a capacitor C14. A resistor R12 is connected in parallel to both ends of the inverter Q14. Further, the capacitor C14, the inverter Q14, and the inverter Q16 are connected in series in this order from the ground side. One side of the capacitor C14 not connected to the inverter Q14 is connected to the ground, and the pulse signal P4 is periodically output from the output side of the inverter Q16. Note that a value obtained by multiplying the capacitance value of the capacitor C14 and the resistance value of the resistor R12 (= C14 × R12) is a time constant and is substantially equal to the cycle of the output pulse signal P4.
[0031]
The oscillator shown in FIG. 6C includes four inverters Q18, Q20, Q22, and Q24. These inverters Q18, Q20, Q22, Q24 are connected in series. Further, the output side of inverter Q22 is connected to the input side of inverter Q18 to form a feedback loop. Then, the pulse signal P4 is periodically output from the output side of the inverter Q24. In this example, the inverters are connected in four stages, but the inverters can be connected in multiple stages (several tens to several hundreds). Each inverter is delayed by a minute time until an input pulse is output, and this delay time Δt8 is proportional to the number of inverters connected in multiple stages. Therefore, the value obtained by multiplying the inverter stage number n by the delay time Δt8 (= n × Δt8) is substantially equal to the cycle of the output pulse signal P4.
[0032]
According to the second embodiment, the self-excited oscillation circuit periodically outputs the pulse signal P4. However, the period of the pulse is not highly accurate and is not uniform. Therefore, the operation signal P6 sent to the CPU 110 by the input processing circuit 108 that has received the winning signal P2 and the pulse signal P4 also becomes non-uniform, and further, the timing at which the CPU 110 refers to the count value of the counter 106 becomes non-uniform. Therefore, the timing at which the CPU 110 obtains a “hit” by the counter value acquired from the counter 106 becomes non-uniform, and since the player cannot know the cycle of the pulse signal P4, it is possible to reliably prevent illegal games. .
The oscillator 108a is not only constituted by the self-excited oscillation circuit, but also a multivibrator, a blocking oscillation circuit, a Colpitts oscillation circuit, a Hartley oscillation circuit, a phase shift oscillation circuit, a piezoelectric oscillation circuit, a Meissner oscillation circuit, a phase-locked oscillation circuit, etc. You may comprise by the other self-oscillation circuit like. Even with these self-excited oscillation circuits, the same effects as those of the oscillation circuits shown in FIG. 6 can be obtained.
[0033]
[Embodiment 3]
Next, Embodiment 3 in which the period of the pulse signal received by the latch circuit 108b in the input processing circuit 108 is changed over time will be described with reference to FIGS. FIG. 7 shows the configuration of the second input processing circuit. FIG. 8 shows the configuration of the third input processing circuit. In these drawings, the same elements as those shown in FIG. 3A are denoted by the same reference numerals, and the description thereof is omitted.
[0034]
The circuit configuration shown in FIG. 7 is different from the circuit configuration shown in FIG. 3A in that a frequency divider 108e is provided between the oscillator 108a and the latch circuit 108b. The frequency divider 108e receives the frequency division value recorded in the ROM 102. This divided value can be received from the CPU 110 through the bus 118 at any time. The frequency divider 108e to which the pulse signal P4 is input divides the pulse based on the divided value and outputs the pulse signal P4a. The latch circuit 108b receives the winning signal P2 and the pulse signal P4a and sends an operation signal P6 to the CPU 110. Therefore, the timing of the operation signal P6 sent to the CPU 110 changes.
Here, the timing at which the frequency divider 108e receives the frequency-divided value is set after at least the first jackpot occurrence after the pachinko machine 10 is turned on (or reset). Thus, even after the first big hit, even if the pachinko ball is fired at every cycle of the counter 106 and the big hit is aimed, the pulse signal P4 is divided by the frequency divider 108e, so the timing is shifted. Therefore, illegal games can be prevented.
A plurality of frequency division values may be recorded in the ROM 102 and sent to the frequency divider 108e at an appropriate time while switching the frequency division values. By doing so, the oscillation cycle of the pulse signal P4a received by the latch circuit 108b can be changed over time. Therefore, illegal games can be prevented more reliably.
[0035]
Further, the circuit configuration shown in FIG. 8 is the same as the circuit configuration shown in FIG. 7 except that the frequency divider 108e receives a frequency division value from a medium such as the CPU 110 or the hall computer 300. The frequency division value received from the CPU 110 includes an ID number and a manufacturing number recorded in the CPU 110. The hall computer 300 is connected via a communication control circuit 116 as shown in FIG. The frequency division value received from the hall computer 300 is recorded on a recording medium such as a ROM, a RAM, or a hard disk in the hall computer 300. Other media such as circuits and elements include the frame control unit 200 shown in FIG. 2, cards (prepaid cards, IC cards, paper cards, etc.), or printed materials on which characters, symbols, and the like are printed. On these media, frequency division values are recorded in a data format, magnetism, bar code, characters, symbols, and the like.
[0036]
According to the third embodiment, by setting the frequency division value recorded on the medium in the frequency divider 108e at an appropriate time, the oscillation period of the pulse signal P4a received by the latch circuit 108b is changed over time. be able to. Since the player cannot know these division values and the timing sent to the frequency divider 108e, even if the pachinko ball is fired at every cycle of the counter 106, the player who intends to cheat is intended. It does not switch to such a gaming state. That is, even if the period based on the oscillator 108a can be synchronized by a fraudulent means such as a sensory device at a certain time, it cannot be synchronized at a later time, and the possibility of being “winning” is extremely low. Therefore, illegal games can be prevented more reliably.
[0037]
[Other Embodiments]
In the gaming machine control device described above, the structure, shape, size, material, number, arrangement, operating conditions, and the like of other parts are not limited to the above embodiment. For example, each of the following embodiments to which the above embodiment is applied can be implemented.
(1) In the first to third embodiments, only one latch circuit 108b is provided, but a plurality of latch circuits 108b may be connected in multiple stages. An example of connection in three stages is shown in FIG. In the one-stage latch circuit 108b, as shown in FIG. 5, the operation signal P6 is output with a time delay for the period Δt4. Therefore, the delay is delayed by (3 × Δt4) in the third stage, and is delayed by (n × Δt4, where n> 2) in the nth stage. As a result, the timing for each cycle of the counter 106 is different from the timing at which the CPU 110 acquires the count value. For this reason, even if the pachinko ball is fired at every cycle of the counter 106, it does not switch to a gaming state intended by the player who intends to cheat. Therefore, illegal games can be prevented.
Note that the delay time differs for each pachinko machine 10 by making the number of stages of the latch circuit 108b different for each pachinko machine 10. In this case, the occurrence of illegal games can be minimized.
[0038]
(2) Carbon resistors and metal film resistors are generally used for the resistors R2, R4, R10, and R12 in the first and second embodiments. Instead of these resistors, a thermistor whose resistance value varies greatly according to the ambient temperature may be used. Further, variable capacitors may be used for the capacitors C2, C10, C12, and C14. By doing so, the input voltage input to the multivibrator 108c can be greatly changed, and the period of the pulse signal P4 output from the multivibrator 108c is also greatly changed. Therefore, it is possible to increase the difference between the timing of the counter 106 for each cycle and the timing at which the CPU 110 acquires the count value. Therefore, since the timing of the player who tries to play the illegal game can be greatly removed, the illegal game can be prevented.
[0039]
(3) In the first embodiment, the transition to the predetermined state is the transition of the pulse signal P4 from the low level to the high level as shown in FIG. The present invention is not limited to this form but can be applied to other forms of change. For example, there is a form in which the pulse signal P4 shown in FIG. 5 transitions from a high level to a low level. Further, after the pulse signal P4 transitions from the low level to the high level, the pulse signal P4 may further transition from the high level to the low level. In these cases, the latch circuit 108b corresponding to the form is required. By so doing, it is possible to extend or contract the period Δt4 in which the operation signal P6 is output with a time delay. Therefore, the difference between the timing of the counter 106 for each cycle and the timing at which the CPU 110 acquires the count value can be increased.
[0040]
(4) In the first to third embodiments, the present invention is applied to the pachinko machine 10. Not only in this form, such as an arrangement ball machine or a video game machine, a CPU that controls the gaming machine, a counter that changes the count value within a predetermined range, and a winning signal output from the winning sensor And an input processing circuit that sends an operation signal to the CPU, and the same applies to a control device for a gaming machine that switches the gaming state based on a count value read by the CPU that has received the operation signal with reference to the counter. it can. Even in these cases, the same effects as in the first to third embodiments can be obtained.
[0041]
[Other Embodiments]
Although the embodiment of the present invention has been described above, this embodiment has not only the embodiment of the invention described in the claims but also other embodiments of the invention. Aspects of the present invention are listed below, and related explanations are given as necessary.
[0042]
[Aspect 1] In the gaming machine control device according to claim 2,
A control device for a gaming machine comprising a frequency divider that receives a pulse output from the oscillator, divides the pulse based on a frequency division value, and outputs the frequency-divided value.
[Related Description of Aspect 1] According to this aspect, the latch circuit receives not the pulse output from the oscillator but the pulse divided by the frequency divider. Then, an operation signal is sent to the CPU when the divided pulse transitions to a predetermined state. Since it is impossible to match the timing of “winning” by this frequency divider, it is possible to prevent illegal games.
[0043]
[Aspect 2] In the gaming machine control device according to aspect 1,
The frequency division value is recorded on a recording medium different from the recording medium on which the program for controlling the gaming machine is recorded, and the recorded frequency division value is set in the frequency divider. .
[Related Description of Aspect 2] According to this aspect, the period of the pulse input to the latch circuit is changed by performing the frequency division value set in the frequency divider at an appropriate time. For this reason, since the cycle of the pulse input to the latch circuit varies in various ways, it is extremely difficult to match the timing of “winning”. Therefore, illegal games can be reliably prevented.
[0044]
【The invention's effect】
According to the present invention, the operation signal sent from the input processing circuit to the CPU is delayed in time from the winning signal output from the winning sensor. That is, the timing of winning and the timing at which the CPU switches the gaming state are shifted. Therefore, since the timing for switching the gaming state is different from one cycle of the counter, illegal gaming can be prevented.
[Brief description of the drawings]
FIG. 1 is a front view showing an external appearance of a pachinko machine.
FIG. 2 is a block diagram illustrating a configuration of a control unit.
FIG. 3 is a diagram showing a configuration of a first input processing circuit.
FIG. 4 is a flowchart showing a hit determination process.
FIG. 5 is a time chart showing a change in an operation signal with respect to a winning signal.
FIG. 6 is a circuit diagram showing a configuration of an oscillator.
FIG. 7 is a diagram showing a configuration of a second input processing circuit.
FIG. 8 is a diagram showing a configuration of a third input processing circuit.
FIG. 9 is a diagram showing a configuration of a fourth input processing circuit.
[Explanation of symbols]
10 Pachinko machines (game machines)
18 Type 1 starting port
34 Start sensor (winning sensor)
38 Gate sensor (winning sensor)
100 Main control unit
102 ROM
104 RAM
106 counter
108 Input processing circuit
108a oscillator
108b Latch circuit
108c Multivibrator
108d D flip-flop
108e divider
110 CPU
200 Frame control unit
300 hall computer
P2 winning signal
P4, P4a Pulse signal
P6 operation signal

Claims (4)

A CPU for controlling the gaming machine;
A counter that changes the count value within a predetermined range;
An input processing circuit that receives a winning signal output from the winning sensor and sends an operation signal to the CPU;
In the control device of the gaming machine that switches the gaming state based on the count value read by the CPU that has received the operation signal with reference to the counter,
The input processing circuit is
An oscillator,
A latch circuit that receives a pulse and a winning signal output from the oscillator and sends an operation signal when the pulse transits to a predetermined state;
Have
A control device for a gaming machine, wherein an operation signal is sent to a CPU after being delayed in time after receiving a winning signal. In the gaming machine control device according to claim 1 ,
A control device for a gaming machine, wherein the oscillator is constituted by a self-excited oscillation circuit. In the gaming machine control device according to claim 1 ,
A control device for a gaming machine, wherein the oscillator oscillates with a different period for each gaming machine. In the gaming machine control device according to claim 1 ,
A control device for a gaming machine, wherein the oscillator oscillates at different periods with time.

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