JP4675386B2 - Control device for gaming machine - Google Patents

Description

  The present invention relates to a control device for a gaming machine, and relates to a technique for preventing an abnormal gaming state due to an oscillator failure or the like.

In a gaming machine such as a pachinko machine or a slot machine machine, whether it is “winning” or “out of” is determined by a random value.
The value of the random number coincides with a value counted by a normal counter (hereinafter referred to as “count value”), and is changed within a certain range every certain period (specifically, 2 to 4 milliseconds).
That is, every time a pulse (pulse signal) output from the oscillator is received, the count value is incremented by 1. When the count value reaches the upper limit value, the count value is cleared and circulated.
For example, assuming that the certain range is 0 to 299, the count value is incremented by 1 when the count value is 0 to 298, and is cleared to 0 when the count value is 299.
Accordingly, the counter continues to be updated periodically after the game machine is powered on (or reset).

The count value is often used for symbol display of a symbol display provided in a gaming machine.
That is, when a game ball wins at the starting port where the symbol variation starts, the count value when the winning is detected is read.
Then, according to the read count value (hereinafter referred to as “read value”), the content of the symbol displayed on the symbol display device is controlled.
For example, it is assumed that “7” is a winning in the above certain range.
If the read value is “7”, control is performed so that the content of the symbol displayed on the symbol display is stopped in a “winning” manner (specifically, a winning symbol such as “777”).
Further, if the read value is a value other than “7”, the content of the symbol displayed on the symbol display device is controlled to stop in a “displacement” mode according to the value.

Here, in the pachinko machine, the timing at which the game ball wins the start opening (hereinafter referred to as “winning timing”) is not uniform because the game ball behaves randomly due to many obstacle nails arranged on the game board surface.
Therefore, even if the count value of the counter updated every predetermined period is read at the winning timing, the read value eventually becomes a random value.
However, since the counter is updated every predetermined period, the period from when a “winning” comes out until the next “winning” comes out is also constant.
The period is equal to a period in which the count value makes a round of the predetermined value range, and is hereinafter referred to as a “count period”.
In the example of the predetermined value range, when 300 values are updated every 4 milliseconds, the count cycle becomes 1.2 seconds.
Therefore, if the game ball wins the starting opening 1.2 seconds after the reading value once becomes a winning value, the reading value at that time also becomes a winning value.

By the way, there is a so-called “sensory sensation device” that generates signals such as vibrations and sounds at regular intervals.
If the player turns on / off the launching device according to the signal generated by the sensor, the game ball can be fired at regular intervals.
Moreover, depending on the operation pattern of a member, a player may know the said fixed period irrespective of a body sensor.
As an operation pattern of this member, there are, for example, a blinking pattern of a lamp provided on the game board surface, a sound effect emitted from a speaker, an operation pattern of an accessory, and the like.
Further, the operation pattern of the members is generally operated at a timing unrelated to one cycle of the counter.
However, if it operates in synchronism with one cycle of the counter due to a cause such as a design or manufacturing error, it becomes possible for the player to know the fixed cycle.
If the player turns on / off the launching device according to the operation pattern of this member, the game ball can be fired at regular intervals.
However, as described above, since a number of obstacle nails are provided on the game board surface, the winning timing does not necessarily occur periodically.

In view of this, the present applicant has disclosed a technique for preventing illegal games by the above-mentioned sensory devices in Japanese Patent Application No. 9-239854 (Patent Document 1).
In this technique, separately provided the first oscillator and the oscillator you supply a signal to activate the CPU, to change the count value of the counter every time it receives a signal output from the first oscillator.
If the oscillation frequency of the oscillator is different from that of the first oscillator or the timing of the signal is shifted, it is very difficult to match the timing of “hit” even if a sensory device or the like is used.
Therefore, it is possible to prevent illegal games.

Japanese Patent Laid-Open No. 11-76582

However, when the first oscillator stops due to a failure or the like, the counter is not counted.
Therefore, depending on the count value at which the count is stopped, it is always “winning” or always “out”.
In such a state, a game on the gaming machine is not established.
The present invention has been made in view of such points, and in the case where the first oscillator stops operating normally, the gaming machine is stopped and prevented from entering an abnormal gaming state. Objective.

The present invention is a control device for controlling a gaming machine for performing a game in which an electronic lottery is performed using random numbers, and a ROM for storing a gaming control program for controlling the gaming machine; In accordance with the game control program, a CPU that controls a game in the gaming machine including the lottery by receiving an operation pulse of a predetermined period, a first oscillator that generates a predetermined count pulse, and the predetermined count pulse In response, the first count value is cyclically counted up or down within a fixed value range, and when the lottery is performed, the first count value as the random number is set in response to an access request from the CPU. A first counter that outputs to the first oscillator, a second oscillator provided separately from the first oscillator, and the first oscillator or the second oscillator A second counter that changes the second count value in response to a pulse output from one of the two and resets the second count value in response to a pulse output from the other, and a constant setting that sets a predetermined value And a first stop that outputs a signal for stopping the CPU when the second counter reaches the value set in the constant setting, and oscillates the oscillation state of the predetermined counting pulse. And a monitoring stop unit for monitoring and outputting a signal for stopping the CPU when the oscillation frequency of the predetermined counting pulse is out of a predetermined range.
According to the present invention, it monitors the oscillation state of the monitoring stop is always the first oscillator, a second oscillator wherein the first oscillator is provided separately, the first oscillator or said A second counter that receives a pulse output from one of the two oscillators to change the second count value, and that receives a pulse output from either one of the oscillators and resets the second count value; and a predetermined value A monitoring stop unit comprising: a constant setting device to be set; and a first stop device that outputs a signal for stopping the CPU when the second counter reaches a value set in the constant setting. The oscillation state of the counting pulse is monitored, and the CPU is stopped when the oscillation frequency of the predetermined counting pulse falls outside the predetermined range.
Since the gaming machine is stopped by the stop of the CPU, an abnormal gaming state can be prevented.
Here, the “predetermined value” is a value larger than the absolute value of the difference between the oscillation frequencies of the first oscillator and the second oscillator in the normal state.
In this aspect, the first oscillator is provided separately from the second oscillator, and the second count value counted by the second counter in a normal state does not reach a predetermined value larger than the difference frequency.
However, in a state where the oscillation frequency of the first oscillator is outside the predetermined range, the second count value reaches a predetermined value.
The first stop device outputs a signal for stopping the CPU when the second count value reaches a predetermined value, so that the gaming machine stops.
In addition, it is extremely rare that the first oscillator and the second oscillator simultaneously fail. Therefore, it is possible to more reliably prevent an abnormal gaming state.

In the present invention, the monitoring stop unit measures the interval between the period setting unit for setting a predetermined period and the previous pulse output from the first oscillator and the current pulse, and the interval is the period setting unit. A second stop device that stops the CPU when a predetermined period of time is exceeded, monitoring the oscillation state of the predetermined counting pulse, and the oscillation frequency of the predetermined counting pulse is out of a predetermined range Then, a signal for stopping the CPU may be output.
According to this aspect, since the first oscillator outputs a signal at a substantially constant period, the interval between the previous signal and the current signal is also substantially constant.
The interval is always measured by the second signal output unit, and the CPU is stopped when a predetermined period is exceeded.
The gaming machine is stopped by the stop of the CPU.
Therefore, it is possible to prevent the gaming machine from entering an abnormal gaming state with a simple configuration.

  In the present invention, the first oscillator may be selected by a selection unit from a plurality of oscillators.
  According to this aspect, when the oscillator that supplies the signal to the first counter is not in a normal oscillation state, the game is normally switched by switching to any one of the oscillators that normally oscillate at an oscillation frequency within a predetermined range. Can be continued.

In here, an example in an example of a digital circuit monitoring stop, which the monitoring stop in the second embodiment and an analog circuit for stopping the CPU monitors the embodiment 1, the first oscillator implementation Each is shown.
In the third embodiment, an example in which the first oscillator is configured by a plurality of oscillators and any one of the normal oscillators is selected to output a signal is shown.

[Embodiment 1] First, in Embodiment 1, the present invention is applied to a pachinko machine that is one of gaming machines, and an oscillator that supplies a signal to a counter is not in a normal oscillation state. In this mode, the CPU is stopped.
The first embodiment will be described with reference to FIGS.
Here, FIG. 1 shows a front view of the appearance of the pachinko machine.
FIG. 2 is a block diagram showing the configuration of the control unit.
FIG. 3 is a block diagram showing the configuration of the counter block.
FIG. 4 is a circuit diagram showing a configuration example of the oscillator.
FIG. 5 is a flowchart showing the counting process, and FIG. 6 is a flowchart showing the monitoring process.

In FIG. 1, first, a first type starting port 26, a big winning port 32, a composite device 14, a general winning port and the like are appropriately arranged on the game board surface 12 of the pachinko machine 10.
The first type starting port 26 corresponds to a predetermined area, and operates in the same manner as a normal winning port to pay out a prize ball (prize ball).
The first type start port 26 is provided with a start port sensor 48 to detect a pachinko ball that has won the first type start port 26.
On the other hand, gate sensors 30 and 50 are provided on the gates 28 and 52, respectively, to detect pachinko balls that have passed through the gates 28 and 52.
The special winning opening 32 is provided with a lid 32 a, which is opened and closed by a solenoid 46.
The special winning opening 32 is provided with a V zone 32c.
If the pachinko ball wins the V zone 32c at a certain time, the big hit gaming state can be continued within a certain limit (for example, 16 times).
Further, a lower start port 32b is provided at the lower portion of the lid 32a.

The composite device 14 is provided with a holding ball lamp 22, a decorative board 54, a normal symbol display 20, a special symbol display 24, and the like.
The holding ball lamp 22 displays the number of pachinko balls that have won the first type start port 26 during symbol variation.
Specifically, a total of four are provided, two on each of the left and right sides of the decorative board 54 provided above the special symbol display 24.
The decorative board 54 is for exhibiting a decorative effect, and is provided with a normal symbol display 20 and a lamp (included in the lamps 16).

The normal symbol display 20 uses a 7-segment LED, and displays normal symbols (for example, alphanumeric characters and symbols).
The normal symbol starts to change when a pachinko ball passes through the gates 28 and 52, and then stops.
When the stopped normal symbol coincides with the winning symbol (for example, “7”), the lid of the lower start port 32b is opened for a certain period (for example, 10 seconds).
The normal symbol display 20 may be another display capable of displaying normal symbols such as a liquid crystal display, CRT, LED display, plasma display, or the like.
A liquid crystal display is used as the special symbol display 24, and displays special symbols (for example, pictures, alphanumeric characters, symbols, etc.), decorative symbols, and the like.
The special symbol starts to change when the pachinko ball wins the first type starting port 26 or the lower starting port 32b, and then stops.
The special symbol display 24 may be a display capable of displaying special symbols such as a CRT, LED display, plasma display or the like.
Also, the normal symbol and the special symbol may be displayed on the special symbol display 24.

Other than the game board surface 12, a lower plate 38 for temporarily storing pachinko balls including prize balls, an ashtray 40 for storing cigarette butts, a speaker 42 for producing sound effects and music, etc., and a player's hand touching the handle 34. A touch sensor 36 for detecting whether or not there is a metal frame sensor 56 for detecting the opening of the glass frame 18 is provided.
The speaker 42 is provided inside an upper plate 44 that is a tray for receiving a prize ball, and the touch sensor 36 and the metal frame sensor 56 are respectively provided at predetermined positions.
In addition, the lamps 16 including the top lamps use display bodies such as light bulbs and LEDs, and are not limited to the illustrated positions, and are disposed at appropriate positions according to the game contents of the pachinko machine 10 and the like.

Next, the configuration of the main control unit 100 will be described with reference to FIG.
In FIG. 2, the main control unit 100 includes a CPU (processor) 110, a counter block 102, a ROM 104, a RAM 106, an input processing circuit 108, an output processing circuit 112, a display control circuit 114, and a communication control circuit 116.
The CPU 110 controls the pachinko game in the pachinko machine 10 according to the game control program stored in the ROM 104.
The game control program includes a program for realizing first-type start port processing, overflow ball processing, symbol control processing, variation display processing, hit processing, miss processing, and the like, which will be described later.
A configuration example and operation of the counter block 102 will be described later.
In addition to the game control program, the ROM 104 stores data such as a winning value and winning symbol data.
The ROM 104 is generally an EPROM, but is not limited to this, and an EEPROM or a flash memory may be used.
A DRAM is generally used as the RAM 106, but a nonvolatile memory such as an SRAM or a flash memory may be used.
The RAM 106 stores various data and input / output signals.

The input processing circuit 108 receives each detection signal sent from the start port sensor 48, converts it into a data format that can be processed in the main control unit 100, and sends it to the CPU 110 and the RAM 106 via the bus 118.
On the other hand, the output processing circuit 112 receives the operation data sent from the CPU 110 via the bus 118 and operates various operation devices provided in the pachinko machine 10 such as the solenoid 46.

The display control circuit 114 receives display data sent from the CPU 110 via the bus 118 and controls the normal symbol display 20 and the special symbol display 24 to display characters, symbols, images, and the like.
Although not shown, the display control circuit 114 displays the number of lamps corresponding to the number of reserved balls (for example, 0 ≦ the number of reserved balls ≦ 4) on the reserved ball lamp 22, and appropriately lights (flashes) the lamps 16. Display control is also performed.
Here, the number of reserved balls is the number of pachinko balls that won the first type starting port 26 while the special symbol is displayed in a varying manner on the special symbol display 24.
The communication control circuit 116 is a circuit for transmitting / receiving data to / from the frame control unit 200.
The frame control unit 200 is configured mainly with a CPU as in the case of the main control unit 100, and since the contents thereof are publicly known, detailed description thereof is omitted.
The frame control unit 200 controls the launch of the pachinko balls and the payout of the prize balls necessary for playing the pachinko game, emits sound effects and music from the speaker 42, or checks the door opening by the metal frame sensor 56, etc. At an appropriate time.
Note that each of the above components is coupled to the bus 118.

The counter block 102 shown in FIG. 3 includes a monitoring unit 150 and a counting unit 160.
In the connection with the CPU 110, the bus 118 and the like are omitted.
The monitoring unit 150 corresponds to a monitoring stop unit, and includes a setting register 152, a comparator 154, an oscillator 156, a counter 158, and the like.
The setting register 152 corresponds to a constant setting device, and temporarily records (stores) setting values set by the CPU 110, the hall computer, or the like.
The oscillator 156 corresponds to a second oscillator and periodically outputs a pulse.
The oscillation frequency f3 of the oscillator 156 may be the same as or different from the oscillation frequency f2 of the oscillator 162 described later.
That is, the oscillation frequency f3 of the oscillator 156 is preferably higher than the oscillation frequency f2 of the oscillator 162 (f3> f2), but may be the same or lower (f3 ≦ f2).
The counter 158 corresponds to a second counter, and receives a pulse output from the oscillator 156 and counts up (or counts down) the count value.
The counter 158 receives the pulse output from the oscillator 162 and clears the counter to a predetermined value.
Here, the predetermined value is, for example, 0 when counting up, and is 299, for example, when counting down.
Note that the count value may be counted up (or counted down) in response to the pulse output from the oscillator 162, and the counter may be cleared to a predetermined value in response to the pulse output from the oscillator 156.
The comparator 154 corresponds to a first stop, and outputs a stop signal when the count value of the counter 158 reaches the set value of the setting register 152, and outputs nothing when it does not.
Upon receiving this stop signal, the CPU 110 stops.

On the other hand, the count unit 160 includes an oscillator 162, a counter 164, a setting register 166, a comparator 168, and the like.
The oscillator 162 is provided separately from the oscillator 101 and periodically outputs pulses. The oscillator 162 corresponds to a first oscillator, and the oscillation frequency f2 may be the same as or different from the oscillation frequency f1 of the oscillator 101.
That is, the oscillation frequency f2 of the oscillator 162 is preferably higher (f2> f1) than the oscillation frequency f1 of the oscillator 101, but may be the same or lower (f2 ≦ f1).
When the oscillation frequencies are the same, it is desirable that the pulses output from the oscillator 101 and the oscillator 162 have a phase difference.
The counter 164 receives the pulse output from the oscillator 162 and counts up (or counts down) the count value.
The counter 164 receives the clear signal output from the setting register 166 and clears the counter with a predetermined value.
Similar to the setting register 152, the setting register 166 temporarily records (stores) setting values set by the CPU 110, the hall computer, or the like.
The comparator 168 outputs a clear signal when the count value of the counter 164 reaches the set value of the setting register 166, and outputs nothing when it does not.
In relation to the counting process (see FIG. 6), which will be described later, when there is a count value access request from the CPU 110 (step S38), the counter 164 of the counting unit 160 outputs the count value to the CPU 110 (step S40).
For example, when a pachinko ball wins at the first type starting port 26, the CPU 110 acquires a count value as a random value from the counter 164, and determines whether or not the jackpot / outage.

Next, a specific circuit configuration of the oscillators 101, 156, and 162 shown in FIG. 3 will be described with reference to FIG.
4A shows an oscillator circuit configuration using a crystal resonator, FIG. 4B shows an oscillator circuit configuration using a resistor and a capacitor, and FIG. 4C shows an inverter. The circuit configurations of the oscillators connected in multiple stages are shown respectively.

The oscillator shown in FIG. 4A includes inverters (NOT circuits) Q10 and Q12, a resistor R10, a crystal resonator XL, and capacitors C10 and C12.
A resistor R10 and a crystal resonator XL are connected in parallel to both ends of the inverter Q10, and are further connected to the ground via capacitors C10 and C12.
An inverter Q12 is connected in series to the inverter Q10, and pulses PL are periodically output from the output side of the inverter Q12.
In this oscillator, the period of the pulse PL depends on the oscillation frequency of the crystal unit XL.
Note that other types of vibrators such as ceramic vibrators may be used in place of the quartz crystal vibrator XL.

The oscillator shown in FIG. 4B includes inverters Q14 and Q16, a resistor R12, and a capacitor C14.
A resistor R12 is connected in parallel to both ends of the inverter Q14.
Further, the capacitor C14, the inverter Q14, and the inverter Q16 are connected in series in this order from the ground side.
One side of the capacitor C14 not connected to the inverter Q14 is connected to the ground, and the pulse PL is periodically output from the output side of the inverter Q16.
Note that a value obtained by multiplying the capacitance value of the capacitor C14 and the resistance value of the resistor R12 (= C14 × R12) is a time constant, which is substantially equal to the cycle of the output pulse PL.

The oscillator shown in FIG. 4C includes four inverters Q18, Q20, Q22, and Q24.
These inverters Q18, Q20, Q22, Q24 are connected in series.
Further, the output side of inverter Q22 is connected to the input side of inverter Q18 to form a feedback loop.
Then, a pulse PL is periodically output from the output side of the inverter Q24.
In this example, the inverters are connected in four stages, but the inverters can be connected in four or more stages (for example, several tens to several hundreds).
Each inverter is delayed by a minute time until the input pulse is output, and this delay time Δt is substantially proportional to the number of inverters connected in multiple stages.
Therefore, the value obtained by multiplying the inverter stage number n by the delay time Δt (= n × Δt) is substantially equal to the cycle of the output pulse PL.
The oscillators 101, 156, and 162 are not only configured by the self-excited oscillation circuit, but also a multivibrator, a blocking oscillation circuit, a Colpitts oscillation circuit, a Hartley oscillation circuit, a phase shift oscillation circuit, a piezoelectric oscillation circuit, a Meissner oscillation circuit, a phase You may comprise by another self-excited oscillation circuit like a synchronous oscillation circuit.

Operations of the monitoring unit 150 and the counting unit 160 of the pachinko machine 10 configured as described above will be described with reference to flowcharts (FIGS. 5 and 6).
First, in the processing of the monitoring unit 150 shown in FIG. 5, the counter 158 performs the processing of steps S10 to S18, and the comparator 154 performs the processing of steps S20 and S22.
Here, the setting value is already set in the setting register 152 by the initialization process of the pachinko machine 10 or the like.
When the pulse output from the oscillator 156 shown in FIG. 3 is received [step S10], the counter 158 counts up (or counts down) [step S12].
On the other hand, when the pulse output from the oscillator 162 is received [step S14], the count value is cleared [step S16].
When no pulse is output from the oscillator 156 or the oscillator 162, the process proceeds to the next processing step without doing anything.
Thereafter, the counter 158 outputs the current count value to the comparator 154 [step S18].
Then, the comparator 154 determines whether or not the count value of the counter 158 has reached the set value set by the setting register 152 [step S20].
Specifically, it is determined whether or not set value ≦ count value is satisfied.
When the count value reaches the set value (YES), a stop signal is output to the CPU 110 [step S22], and the process is terminated.
On the other hand, if the count value does not reach the set value (NO), the process returns to step S10 and prepares for the next process.
According to the monitoring unit 150, the count value of the counter 158 does not reach the set value set in the setting register 152 when the oscillator 162 is operating at an oscillation frequency in a normal range.
On the other hand, when the oscillator 162 operates outside the normal range of the oscillation frequency, the count value of the counter 158 reaches the set value set in the setting register 152.
Therefore, a stop signal is output from the comparator 154 to the CPU 110, and the CPU 110 stops.
Therefore, since the pachinko machine 10 is also stopped, it is possible to prevent an abnormal gaming state.

Next, the counter 164 performs the processing of the counting unit 160 shown in FIG.
Here, similarly to the setting register 152, the setting value is already set in the setting register 166 by the initialization process of the pachinko machine 10.
When the pulse output from the oscillator 162 shown in FIG. 3 is received [step S30], the counter 164 counts up (or counts down) [step S32].
If the pulse is not received, the process proceeds to step S34 without doing anything.
When the clear signal output from the comparator 168 is received [step S34], the count value is cleared [step S36].
When the clear signal is not received, the process proceeds to step S38 without doing anything.
Further, when there is a count value access request from the CPU 110 or the like [step S38], the count value is output [step S40].
If the access request is not received, the process returns to step S30 without doing anything for repeated execution.
According to the counting unit 160, the count value increases in accordance with the pulse periodically output from the oscillator 162 in the counter 164, and the count value is cleared in accordance with the clear signal output from the comparator 168.
Thus, the count value of the counter 164 can be referred to from the CPU 110 or the like at any time.

According to the first embodiment, the monitoring unit 150 (monitoring stop unit) constantly monitors the oscillation state of the oscillator 162 (second oscillator) [Steps S10 to S20], and the oscillation frequency of the oscillator 162 is out of the predetermined range. When (including stop), a stop signal is output to the CPU 110 [step S22], and the CPU 110 is stopped.
Since the pachinko machine 10 (game machine) is stopped by the stop of the CPU 110, an abnormal gaming state can be prevented.
The oscillator 156 ( second oscillator) is provided separately from the oscillator 162, and the count value counted by the counter 158 (second counter) in the normal state is set in the setting register 152 larger than the difference frequency. The value (predetermined value) is not reached.
However, when the oscillation frequency of the oscillator 156 is out of the predetermined range, the count value reaches a predetermined value.
Then, the comparator 154 (first signal output unit) outputs a stop signal for stopping the CPU 110 when the count value reaches a predetermined value, so that the pachinko machine 10 stops.
In this case, it is extremely rare for the oscillator 156 and the oscillator 162 to fail simultaneously.
Therefore, it is possible to more reliably prevent an abnormal gaming state.

[Embodiment 2] Next, in Embodiment 2, the present invention is applied to a pachinko machine that is one of the gaming machines as in Embodiment 1, and an oscillator for supplying a signal to a counter is provided. In this mode, the CPU is stopped when the normal oscillation state is lost.
In the second embodiment, the configuration and the like of the pachinko machine 10 are the same as those in the first embodiment, so that differences from the first embodiment will be described with reference to FIG.
FIG. 7 is a block diagram showing the configuration of the counter block.
FIG. 8 is a circuit diagram illustrating a configuration example of the monitoring unit 170.
In these drawings, the same elements as those in FIG.

The monitoring unit 170 illustrated in FIG. 7 corresponds to another monitoring stop unit, and includes a charging circuit 172, a monitoring circuit 174, a latch circuit 176, and the like.
The monitoring circuit 174 monitors the oscillation state of the oscillator 162 and outputs a detection signal when the oscillator 162 operates in a state where the oscillation frequency is out of the normal range.
Specifically, the monitoring circuit 174 uses the charging circuit 172 to discharge the charging potential constantly supplied to the charging circuit when the rising edge (level change) of the pulse output from the oscillator 162 is detected.
At this time, when the oscillator 162 outputs pulses at an oscillation frequency in a normal range, charging and discharging are performed within a predetermined range.
However, when the oscillator 162 operates in a state where the oscillation frequency is out of the normal range, the monitoring circuit 174 continues to be unable to detect the pulse for a predetermined period (for example, 1 millisecond), and the charging circuit 172. Is outside the predetermined range.
As described above, when the potential reaches a potential outside the predetermined range, the monitoring circuit 174 outputs a detection signal.
The detection signal output from the monitoring circuit 174 is held by the latch circuit 176 and output to the CPU 110 as a stop signal.
Thus, the CPU 110 stops and the pachinko machine 10 also stops.

Here, a specific circuit example of the monitoring unit 170 is shown in FIG.
In FIG. 8, the charging circuit 172 includes a resistor R20 and a capacitor C20 connected in series to the constant voltage source Vcc.
As the monitoring circuit 174, a monitoring IC 174a (more specifically, M5295L manufactured by Mitsubishi Electric Corporation) is used.
The latch circuit 176 includes a D flip-flop 176a and an oscillator 176b.
In this circuit example, the pulse output from the oscillator 162 is input to the WD terminal of the monitoring IC 174a.
The TC terminal of the monitoring IC 174a is connected to the connection between the resistor R20 and the capacitor C20, and the capacitor C20 is charged / discharged.
The knot RST1 of the monitoring IC 174a (hereinafter, a knot indicating negative logic is represented by “/”.
In this example, “/ RST1”. ) Terminal outputs the detection signal, so that it is input to the D terminal of the D flip-flop 176a.
Further, in order to operate the D flip-flop 176a, the output of the oscillator 176b is input to the CK terminal.
Since the signal latched by the D flip-flop 176a is output from the Q terminal, it is connected to the bus 118 (see FIG. 3) and sent to the CPU 110.
According to the above circuit example, the operating state of the oscillator 162 can be monitored with a simple circuit configuration, and a stop signal can be output to the PU 110 when the oscillation frequency of the oscillator 162 falls outside a predetermined range.

According to the second embodiment, since the oscillator 162 ( first oscillator) outputs a signal at a substantially constant period, the interval between the previous signal and the current signal is also substantially constant.
The interval is constantly measured by the monitoring circuit 174 (monitoring IC 174a, second signal output device), and the CPU 110 is stopped when a predetermined period is exceeded.
The pachinko machine 10 (game machine) is stopped by the stop of the CPU 110.
Therefore, it is possible to prevent the pachinko machine 10 from entering an abnormal gaming state with a simple configuration.
Therefore, the present invention can be realized at low cost.

[Embodiment 3] Next, in Embodiment 3, the present invention is applied to a pachinko machine that is one of the gaming machines, and the oscillator that supplies a signal to the counter is not in a normal oscillation state. In this case, the game is continued normally.
Since the configuration of the pachinko machine 10 in the third embodiment is the same as that in the first embodiment, differences from the first embodiment will be described with reference to FIGS.
FIG. 9 is a block diagram showing the configuration of the counter block.
FIG. 10 is a block diagram showing the configuration of the oscillation unit.
FIG. 11 is a circuit diagram showing the configuration of the switch.
FIG. 12 is a block diagram showing the configuration of the control unit.
In these drawings, the same elements as those in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof is omitted.

The counter block 102a shown in FIG. 9 is a substitute for the counter block 102 shown in FIG.
The counter block 102a includes an oscillating unit 180 instead of the oscillator 162 as compared with the counting unit 160 shown in FIG.
The oscillation unit 180 includes a plurality of oscillators, and switches to any one of the oscillators that normally oscillate at an oscillation frequency within a predetermined range and outputs a pulse to the counter 164.
The configuration of the oscillator 180 will be described with reference to FIGS.

The oscillation unit 180 shown in FIG. 10 includes a plurality of oscillators 182, 184,.
The plurality of oscillators 182, 184,..., 18z are each composed of a circuit shown in FIG.
The switch 190 receives a pulse output from the plurality of oscillators 182, 184,..., 18z, and switches to any one oscillator that normally oscillates at an oscillation frequency within a predetermined range.
A specific circuit example of the switch 190 is shown in FIG.
This circuit example is an example in which a pulse is output by switching to one of the two oscillators 182 and 184.

A switching device 190 shown in FIG. 11 includes two multivibrators 192 and 196 and two buffers 194 and 198.
Here, a circuit for setting the oscillation period of the multivibrators 192 and 196 is omitted.
As the buffers 194 and 198, a three-state buffer is used.
First, the pulse output from the oscillator 182 is input to the / A terminal of the multivibrator 192, and the constant voltage source Vcc is supplied to the B terminal.
On the other hand, a signal output from the / Q terminal of the multivibrator 192 is input to the gate terminal of the buffer 194.
When the H signal (high level signal) is input to the gate terminal, the buffer 194 enters a high impedance state and outputs nothing, and the L signal (low level signal) is input to the gate terminal. The signal output from the oscillator 182 is inverted and output.
Next, a signal output from the Q terminal of the multivibrator 192 is input to the / A terminal of the multivibrator 196, and a pulse output from the oscillator 184 is input to the B terminal.
On the other hand, a signal output from the / Q terminal of the multivibrator 196 is input to the gate terminal of the buffer 198.
The buffer 198 enters a high impedance state when the H signal is input to the gate terminal and outputs nothing, and the buffer 198 receives the pulse output from the oscillator 184 when the L signal is input to the gate terminal. The signal is inverted and output.

The switch 190 configured as described above operates as follows.
That is, when the oscillators 182 and 184 normally oscillate at oscillation frequencies within a predetermined range, the multivibrators 192 and 196 also operate normally.
Therefore, the L signal is output from the / Q terminal of the multivibrator 192, and the H signal is output from the Q terminal of the multivibrator 196.
Thus, the buffer 194 is activated and the buffer 198 is deactivated.
Therefore, the pulse output from the oscillator 182 is inverted and output as a pulse of the oscillation unit 180.
Further, when the oscillator 182 does not oscillate at the oscillation frequency within the predetermined range (including the stop) and the oscillator 184 oscillates at the oscillation frequency within the predetermined range, the pulse output from the oscillator 184 is inverted to generate the oscillation. It is output as a pulse of the unit 180.
That is, the multivibrator 192 does not operate normally, and the multivibrator 196 operates normally.
Therefore, the H signal is output from the / Q terminal of the multivibrator 192, and the L signal is output from the Q terminal of the multivibrator 196.
Therefore, the buffer 194 is inactive and the buffer 198 is active.
Therefore, the pulse output from the oscillator 184 is inverted and output.
Further, when the oscillator 182 oscillates at an oscillation frequency within a predetermined range and the oscillator 184 does not oscillate at an oscillation frequency within the predetermined range (including stoppage), the pulse output from the oscillator 182 is inverted and the oscillation unit It is output as 180 pulses.
That is, the multivibrator 192 operates normally, and the multivibrator 196 does not operate normally.
Therefore, the L signal is output from the / Q terminal of the multivibrator 192, and the H signal is output from the / Q terminal of the multivibrator 196.
Therefore, the buffer 194 is in an operating state and the buffer 198 is in an inactive state.
Therefore, the pulse output from the oscillator 182 is inverted and output.

According to the third embodiment, the switch 190 operates normally even if one of the plurality of oscillators 182, 184,..., 18z (a plurality of second oscillators) becomes unusable due to a failure or the like. The pulse (signal) can be supplied to the counter 164 (first counter) by switching to one of the oscillators.
Therefore, the pachinko machine 10 (game machine) does not stop the counting of the counter 164 even if any of the oscillators has a failure or the like.
For this reason, even if the CPU 110 refers to the count value of the counter 164, it is always “winning”, or it is not always “missing”, and the hitting can be performed normally.
Therefore, the game by the pachinko machine 10 can be continued.

The pulse output from the oscillating unit 180 can be supplied not only to the counter 164 but also to any circuit or device that requires a pulse.
In particular, it is useful to use as an oscillator that supplies a pulse to the CPU 110 that is the heart of the pachinko machine 10.
The configuration of the control unit in this example is shown in FIG.
In the main control unit 100 illustrated in FIG. 12, the pulse output from the oscillation unit 180 is supplied to the CPU 110, and a counter 106 a instead of the counter block 102 is provided in the RAM 106.
The counter 110a counts up (or counts down) by the CPU 110 accessing it directly.
Thus, even if one of the plurality of oscillators 182, 184,..., 18 z (a plurality of oscillators) becomes unusable due to a failure or the like, the switch 190 switches to the oscillator that operates normally and supplies a signal to the CPU 110. can do.
Therefore, even when a failure or the like occurs in the pachinko machine 10 oscillator, a normal operation is performed.
Therefore, it is possible to continue playing with the gaming machine.
Note that the oscillation unit 180 can be used not only for the CPU 110 but also for the display control circuit 114, the communication control circuit 116, and the like.

[Other Embodiments] In the gaming machine control device described above, the structure, shape, size, material, number, arrangement, operating conditions, etc. of other parts are not limited to the above-described embodiment.
For example, each of the following embodiments to which the above embodiment is applied can be implemented.
(1) In the above embodiments, the present invention is applied to the pachinko machine 10.
Instead of this form, the present invention can be similarly applied to gaming machines other than pachinko machines (for example, arrange ball machines, slot machine machines, video game machines, etc.).
Even in such a gaming machine, when the oscillator has an oscillation frequency outside the predetermined range, the CPU is stopped, so that an abnormal gaming state can be prevented.
In addition, when switching to an oscillator that oscillates at an oscillation frequency within a predetermined range, the game in the gaming machine can be continued.

(2) In the first embodiment, the present invention is realized by a digital circuit, and in the second and third embodiments, the present invention is realized by an analog circuit.
In addition to these circuits, it can be easily realized by a gate array, an ECL circuit, a TTL circuit, or the like.
Further, it can be realized by a microprogram in firmware.
(3) In the first and second embodiments, the monitoring units 150 and 170 send a stop signal directly to the CPU 110 to stop it.
Instead of this form, the CPU 110 passes through a circuit (OR circuit) that takes a logical sum of signals output from the monitoring units 150 and 170 and a signal output from the watchdog timer (NAND circuit) or a circuit that takes a negative logical product (NAND circuit). It is good also as a form sent to.
Here, the watchdog timer is a circuit (device) that monitors whether or not the game control program stored in the ROM 104 of the main control unit 100 shown in FIG. 3 is normally executed.
Thus, the CPU 110 can be stopped not only when the oscillator has an oscillation frequency outside the predetermined range but also when the game control program is not normally executed.
Therefore, it is possible to prevent an abnormal gaming state.

Although the embodiment of the present invention has been described above, this embodiment has not only the embodiment of the invention described in the claims but also other embodiments of the invention.
Aspects of the present invention are listed below, and related explanations are given as necessary.

[Aspect 1] A gaming machine having a CPU for controlling a gaming machine, a plurality of oscillators, and a switching unit that switches to a normally operating oscillator among the plurality of oscillators and supplies a signal for operating the CPU to the CPU. Control device.
[Related Description of Aspect 1] According to this aspect, even when one of a plurality of oscillators becomes unusable due to a failure or the like, the switch is switched to an oscillator that operates normally to supply a signal to the CPU. be able to.
Therefore, the gaming machine performs a normal operation even when a failure or the like occurs in the oscillator.
Therefore, it is possible to continue playing with the gaming machine.

A CPU for controlling the [Aspect 2] gaming machine, the Oscillator you supply a signal to activate the CPU, a first counter which the CPU refers to the first count value, and a plurality first oscillator, the A control device for a gaming machine, comprising: a switch that switches to a normally operating oscillator among a plurality of first oscillators and supplies a signal that changes a first count value to a first counter.
According to this aspect Description of the Related aspects 2], even when the first oscillator in one of the plurality of first oscillator unavailable due to a failure or the like, a first oscillator switching device operates normally The signal can be supplied to the first counter.
Therefore, even if a gaming machine has a failure or the like, the first counter does not stop counting.
For this reason, even if the CPU refers to the count value of the first counter, it is not always “winning” or “out of”, and the hitting can be normally performed.
Therefore, it is possible to continue playing with the gaming machine.

As described above, according to the present invention, monitors the monitoring stop is always oscillating state of the first oscillator, the oscillation frequency of the first oscillator is oscillating state such that the predetermined range CPU Stop.
Since the gaming machine is stopped by the stop of the CPU, an abnormal gaming state can be prevented.

It is a front view which shows the external appearance of a pachinko machine. It is a block diagram which shows the 1st structure of a control part. It is a block diagram which shows the 1st structure of a counter block. It is a circuit diagram which shows the structure of an oscillator. It is a flowchart which shows a count process. It is a flowchart which shows the monitoring process. It is a block diagram which shows the 2nd structure of a counter block. It is a circuit diagram which shows the structural example of a monitoring part. It is a block diagram which shows the 3rd structure of a counter block. It is a block diagram which shows the structure of an oscillation part. It is a circuit diagram which shows the structure of a switching device. It is a block diagram which shows the 2nd structure of a control part.

Explanation of symbols

10 Pachinko machines (game machines)
DESCRIPTION OF SYMBOLS 14 Compound apparatus 20 Normal symbol display 24 Special symbol indicator 26 1st type starting port 28, 52 Gate 30, 50 Gate sensor 32 Big winning port 48 Starting port sensor 100 Main control part 101 Oscillator 102 Counter block 150 Monitoring part (monitoring) Stop part)
156 oscillator ( second oscillator)
158 counter (second counter)
160 count unit 162 oscillator (first oscillator)
164 Counter (first counter)
200 Frame control unit 300 Hall computer

Claims (3)

A control device that controls a gaming machine for performing a game in which a random lottery electronic lottery is performed,
ROM storing a game control program for controlling the gaming machine;
A CPU that controls a game in the gaming machine including the lottery by receiving an operation pulse of a predetermined period in accordance with the game control program;
A first oscillator for generating a predetermined counting pulse;
In response to the predetermined counting pulse, the first count value is cyclically counted up or down within a certain value range, and when the lottery is performed, as the random number in response to an access request from the CPU A first counter that outputs a first count value to the CPU;
A second oscillator provided separately from the first oscillator and a pulse output from either the first oscillator or the second oscillator to change a second count value; A second counter that resets the second count value in response to a pulse output from one of the other, a constant setter that sets a predetermined value, and when the second counter reaches the value set in the constant setting; A first stop that outputs a signal for stopping the CPU, and monitors the oscillation state of the predetermined counting pulse, and the CPU counts when the oscillation frequency of the predetermined counting pulse is out of a predetermined range. A monitoring stop unit that outputs a signal for stopping
A control device for a gaming machine having A control device that controls a gaming machine for performing a game in which a random lottery electronic lottery is performed,
ROM storing a game control program for controlling the gaming machine;
A CPU that controls a game in the gaming machine including the lottery by receiving an operation pulse of a predetermined period in accordance with the game control program;
A first oscillator for generating a predetermined counting pulse;
In response to the predetermined counting pulse, the first count value is cyclically counted up or down within a certain value range, and when the lottery is performed, as the random number in response to an access request from the CPU A first counter that outputs a first count value to the CPU;
A period setting unit for setting a predetermined period;
A second stop for measuring the interval between the previous pulse and the current pulse output from the first oscillator and stopping the CPU when the interval exceeds a predetermined period set in the period setter; A monitoring stop unit for monitoring an oscillation state of the predetermined counting pulse and outputting a signal for stopping the CPU when the oscillation frequency of the predetermined counting pulse is out of a predetermined range;
A control device for a gaming machine having 3. The gaming machine control device according to claim 1, wherein the first oscillator is selected by a selection unit from a plurality of oscillators . 4.