JP4137040B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a metal thin film resistor made of a metal thin film formed on an insulating film.
A semiconductor device including a metal thin film resistor is used in, for example, a microcomputer, a camera, a video device, a communication device, a pager, a calculator, an electronic notebook, a remote controller, and a portable device in general.

In an analog integrated circuit, a resistance element is frequently used as an important element. In recent years, among resistive elements, a resistor made of a metal thin film (referred to as a metal thin film resistor) has attracted attention because of its low temperature dependency (hereinafter referred to as TCR). Examples of the material for the metal thin film resistor include chromium silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi ₂ ), chromium nitride silicide (CrSiN), and chromium silicon oxy (CrSi0). Used.

  In a semiconductor device provided with a metal thin film resistor, in order to satisfy the demand for higher integration, the metal thin film resistor is often formed with a thin film thickness of 1000 Å (angstrom) or less with the aim of higher sheet resistance.

In general, the metal thin film resistor has a problem that the resistance value varies due to the composition of the base film, the elapsed time since the base film is formed, and the like.
An object of the present invention is to achieve stabilization of the resistance value of a metal thin film resistor in a method of manufacturing a semiconductor device provided with a metal thin film resistor.

  A manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device provided with a metal thin film resistor on an insulating film, and a metal thin film for forming a metal thin film resistor is formed on the insulating film. Before, an etching process is performed on the insulating film by an Ar sputter etching technique.

  A specific manufacturing method to which the present invention is applied is as follows: (A) a step of forming a wiring pattern on the base insulating film corresponding to the regions where both ends of the metal thin film resistor are to be formed; (B) on the wiring pattern; (C) forming a connection hole in the insulating film corresponding to the formation planned region of both ends of the metal thin film resistor and the wiring pattern; D) forming a metal thin film on the insulating film including inside the connection hole; and (E) forming a metal thin film resistor by patterning the metal thin film so that the metal thin film remains in the connection hole. The insulating film is etched by an Ar sputter etching technique before forming the metal thin film in the step (D).

The thickness of the metal thin film formed for the metal thin film resistor is 5 to 1000 mm, preferably 20 to 500 mm.
It is preferable to continuously form the metal thin film without breaking the vacuum after the etching process for the insulating film by the Ar sputter etching technique.

  The amount of the etching process by the Ar sputter etching technique is, for example, a film thickness of 25 mm or more in terms of the thermal oxide film etching amount. However, the etching amount for the insulating film by the Ar sputter etching technique is not limited to this.

  In the structure in which the metal thin film resistor and the metal wiring are in direct contact, the contact resistance largely fluctuates due to a relatively low temperature heat treatment at about 300 to 400 ° C. Therefore, TiW or the like is between the metal thin film resistor and the metal wiring. It is preferable to form a barrier film. Therefore, the wiring pattern in contact with the metal thin film resistor is composed of a metal material pattern and a refractory metal film formed on at least the upper surface thereof, or a polysilicon pattern and a refractory metal film formed on at least the upper surface thereof. It is preferable to be configured.

The refractory metal film formed on the upper surface of the wiring pattern is suitably formed to a film thickness of, for example, 500 to 3000 mm.
In the step (D), after forming the metal thin film in an oxygen-free atmosphere, a metal nitride film is continuously formed on the metal thin film in the oxygen-free atmosphere, and in the step (E), the metal nitride film and The metal thin film may be patterned to form a laminated pattern composed of a metal nitride film pattern and the metal thin film resistor.
A suitable nitrogen partial pressure in the sputtering gas for forming the metal nitride film is 18 to 90%.
The wiring pattern is preferably the uppermost wiring pattern.

  In the present invention, before the metal thin film for forming the metal thin film resistor is formed on the insulating film, the insulating film is etched by the Ar sputter etching technique. It is possible to reduce the dependency of the sheet resistance on the base film and the change with time, and to stabilize the resistance value of the metal thin film resistor.

  In this specific manufacturing method, after forming a wiring pattern and a connection hole (steps (A) to (C)), a metal thin film resistor is formed, and the metal thin film resistor and the wiring pattern are electrically connected within the connection hole. Since the connection is formed (steps (D) and (E)), it is not necessary to perform patterning by the wet etching technique after forming the metal thin film resistor. Furthermore, compared to the method of forming a wiring pattern on the metal thin film resistor, the contact surface of the metal thin film resistor with the wiring pattern is not exposed to the atmosphere, and the surface oxide film removal treatment for the metal thin film resistor is performed. In addition, a semiconductor having a metal thin film resistor having a film thickness as described above can be obtained with good electrical connection between the metal thin film resistor and the wiring pattern without forming a barrier film for etching prevention. Even if it is applied to the apparatus and the manufacturing method thereof, the metal thin film resistor can be miniaturized and the resistance value can be stabilized without increasing the number of steps.

  As a wiring pattern, a metal material pattern and a refractory metal film formed on at least the upper surface thereof are formed, or a polysilicon pattern and a refractory metal film formed on at least the upper surface thereof are formed. Thus, a refractory metal film can be interposed between the metal thin film resistor and the metal wiring or the polysilicon wiring without adding a manufacturing process, so that the contact resistance variation between the metal thin film resistor and the wiring pattern varies. And the accuracy of the resistance value and the yield can be improved.

  Further, when the wiring pattern is formed of a metal material pattern and a refractory metal film, the refractory metal as an antireflection film formed on the upper surface of the metal material pattern is connected to the metal material pattern and the metal thin film resistor. If the wiring pattern is formed of a polysilicon pattern and a refractory metal film, the refractory metal film formed for the purpose of lowering the resistance of the polysilicon pattern may be used as a barrier film. If it is used as a barrier film between the silicon pattern and the metal thin film resistor, the manufacturing process will not increase, so the contact resistance between the metal thin film resistor and the wiring pattern can be stabilized while preventing an increase in manufacturing cost. Can be made.

  In the case of forming a refractory metal film on the upper surface of the wiring pattern, if the film thickness is 500 to 3000 mm, the insulating film is etched by Ar sputter etching technique before forming the metal thin film in step (D). When the process is performed, the refractory metal can be sufficiently left in the connection hole.

  In step (D), after forming the metal thin film in an oxygen-free atmosphere, a metal nitride film is continuously formed on the metal thin film in the oxygen-free atmosphere. In step (E), the metal nitride film and the metal thin film are formed. If patterning is performed to form a laminated pattern consisting of a metal nitride film pattern and a metal thin film resistor, oxidation of the upper surface of the metal thin film resistor can be eliminated, and the resistance value of the metal thin film resistor is stabilized and accurate. Can be improved.

  If the wiring pattern connected to the metal thin film resistor is the uppermost wiring pattern, for example, the layout of the metal thin film resistor can be changed by changing the layout of the metal thin film resistor and the uppermost wiring pattern. The degree can be improved.

  In addition, by disposing the metal thin film resistor on the insulating film formed on the uppermost wiring pattern, a final protective film made of an insulating material is formed on the upper layer of the metal thin film resistor. Compared with the case where an insulating film other than the final protective film is formed on the upper layer, the film thickness of the insulating material on the metal thin film resistor can be reduced to reduce the film thickness variation. As a result, when the metal thin film resistor is subjected to trimming by irradiating a laser to the metal thin film resistor, the dispersion of laser interference in the insulating material on the metal thin film resistor is reduced to reduce the laser energy given to the metal thin film resistor. The variation can be reduced, and the trimming accuracy can be improved. Furthermore, the heat dissipation capability can be improved against the temperature rise of the metal thin film resistor caused by laser irradiation during the trimming process.

  1 and 2 are process cross-sectional views for explaining an embodiment of the manufacturing method. In FIG. 1 and FIG. 2, transistor elements, capacitor elements, and the like are formed on the same substrate, but illustration of these elements is omitted. First, an example of a semiconductor device manufactured by this method will be described with reference to FIG.

  An element isolation oxide film 3 is formed on the silicon substrate 1. A first interlayer insulating film (base insulating film) 5 made of a BPSG film or a PSG (phospho silicate glass) film is formed on the silicon substrate 1 including the region where the element isolation oxide film 3 is formed. On the first interlayer insulating film 5, a wiring pattern 11 made of a metal material pattern 7 and a refractory metal film 9 formed on the surface of the metal material pattern 7 is formed. The metal material pattern 7 is formed of, for example, an AlSiCu film. The refractory metal film 9 is formed of, for example, a TiN film and functions as an antireflection film / barrier film.

  A second interlayer insulating film (insulating) comprising a plasma CVD oxide film 13, an SOG (spin on glass) film 15, and a plasma CVD oxide film 17 in this order from the lower layer side on the first interlayer insulating film 5 including the formation region of the wiring pattern 11. Film) 19 is formed. Connection holes 21 are formed in the second interlayer insulating film 19 corresponding to both ends of the metal thin film resistor and the wiring pattern 11.

A CrSi thin film resistor (metal thin film resistor) 23 is formed on the second interlayer insulating film 19 from the region between the connection holes 21 and 21 to the inner wall of the connection hole 21 and the wiring pattern 11. Both ends of the CrSi thin film resistor 23 are electrically connected to the wiring pattern 11 in the connection hole 21.
On the second interlayer insulating film 19 including the region where the CrSi thin film resistor 23 is formed, a passivation film 29 is formed as a final protective film consisting of a silicon oxide film 25 on the lower layer side and a silicon nitride film 27 on the upper layer side.

With reference to FIG.1 and FIG.2, one Example of a manufacturing method is described.
(1) A first interlayer made of a BPSG film or a PSG film is formed on a wafer-like silicon substrate 1 on which an element isolation oxide film 3 and transistor elements (not shown) have been formed using, for example, an atmospheric pressure CVD apparatus. The insulating film 5 is formed to a thickness of about 8000 mm. Thereafter, heat treatment such as reflow is performed to flatten the surface of the first interlayer insulating film 5 (see FIG. 1A).

(2) For example, using a DC magnetron sputtering apparatus, a wiring metal film 31 made of an AlSiCu film is formed on the first interlayer insulating film 5 to a thickness of about 5000 mm, and further, it is a known technique. A refractory metal film 33 as an antireflection film, here a TiN film, is continuously formed in a vacuum to a thickness of about 800 mm in vacuum (see FIG. 1B). Here, the refractory metal film 33 finally functions as a barrier film for stabilizing the contact resistance between the metal material pattern formed from the wiring metal film 31 in a subsequent process and the metal thin film resistor. Therefore, it is preferable to continuously form the wiring metal film 31 and the refractory metal film 33 in a vacuum.

(3) The refractory metal film 33 and the wiring metal film 31 are patterned by a known photolithography technique and etching technique to form a wiring pattern 11 including the metal wiring pattern 7 and the refractory metal film 9 (FIG. 1 (c)). At this time, since the refractory metal film 33 functioning as an antireflection film is formed on the wiring metal film 31, the resist pattern for demarcating the formation area of the wiring pattern 11 is minimized. Can be suppressed.

  At this stage, the metal thin film resistor is not formed as in the prior art, and the base film of the wiring pattern 11 is formed by the first interlayer insulating film 5, so that the refractory metal film 33 and the wiring are formed. The metal film 31 can be patterned with sufficient over-etching by the dry etching technique, and there is no need to apply the patterning by the wet etching technique, which has been a problem of the prior art. It will not affect the conversion.

(4) A plasma CVD oxide film 13 is formed to a thickness of about 6000 mm on the first interlayer insulating film 5 including the formation region of the wiring pattern 11 by, for example, a plasma CVD method (see FIG. 1D).
(5) The SOG film 15 is formed on the plasma CVD oxide film 13 and planarized by performing the SOG coating process and etch back process, which are known techniques, and then the diffusion of components from the SOG film 15 is performed. A plasma CVD oxide film 17 for preventing the film is formed to a thickness of about 2000 mm, and a second interlayer insulating film 19 composed of the plasma CVD oxide film 13, the SOG film 15, and the plasma CVD oxide film 17 is formed (FIG. 1). (See (e)).

(6) A resist pattern 35 for forming a connection hole in the second interlayer insulating film 19 is formed by a known photoengraving technique corresponding to the formation planned regions at both ends of the metal thin film resistor and the wiring pattern 11. In the resist pattern 35, openings 36 are formed corresponding to the regions where the metal thin film resistors are to be formed and the wiring pattern 11 (see FIG. 1F).

(7) Conditions of RF power: 700 W (watts), Ar: 500 sccm (standard cc / min), CHF ₃ : 500 sccm, CF ₄ : 500 sccm, pressure: 3.5 Torr (torr) by, for example, a parallel plate type plasma etching apparatus Then, the second interlayer insulating film 19 is selectively removed using the resist pattern 35 as a mask, and a connection hole 21 is formed in the second interlayer insulating film 19. At the bottom of the connection hole 21, the refractory metal film 9 as an antireflection film / barrier film remains with a thickness of about 600 mm.
Thereafter, the resist pattern 35 is removed (see FIG. 2G).

  Here, after the connection hole 21 is formed, a by-product removal step during etching attached to the side wall of the connection hole 21 or the like may be performed. Further, in order to improve the step coverage of the metal thin film resistor inside the connection hole 21, the shape of the connection hole 21 is obtained by taper etching by changing etching conditions, etching processing combining wet etching technology and dry etching technology, or the like. Improvements may be made.

  In the step (7), the etching rate of the refractory metal film 9 relative to the etching rate of the second interlayer insulating film 19 can be sufficiently suppressed by optimizing the plasma etching conditions. The film thickness of the refractory metal film 9 remaining at the bottom of 21 can be made larger than in this embodiment. Furthermore, the remaining film thickness of the refractory metal film 9 after the connection hole 21 is formed can be secured while the film thickness at the time of forming the refractory metal film 9 is kept low. As described above, since the step (7) for forming the connection hole 21 is performed at a stage where the metal thin film resistor is not formed, the connection hole 21 is not subjected to any restrictions due to the thinness of the metal thin film resistor. Processing is possible, and the pursuit of miniaturization by applying dry etching technology is sufficiently possible.

(8) For example, in the Ar sputter etching chamber of the multi-chamber sputtering apparatus, in the vacuum, the connection hole 21 under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr (millitorr), treatment time: 20 seconds An Ar sputter etching process is performed on the surface of the second interlayer insulating film 19 including the inside. This etching condition is the same as that for etching a thermal oxide film formed in a wet atmosphere at 1000 ° C. by about 50 mm. The thickness of the refractory metal film 9 remaining at the bottom of the connection hole 21 after this treatment was about 500 mm.

  Subsequently, after completion of the Ar sputter etching, a CrSi thin film (metal thin film) 37 for the metal thin film resistor is continuously formed without breaking the vacuum. Here, after a semiconductor wafer is transferred from an Ar sputter etching chamber to a sputter chamber equipped with a CrSi target, a Si / Cr = 80/20 wt% (weight percent) CrSi target is used and a DC power of 0.7 kW ( (Kilowatt), Ar: 85 sccm, pressure: 8.5 mTorr, processing time: 9 seconds. The CrSi thin film 37 is formed on the entire surface of the second interlayer insulating film 19 including the inside of the connection hole 21 to a thickness of about 50 mm. It formed (refer FIG.2 (h)).

Thus, before forming the CrSi thin film 37 for the metal thin film resistor, the Ar sputtering process is performed on the second interlayer insulating film 19 including the inside of the connection hole 21 to clean the inside of the connection hole 21. In addition, an extremely small amount of the natural oxide film formed on the surface of the refractory metal film 9 at the bottom of the connection hole 21 can be removed. Thereby, a favorable electrical connection between the wiring pattern 11 and the CrSi thin film 37 can be achieved.
Furthermore, by performing the Ar sputter etching process, the dependency of the CrSi thin film resistor formed from the CrSi thin film 37 in the subsequent process on the base film can be improved. This effect will be described later.

(9) A resist pattern 39 for defining a formation region of the metal thin film resistor is formed on the CrSi thin film 37 by photolithography. For example, using a RIE (Reactive Ion Etching) apparatus, the CrSi thin film 37 is patterned using the resist pattern 39 as a mask to form the CrSi thin film resistor 23 (see FIG. 2I).

(10) The resist pattern 39 is removed (see FIG. 2 (j)). Here, since the CrSi thin film resistor 23 is electrically connected to the wiring pattern 11 in the connection hole 21, in order to make an electrical connection on the upper surface of the metal thin film resistor as in the prior art, a hydrofluoric acid aqueous solution is used. It is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 23.

(11) A silicon oxide film 25 and a silicon nitride film 27 as a passivation film are sequentially formed on the second interlayer insulating film 19 including the formation region of the CrSi thin film resistor 23 by, for example, plasma CVD. Thus, the semiconductor device manufacturing process is completed (see FIG. 2K).

  According to the above embodiment, after the wiring pattern 11 and the connection hole 21 are formed, the CrSi thin film resistor 23 is formed, and the electrical connection between the CrSi thin film resistor 23 and the wiring pattern 11 is formed in the connection hole 21. It is not necessary to perform patterning by the wet etching technique after patterning the CrSi thin film resistor 23.

Further, since the contact surface of the CrSi thin film resistor 23 with the wiring pattern 11 is not exposed to the atmosphere, the surface oxide film removal treatment and the etching prevention barrier film formation on the CrSi thin film resistor 23 are not performed. A good electrical connection between the CrSi thin film resistor 23 and the wiring pattern 11 can be obtained stably.
Thereby, miniaturization of the CrSi thin film resistor 23 and stabilization of the resistance value can be realized without increasing the number of steps regardless of the film thickness of the CrSi thin film resistor 23.

  Further, since the refractory metal film 9 functioning as a barrier film is interposed between the CrSi thin film resistor 23 and the metal material pattern 7, variation in contact resistance between the CrSi thin film resistor 23 and the wiring pattern 11 is reduced. Thus, the accuracy of the resistance value and the yield can be improved.

  Further, the refractory metal film 9 also functions as a barrier film and antireflection film, and the refractory metal film 9 can be formed without increasing the number of manufacturing steps compared to the prior art, so that the manufacturing cost is increased. The contact resistance between the metal thin film resistor and the wiring pattern can be stabilized.

  With reference to FIG. 3 and FIG. 4, the result of having investigated the characteristic of the metal thin film resistor formed by the structure similar to the said Example is shown. FIG. 3 shows the relationship between the sheet resistance and the film thickness of the metal thin film resistor, the vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the CrSi film thickness (Å). FIG. 4 shows the relationship between the value (σ / AVE) obtained by dividing the standard deviation (σ) of the sheet resistance of the metal thin film resistor at 63 locations in the wafer surface by the average value (AVE) and the CrSi film thickness. The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å).

The conditions for forming the metal thin film resistor are as follows.
Using a multi-chamber sputtering apparatus, the volume time is adjusted for two types of DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, target: Si / Cr = 50/50 wt% and 80/20 wt%. Thus, a sample was prepared with a CrSi thin film having a thickness of 25 to 500 mm. In addition, about the sample of Si / Cr = 50/50 wt%, the film thickness of 500 mm is not produced.

Further, the Ar sputter etching process before forming the CrSi thin film was performed using the multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, and processing time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
In this sample, an AlSiCu film having a thickness of 5000 mm is used as the lower layer metal wiring connected to the metal thin film resistor, and a TiN film on the AlSiCu film is formed at the bottom of the connection hole between the AlSiCu film and the CrSi thin film. Adopted a structure that is not.

Sheet resistance was measured by applying a voltage of 1V across one metal thin film resistor of 20 strips with a width of 0.5 μm (micrometer) and a length of 50 μm arranged at intervals of 0.5 μm. The two-terminal method for measuring the current value was performed.
The plane dimension of the connection hole connecting the metal wiring and the CrSi thin film resistor was 0.6 μm × 0.6 μm.

  As shown in FIG. 3, regardless of the composition of the target (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%), the film thickness ranges from a thickness of 200 mm or more to a very thin film thickness of 25 mm. It can be seen that the linearity of the sheet resistance is maintained, and a metal thin film resistor having a fine dimension that cannot be formed by the conventional technique can be formed in a thin film thickness.

  Moreover, even if it sees FIG. 4 which shows the variation of the sheet resistance in 63 places in a wafer surface, the variation in resistance value of both targets (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%) It can be seen that the film is hardly affected by the film thickness, and the variation in resistance value is very small and stable. From this, if the structure of this invention is employ | adopted, a very fine metal thin film resistor pattern can be formed stably irrespective of the film thickness of a metal thin film resistor.

  FIG. 5 shows the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor when the Ar sputter etching process is performed and not performed before forming the metal thin film for the metal thin film resistor. It is a figure which shows the relationship with the time which passed since (A) when it does, (B) shows the case where it does not perform. In FIG. 5, the vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the elapsed time (time) after forming the base film.

  As a sample of FIG. 5, two silicon wafers of a plasma SiN film and a plasma NSG (non-doped silicate glass) film formed to a film thickness of 2000 mm as a base film by a plasma CVD method were prepared and formed on these silicon wafers. Using a CrSi thin film resistor, the sheet resistance of the CrSi thin film resistor was measured by the four-terminal method.

The plasma SiN film as a base film is formed using a parallel plate type plasma CVD apparatus under conditions of temperature: 360 ° C., pressure: 5.5 Torr, RF power: 200 W, SiH ₄ : 70 sccm, N ₂ : 3500 sccm, NH ₃ : 40 sccm. Formed with.
The plasma NSG film was formed using a parallel plate plasma CVD apparatus under the conditions of temperature: 400 ° C., pressure: 3.0 Torr, RF power: 250 W, SiH ₄ : 16 sccm, N ₂ O: 1000 sccm.

  The CrSi thin film resistor is formed using a multi-chamber sputtering apparatus under the conditions of Si / Cr = 80/20 wt% target, DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 13 seconds. By performing the treatment, a film thickness of 100 mm was formed.

  The sample subjected to the Ar sputter etching process was performed using the multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, and processing time: 80 seconds. This is a process corresponding to etching and removing a thermal oxide film formed at 1000 ° C. in a wet atmosphere by 200 mm.

As shown in (B), when the Ar sputter etching process is not performed before the formation of the CrSi thin film, it can be seen that the sheet resistance is greatly different depending on the difference in the underlying film (on the SiN film and on the NSG film). Furthermore, it can be seen that the time elapsed from the formation of the base film to the formation of the CrSi thin film resistor is greatly affected.
On the other hand, as shown in (A), when Ar sputter etching is performed, it can be seen that both the type of the underlying film and the elapsed time have little effect on the sheet resistance of the CrSi thin film resistor.

  From this, after performing Ar sputter etching process, by forming a metal thin film for metal thin film resistors continuously in vacuum, depending on the elapsed time from the previous process, the difference in the underlying film for each product, etc. It can be seen that the variation in the generated resistance value can be greatly improved.

  FIG. 6 is a diagram showing the relationship between the amount of Ar sputter etching and the sheet resistance. The vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the etching amount (in terms of thermal oxide film etching amount) (Å). For the sample of FIG. 6, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 5 were used as the base film and the CrSi thin film resistor. In addition, after carrying out Ar sputter etching with respect to the plasma NSG film which passed one week after film-forming, the CrSi thin film resistor was formed on the plasma NSG film. The Ar sputter etching was performed under the same conditions as the sample of FIG. 5 except for the etching amount. And it adjusted so that it might be set to 0 (no Ar sputter etching), 25 (s), 50 (s), 100 (s), 200 (s), 400 (s), and 1000 (s) in conversion of the etching amount of the thermal oxide film formed in the wet atmosphere. The sheet resistance of the CrSi thin film resistor was measured by the 4-terminal method.

  From the results of FIG. 6, it is understood that the effect of stabilizing the resistance value of the CrSi thin film resistor can be obtained if the Ar sputter etching is performed by a film thickness of 25 mm or more in terms of the etching amount of the thermal oxide film formed in the wet atmosphere. It was. In FIG. 6, the sample is manufactured only up to an etching amount of 1000 mm in terms of the thermal oxide film etching amount in terms of the Ar sputter etching condition, but a film thickness larger than 1000 mm in terms of the thermal oxide film etching amount. Even if only etching is performed, if the base film remains in the formation region of the metal thin film resistor, the effect of the Ar sputter etching can be expected to be obtained.

Furthermore, it has been found that the effect of the Ar sputter etching process affects not only the influence of the base but also the stability of the resistance value of the CrSi thin film itself.
FIG. 7 shows the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% after the formation of the CrSi thin film and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance (R0) immediately after formation. The vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hours).

For the sample of FIG. 7, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 5 were used as the base film and the CrSi thin film resistor.
For Ar sputter etching, no treatment is performed (without Ar etching), thermal oxide film conversion: 100 liters with a processing time of 40 seconds (Ar etching: 100 liters), thermal oxide film conversion with a processing time of 80 seconds: 200 liters Three types (Ar etch: 200 mm) were prepared.

In the sample not subjected to the Ar sputter etching process (without Ar etching), the resistance value increases as time passes after the formation, and the resistance value fluctuates by 3% or more when left for 300 hours or more. I understand.
On the other hand, in the samples subjected to the Ar sputter etching process (Ar etch: 100 mm and Ar etch: 200 mm), the rate of change in resistance value is greatly reduced, and the sheet resistance immediately after formation is reduced even after being left for 300 hours or longer. There was no deviation from ± 1%.
Further, when comparing Ar etch: 100 Å with Ar etch: 200 Å, it was found that the effect of the Ar sputter etching amount is small, and the effect is small with a small etching amount.

As described above, the effects of the present invention on the influence of the base film on the sheet resistance and the influence of the air standing time have been described with reference to FIGS. 3 to 7. These effects are obtained when the target used as a sample is Si / It is not limited to Cr = 50/50 wt% or 80/20 wt% CrSi thin film resistor. In addition, the same effect as the above is observed in all of the CrSi thin film and the CrSiN film formed with the target of Si / Cr = 50/50 to 90/10 wt%.
Also, the Ar sputter etching method is not limited to the DC bias sputter etching method used this time.

  FIG. 8 is a diagram showing the results of examining the fluctuations in the metal thin film resistance and the metal wiring contact resistance caused by the heat treatment for the sample in which the refractory metal film is left at the bottom of the connection hole when the connection hole is formed and the sample that is completely removed. It is. The vertical axis represents the value normalized by the contact resistance value before heat treatment, and the horizontal axis represents the number of heat treatments.

As a sample of FIG. 8, by adjusting the dry etching time at the time of forming the connection hole, a sample in which about 500 mm of the refractory metal film at the bottom of the connection hole was left and a sample in which the complete removal was made were prepared.
A TiN film was used as the refractory metal film.
The CrSi thin film resistor was formed to a thickness of 50 mm under the conditions of Si / Cr = 80/20 wt%, DC power: 0.7 KW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 6 seconds.
The Ar sputter etching process before forming the CrSi thin film was performed under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, and processing time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
The plane dimension of the connection hole was 0.6 μm × 0.6 μm. A four-terminal method was used as the contact resistance measurement method.

About said sample, it was investigated how contact resistance changed by adding heat processing for 30 minutes in 350 degreeC and nitrogen atmosphere.
A sample (with TiN) having a TiN film at the bottom of the connection hole hardly changes from the contact resistance before the heat treatment even if the heat treatment is added twice. On the other hand, in the sample from which the TiN film was completely removed (without TiN), the contact resistance fluctuated by 20% or more compared to before the heat treatment due to the addition of two heat treatments. This means that the TiN film has a function as a barrier film that prevents resistance fluctuation due to the interaction between the CrSi thin film and the metal wiring.

  The presence of the TiN film between the CrSi thin film resistor and the metal wiring makes it possible to extremely reduce fluctuations in contact resistance due to heat treatment performed in the manufacturing process, such as sintering and CVD, and to perform assembly work as a subsequent process. Fluctuations in contact resistance due to heat treatment such as soldering. As a result, the contact resistance as set can be stably obtained, and fluctuations in the contact resistance before and after assembly can be prevented, so that the accuracy of the product and the yield can be improved.

In the embodiment of the manufacturing method described with reference to FIGS. 1 and 2, the wiring metal film 31 and the refractory metal film 33 are continuously formed in a vacuum in the step (2). The invention is not limited to this.
For example, when the wiring metal film 31 is formed, and once exposed to the atmosphere, the refractory metal film 33 is formed, the wiring metal film is affected by the natural oxide film formed on the surface of the wiring metal film 31. It becomes difficult to ensure electrical conduction between the film 31 and the refractory metal film 33.

  In such a case, the connection hole 21 is formed in the second interlayer insulating film 19 on the wiring pattern 11 made of the metal material pattern 7 and the refractory metal film 9 formed by patterning the wiring metal film 31 and the refractory metal film 33. At the stage of formation, the entire refractory metal film 9 at the bottom of the connection hole 21 is removed, whereby electrical connection between the wiring pattern 11 and the CrSi thin film resistor 23 can be obtained.

In the step (2), the refractory metal film 33 functioning as an antireflection film / barrier film is formed to a thickness of 800 mm, but the present invention is not limited to this.
In general, the refractory metal film as the antireflection film is formed to a thickness of 500 mm or less. However, in the method of manufacturing a semiconductor device of the present invention, the refractory metal film 9 as the barrier film remains at the bottom of the connection hole 21. In the case where it is desired to do so, the film of the refractory metal film 9 is formed by over-etching when the connection hole 21 is formed (see step (7) above) or Ar sputter etching treatment when forming the metal thin film (see step (8) above). Since some belief occurs, it is preferable to form the film with a thickness of 500 mm or more in order to stably obtain the function as a barrier film.

  However, as described above, by optimizing the etching conditions for forming the connection holes 21 and the Ar sputter etching conditions, even if the film thickness of the refractory metal film 9 is 500 mm or less, the film verification of the refractory metal film 9 is minimized. It is possible to exhibit the function as a barrier film while suppressing the film thickness to a minimum.

  In the step (8), Ar sputter etching is performed immediately before the formation of the CrSi thin film 37. If the refractory metal film 9 as the barrier film remains at the bottom of the connection hole 21, TiN Since the refractory metal film 9 made of a film does not form a natural oxide film as strong as the AlSiCu film even when exposed to the atmosphere, the CrSi thin film 37 and the wiring pattern 11 can be electrically connected without performing the Ar sputter etching process. Obtainable. However, as described above, since the stability of the resistance value of the CrSi thin film resistor 23 can be improved by performing the Ar sputter etching process immediately before the formation of the CrSi thin film 37, it is preferable to perform the Ar sputter etching process. .

  In the above embodiment, the second interlayer insulating film 19 is flattened by using the formation of the SOG film 15 and the etch-back technique, but this is the insulating film that is the base of the metal thin film resistor. It is not limited to. Examples of the insulating film that forms the base of the metal thin film resistor include an insulating film that has been flattened using CMP (chemical mechanical polish), which is a known technique, and a plasma CVD oxide film that has not been flattened. Other insulating films may be used. However, since many analog resistance elements are used not only in the TCR but also in a configuration in which pairability and specific accuracy are important, in particular, the metal thin film resistor constituting the semiconductor device of the present invention. When the body is applied to an analog resistance element, it is preferable that the insulating film serving as the base of the metal thin film resistor is subjected to a planarization process.

  FIG. 9 is a cross-sectional view for explaining an embodiment of a semiconductor device having a structure different from that of the embodiment described above, and a method for manufacturing the same, as an insulating film serving as a base of the metal thin film resistor. In FIG. 9, transistor elements, capacitor elements, and the like are formed over the same substrate, but illustration of these elements is omitted. Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

A wiring pattern 11 including an element isolation oxide film 3, a first interlayer insulating film 5, a metal material pattern 7, and a refractory metal film 9 is formed on the silicon substrate 1.
A second interlayer insulating film 44 made of an SOG film is formed on the first interlayer insulating film 5 including the region where the wiring pattern 11 is formed. Connection holes 21 are formed in the second interlayer insulating film 19 corresponding to both ends of the metal thin film resistor and the wiring pattern 11.
A CrSi thin film resistor 23 is formed on the second interlayer insulating film 44 from the region between the connection holes 21 and 21 to the inner wall of the connection hole 21 and the wiring pattern 11. A passivation film 29 composed of a silicon oxide film 25 and a silicon nitride film 27 is formed on the second interlayer insulating film 44 including the formation region of the CrSi thin film resistor 23.

  The method for forming the second interlayer insulating film 44 will be described. After the SOG is applied to a thickness of, for example, 4000 mm, the second interlayer insulating film 44 is formed by performing a heat treatment. Thereby, the step on the surface of the second interlayer insulating film 44 made of the SOG film can be reduced.

  FIG. 10 is a cross-sectional view for explaining an embodiment of a semiconductor device having a structure different from that of the above-described embodiment in which the insulating film serving as the base of the metal thin film resistor and the manufacturing method thereof. In FIG. 10, transistor elements, capacitor elements, and the like are formed on the same substrate, but illustration of these elements is omitted. Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

This embodiment differs from the embodiment described with reference to FIG. 2K and the embodiment described with reference to FIG. 9 in that the second interlayer insulating film 46 is planarized by the CMP method. is there. The material of the second interlayer insulating film 46 is, for example, a plasma CVD oxide film. Thereby, the flatness of the second interlayer insulating film 46 which is the base film of the CrSi thin film resistor 23 can be further improved.
An example of a method for forming the second interlayer insulating film 46 will be described. A plasma CVD oxide film is formed to a thickness of about 10,000 mm, and is polished and planarized to a thickness of about 4000 mm by a CMP method.

  In addition, a CVD insulating film formed by HDP (high-density-plasma) -CVD may be used as an insulating film serving as a base for the CrSi thin film resistor. For example, an HDP-CVD film formed to a thickness of about 8000 mm is etched back to a thickness of about 4000 mm, whereby an insulating film having good flatness can be formed.

  In the above embodiment, the passivation film 29 is formed on the CrSi thin film resistor 23. However, the present invention is not limited to this. For example, to form a second-layer metal wiring. The film on the CrSi thin film resistor 23, such as an interlayer insulating film, may be any insulating film.

  FIG. 11 is a process cross-sectional view for explaining still another embodiment of the manufacturing method. FIG. 11D shows still another embodiment of the semiconductor device. In FIG. 11, transistor elements, capacitor elements, and the like are formed over the same substrate, but illustration of these elements is omitted. Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. First, an embodiment of a semiconductor device will be described with reference to FIG.

  On the silicon substrate 1, an element isolation oxide film 3, a first interlayer insulating film 5, a wiring pattern 11 comprising a metal material pattern 7 and a refractory metal film 9, a plasma CVD oxide film 13, an SOG film 15 and a plasma CVD oxide film A second interlayer insulating film 19 made of 17 is formed. Connection holes 21 are formed in the second interlayer insulating film 19 corresponding to both ends of the metal thin film resistor and the wiring pattern 11.

A CrSi thin film resistor 23 is formed on the second interlayer insulating film 19 from the region between the connection holes 21 and 21 to the inner wall of the connection hole 21 and the wiring pattern 11. A CrSiN film (metal nitride film) 41 is formed on the upper surface of the CrSi thin film resistor 23. CrSiO is not formed between the CrSi thin film resistor 23 and the CrSiN film 41.
Although illustration is omitted, an interlayer insulating film or a passivation film is formed on the second interlayer insulating film 19 including the region where the CrSi thin film resistor 23 is formed.

An embodiment of the manufacturing method will be described with reference to FIG.
(1) On the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 3 has been completed by the same steps as the steps (1) to (7) described with reference to FIGS. A first interlayer insulating film 5, a wiring pattern 11 made of a metal wiring pattern 7 and a refractory metal film 9, and a second interlayer insulating film 19 made of a plasma CVD oxide film 13, an SOG film 15, and a plasma CVD oxide film 17 are formed. Then, a connection hole 21 is formed in the second interlayer insulating film 19 (see FIG. 11A).

(2) By the same step as the above step (8) described with reference to FIG. 2 (h), for example, in the Ar sputter etching chamber of the multi-chamber sputtering apparatus, in the vacuum, the second interlayer including the inside of the connection hole 21 An Ar sputter etching process is performed on the surface of the insulating film 19, and a CrSi thin film 37 for a metal thin film resistor is continuously formed without breaking the vacuum after completion of the Ar sputter etching.

Further, after the CrSi thin film 37 is formed, a CrSiN film 43 is formed on the CrSi thin film 37 continuously without breaking the vacuum. Here, the Si / Cr = 80/20 wt% CrSi target used in the formation of the CrSi thin film 37 is used, DC power: 0.7 kW (kilowatt), Ar + N ₂ (mixed gas of argon and nitrogen): 85 sccm, pressure Was processed under the conditions of: 8.5 mTorr, processing time: 6 seconds, and a CrSiN film 43 having a thickness of about 50 mm was formed on the CrSi thin film 37 (see FIG. 11B).

(3) Similar to the above step (9) described with reference to FIG. 2 (i), a resist pattern 39 for defining the formation region of the metal thin film resistor on the CrSiN film 43 is formed by photolithography. Then, using a RIE (reactive ion etching) apparatus, the CrSiN film 43 and the CrSi thin film 37 are patterned using the resist pattern 39 as a mask to form a laminated pattern composed of the CrSiN film 41 and the CrSi thin film resistor 23 ( (Refer FIG.11 (c)).

(4) The resist pattern 39 is removed (see FIG. 11D). Similar to the above embodiment, since the CrSi thin film resistor 23 is electrically connected to the wiring pattern 11, the metal oxide film removal process on the surface of the CrSi thin film resistor 23 with a hydrofluoric acid aqueous solution as in the prior art. There is no need to do. Furthermore, since the upper surface of the CrSi thin film resistor 23 is covered with the CrSiN film 41, the upper surface of the CrSi thin film resistor 23 is not oxidized even when exposed to an atmosphere containing oxygen, such as air.
Thereafter, although not shown, an interlayer insulating film or a passivation film is formed on the second interlayer insulating film 19 including the regions where the CrSi thin film resistor 23 and the CrSiN film 41 are formed.

In general, a metal thin film has high reactivity with oxygen, and it is known that the resistance value fluctuates when the metal thin film is left for a long time in a state exposed to the atmosphere.
In this embodiment, the CrSiN film 41 is formed on the upper surface of the CrSi thin film resistor 23 to prevent the upper surface of the CrSi thin film resistor 23 from being exposed to the air and changing the resistance value of the CrSi thin film resistor 23. ing. Here, when the CrSi thin film 37 for forming the CrSi thin film resistor 23 is formed, the electrical connection between the CrSi thin film 37 and the wiring pattern 11 is completed. Even if a thin film is formed, there is no influence on the characteristics.

FIG. 12 is a diagram showing the relationship between the N ₂ partial pressure of the gas for forming the CrSiN film and the resistivity of the CrSiN film, where the vertical axis represents resistivity ρ (mohm · cm (mohm · cm)), and the horizontal axis represents N ₂ partial pressure (%) is indicated. Here, the N ₂ partial pressure of Ar + N ₂ gas is adjusted under the conditions of target: Si / Cr = 50/50 wt%, DC power: 0.7 kW, Ar + N ₂ : 85 sccm, pressure: 8.5 mTorr, treatment time: 6 seconds. Thus, a CrSiN film was formed.

The CrSiN film formed by reactive sputtering with an N ₂ partial pressure of 18% or more is 10 times higher than when a gas not containing N ₂ is used at all (N ₂ partial pressure is 0%). Resistivity is shown. Therefore, if the CrSiN film is formed by setting the N ₂ partial pressure to 18% or more, even if the CrSiN film is directly formed on the CrSi thin film resistor, the resistance value of the entire CrSi thin film resistor is CrSi. The thin film is determined, and the CrSiN film has little influence on the resistance value. Here, the upper limit of the N ₂ partial pressure is about 90%. If the N ₂ partial pressure is set to be larger than 90%, it is not preferable because the sputtering rate is significantly reduced and the production efficiency is lowered.
Note that the CrSiN film itself can be used as a metal thin film resistor if the CrSiN film is formed by reactive sputtering with an N ₂ partial pressure of about 6 to 11%, for example.

  In the above embodiment, the CrSiN film 41 is formed on the CrSi thin film resistor 23. However, a CVD-based insulating film such as a silicon nitride film may be formed on the CrSi thin film resistor 23. However, a CVD chamber is not connected to a general multi-chamber sputtering apparatus, and in order to continuously form a CVD-based insulating film on the CrSi thin film resistor 23 in a vacuum, a corresponding new facility is required. It is necessary to purchase, and the production cost is greatly affected.

  As in the above embodiment, if the CrSiN film 43 is formed on the CrSi thin film 37 for the CrSi thin film resistor 23, a CrSi thin film resistor can be used by using an existing multi-chamber sputtering apparatus without purchasing a new apparatus. The CrSiN film 43 serving as the oxidation resistant cover film of the body 23 can be formed without breaking the vacuum.

  In the above embodiments, TiN films are used as the refractory metal films 9 and 33. However, the refractory metal film constituting the wiring pattern is not limited to this. For example, TiW or WSi is used. Other refractory metal films may be used.

  In the above embodiment, the present invention is applied to a semiconductor device having a single wiring pattern 11 as a metal wiring. However, the present invention is not limited to this, and a semiconductor device having a multilayer metal wiring structure. The present invention can also be applied to. In that case, the metal wiring in the lower layer of the metal thin film resistor for obtaining the electrical connection of the metal thin film resistor may be any number of metal wirings. When the present invention is applied to a semiconductor device having a multilayer metal wiring structure, the wiring pattern in the lower layer of the metal thin film resistor (metal wiring), that is, the wiring pattern electrically connected to the metal thin film resistor is the uppermost wiring pattern. In this case, for example, the layout of the metal thin film resistor can be changed by changing the layout of the metal thin film resistor and the uppermost wiring pattern. In addition, by disposing the metal thin film resistor on the insulating film formed on the uppermost wiring pattern, a final protective film made of an insulating material is formed on the upper layer of the metal thin film resistor. Compared with the case where an insulating film other than the final protective film is formed on the upper layer, the film thickness of the insulating material on the metal thin film resistor can be reduced to reduce the film thickness variation. As a result, when the metal thin film resistor is subjected to trimming by irradiating a laser to the metal thin film resistor, the dispersion of laser interference in the insulating material on the metal thin film resistor is reduced to reduce the laser energy given to the metal thin film resistor. The variation can be reduced, and the trimming accuracy can be improved. Furthermore, the heat dissipation capability can be improved against the temperature rise of the metal thin film resistor caused by laser irradiation during the trimming process.

  In the above embodiment, the wiring pattern 11 is formed by forming the refractory metal film 9 on the upper surface of the metal material pattern 7. However, the present invention is not limited to this, and the wiring pattern Alternatively, a metal material pattern having no refractory metal film formed on the upper surface may be used. In this case, when, for example, an Al-based alloy is used as the metal material pattern, a strong natural oxide film is formed on the surface of the metal material pattern, so a metal thin film for the metal thin film resistor is formed after the connection hole is formed. It is preferable to perform a step of removing the natural oxide film on the surface of the metal material pattern at the bottom of the connection hole before. The natural oxide film removing step may also be performed in combination with the Ar sputter etching process for the purpose of suppressing the temporal change of the resistance value of the metal thin film resistor. Further, the wiring pattern is not limited to the one containing an Al-based alloy, and may be a wiring pattern made of another metal material such as a Cu wiring formed by a so-called damascene method.

  In the above embodiment, the wiring pattern 11 for taking the potential of the CrSi thin film resistor 23 is composed of the metal material pattern 7 and the refractory metal film 9. A silicon pattern can also be used.

  FIG. 13 is a process cross-sectional view for explaining still another embodiment of the manufacturing method. FIG. 13D shows still another embodiment of the semiconductor device. In FIG. 13, transistor elements, capacitor elements, and the like are formed over the same substrate, but illustration of these elements is omitted. Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. First, an embodiment of a semiconductor device will be described with reference to FIG.

  An element isolation oxide film 3 is formed on the silicon substrate 1. A wiring pattern 49 comprising a polysilicon pattern 45 and a refractory metal film 47 formed on the polysilicon pattern 45 on an oxide film (not shown) formed on the silicon substrate 1 and on the element isolation oxide film 3. Is formed. The refractory metal film 47 is made of, for example, WSi or TiSi.

  A first interlayer insulating film 5 is formed on the silicon substrate 1 including the formation region of the wiring pattern 49 and the element isolation oxide film 3. In the first interlayer insulating film 5, connection holes 21 are formed corresponding to both end portions of the metal thin film resistor and the wiring pattern 49.

On the first interlayer insulating film 5, a CrSi thin film resistor 23 is formed from the region between the connection holes 21 and 21 to the inner wall of the connection hole 21 and the wiring pattern 49.
Although illustration is omitted, an interlayer insulating film, a metal wiring, and a passivation film are formed on the first interlayer insulating film 5 including the region where the CrSi thin film resistor 23 is formed.

An example of the manufacturing method will be described with reference to FIG.
(1) An element isolation oxide film 3 is formed on a silicon substrate 1 and an oxide film (not shown) such as a gate oxide film of a transistor is formed on the surface of the silicon substrate 1 other than the element isolation oxide film 3. 1 A polysilicon film is formed on the entire surface. For example, the polysilicon pattern 45 with reduced resistance is formed simultaneously with the formation of the gate electrode of the transistor. A refractory metal film is formed on the entire surface of the silicon substrate 1 including the polysilicon pattern 45, and the polysilicon pattern 45 is salicided to form a refractory metal film 47 such as TiSi or WSi on the polysilicon pattern 45. Then, a wiring pattern 49 is formed (see FIG. 13A).

(2) The first interlayer insulating film 5 is formed on the entire surface of the silicon substrate 1 including the wiring pattern 49 in the same manner as the step (1) described with reference to FIG. )reference).
(3) A resist pattern (not shown) for forming connection holes in the first interlayer insulating film 5 corresponding to both ends of the metal thin film resistor and the wiring pattern 49 is formed by a known photolithography technique. Using the resist pattern as a mask, the first interlayer insulating film 5 is selectively removed, and a connection hole 21 is formed in the first interlayer insulating film 5. The refractory metal film 47 remains at the bottom of the connection hole 21. Thereafter, the resist pattern is removed (see FIG. 13C).

(4) By the same step as the above steps (8) and (9) described with reference to FIGS. 2 (h) and (i), for example, in a vacuum in an Ar sputter etching chamber of a multi-chamber sputtering apparatus. An Ar sputter etching process is performed on the surface of the second interlayer insulating film 19 including the inside of the hole 21, and then a metal thin film for a metal thin film resistor is continuously formed without breaking the vacuum after the Ar sputter etching process is completed. Then, a CrSi thin film resistor 23 is formed by patterning the metal thin film (see FIG. 13D).
Thereafter, although not shown, an interlayer insulating film, a metal wiring, and a passivation film are formed on the first interlayer insulating film 5 including the region where the CrSi thin film resistor 23 is formed.

  In this embodiment, similarly to the embodiment described with reference to FIGS. 1 and 2, it is not necessary to pattern the CrSi thin film resistor 23 after the CrSi thin film resistor 23. Further, the CrSi thin film resistor 23 is not required to be patterned. Since the contact surface with the wiring pattern 49 is not exposed to the atmosphere, good electrical connection between the CrSi thin film resistor 23 and the wiring pattern 49 can be stably obtained, and the film thickness of the CrSi thin film resistor 23 can be obtained. Regardless, the CrSi thin film resistor 23 can be miniaturized and the resistance value can be stabilized without increasing the number of steps.

  Furthermore, since the refractory metal film 47 functioning as a barrier film is interposed between the CrSi thin film resistor 23 and the polysilicon pattern 45, variation in contact resistance between the CrSi thin film resistor 23 and the wiring pattern 49 is reduced. Thus, the accuracy of the resistance value and the yield can be improved.

  Furthermore, the refractory metal film 47 contributes to lowering the resistance of the polysilicon pattern 45, and the refractory metal film 47 can be formed without increasing the number of manufacturing steps compared to the prior art. The contact resistance between the metal thin film resistor and the wiring pattern can be stabilized.

  Further, in the embodiment of the manufacturing method described above, the Ar sputter etching process is performed before the metal thin film for the CrSi thin film resistor 23 is formed. It is possible to reduce the variation in resistance value caused by the above.

In the embodiment shown in FIG. 13, a CrSiN film may be formed on the CrSi thin film resistor 23 as in the embodiment shown in FIG.
In the above-described embodiments and samples shown in FIGS. 1 to 13, an example is shown in which CrSi is used as the material of the metal thin film resistor, but the present invention is not limited to this, and the metal thin film As the material of the resistor, other materials such as NiCr, TaN, CrSi ₂ , CrSiN, CrSi, and CrSi 0 may be used.

The metal thin film resistor constituting the semiconductor device of the present invention and the metal thin film resistor formed by the manufacturing method of the present invention can be applied to a semiconductor device including an analog circuit, for example.
The embodiments of the present invention have been described above. However, the present invention is not limited to these, and the dimensions, shapes, materials, arrangements, and the like are examples, and are within the scope of the present invention described in the claims. Various changes can be made.

  The present invention can be used to manufacture a semiconductor device including a metal thin film resistor made of a metal thin film formed on an insulating film.

It is process sectional drawing for demonstrating the first half of one Example of a manufacturing method. It is process sectional drawing for demonstrating the second half of the Example of the manufacturing method, (k) shows one Example of a semiconductor device. It is a figure which shows the relationship between the sheet resistance and film thickness of the metal thin film resistor formed by this invention, a vertical axis | shaft shows sheet resistance (ohm / square) and a horizontal axis shows CrSi film thickness (Å). The relationship between the film thickness and the value (σ / AVE) obtained by dividing the standard deviation (σ) of the sheet resistance of the metal thin film resistor formed by the present invention at 63 locations in the wafer surface by the average value (AVE) The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å). Time elapsed since the formation of the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor with and without the Ar sputter etching process before forming the metal thin film for the metal thin film resistor (A) shows the case where it is performed, (B) shows the case where it is not performed, the vertical axis is the sheet resistance (Ω / □), and the horizontal axis is the elapsed time (hours) after the formation of the base film. ). It is a figure which shows the relationship between the amount of Ar sputter etching, and sheet resistance, a vertical axis | shaft shows sheet resistance (ohm / square), and a horizontal axis shows etching amount (thermal oxide film etching amount conversion) (換算). After forming a CrSi thin film for metal thin film resistors, the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance immediately after formation is shown. In the figure, the vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hour). It is a figure showing the results of investigating fluctuations in the metal thin film resistance and metal wiring contact resistance caused by heat treatment for the sample with the refractory metal film remaining at the bottom of the connection hole and the sample completely removed at the time of forming the connection hole. The axis indicates the value normalized by the contact resistance value before heat treatment, and the horizontal axis indicates the number of heat treatments. It is sectional drawing for demonstrating the other Example of a semiconductor device and a manufacturing method. It is sectional drawing for demonstrating the further another Example of a semiconductor device and a manufacturing method. It is process sectional drawing for demonstrating the further another Example of a manufacturing method, (d) shows the further another Example of a semiconductor device. Is a diagram showing the relationship between the resistivity of the N ₂ partial pressure of the gas for CrSiN film formation and CrSiN film, and the vertical axis resistivity [rho (mohms · cm), the horizontal axis represents the N ₂ partial pressure (%). It is process sectional drawing for demonstrating the further another Example of a manufacturing method, (d) shows the further another Example of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation oxide film 5 1st interlayer insulation film 7 Metal material pattern 9 Refractory metal film 11 Wiring pattern 13, 17 Plasma CVD oxide film 15 SOG film 19 2nd interlayer insulation film 21 Connection hole 23 CrSi thin film resistor 25 Silicon oxide film 27 Silicon nitride film 29 Passivation film 31 Metal film for wiring 33 High melting point metal film 35, 39 Resist pattern 36 Opening 37 CrSi thin film 41, 43 CrSiN film 44 Second interlayer insulating film 45 Polysilicon pattern 46 Second Interlayer insulation film 47 Refractory metal film 49 Wiring pattern

Claims (11)

In a method for manufacturing a semiconductor device having a metal thin film resistor on an insulating film,
Before forming a metal thin film for forming a metal thin film resistor on the insulating film, the semiconductor device manufacturing method includes a step of etching the insulating film by an Ar sputter etching technique. . (A) A step of forming a wiring pattern on the base insulating film corresponding to the formation planned regions at both ends of the metal thin film resistor,
(B) forming an insulating film on the base insulating film including the wiring pattern;
(C) a step of forming connection holes in the insulating film corresponding to the formation planned regions at both ends of the metal thin film resistor and the wiring pattern;
(D) forming a metal thin film on the insulating film including the inside of the connection hole; and (E) patterning the metal thin film so that the metal thin film remains in the connection hole to form a metal thin film resistor. Including the step of forming,
The manufacturing method according to claim 1, wherein the insulating film is etched by the Ar sputter etching technique before the metal thin film is formed in the step (D).   The manufacturing method of Claim 1 or 2 which forms the said metal thin film in the film thickness of 5-1000 mm.   The manufacturing method according to any one of claims 1 to 3, wherein the metal thin film is continuously formed without breaking a vacuum after the etching process on the insulating film by the Ar sputter etching technique.   The manufacturing method according to any one of claims 1 to 4, wherein the etching process using an Ar sputter etching technique is performed for a film thickness of 25 mm or more in terms of a thermal oxide film etching amount.   6. The manufacturing method according to claim 2, wherein, in the step (A), the wiring pattern is formed of a metal material pattern and a refractory metal film formed on at least the upper surface of the metal material pattern. .   6. The manufacturing method according to claim 2, wherein in the step (A), the wiring pattern is formed of a polysilicon pattern and a refractory metal film formed on at least the upper surface of the polysilicon pattern. .   The manufacturing method according to claim 6 or 7, wherein the refractory metal film is formed to a thickness of 500 to 3000 mm. In the step (D), after forming the metal thin film in an oxygen-free atmosphere, continuously forming a metal nitride film on the metal thin film in an oxygen-free atmosphere,
The manufacturing method according to claim 2, wherein in the step (E), the metal nitride film and the metal thin film are patterned to form a laminated pattern including the metal nitride film pattern and the metal thin film resistor.   The manufacturing method according to claim 9, wherein a nitrogen partial pressure in a sputtering gas when forming the metal nitride film is 18 to 90%. The manufacturing method according to claim 2, wherein the wiring pattern is an uppermost wiring pattern.

Images