JP4497975B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a metal thin film resistor on a base insulating film formed on a semiconductor substrate.

In an analog integrated circuit, a resistance element is frequently used as an important element. In recent years, among resistive elements, a resistor made of a metal thin film (referred to as a metal thin film resistor) has attracted attention because of its low temperature dependency (hereinafter referred to as TCR). Examples of the material for the metal thin film resistor include chromium silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi ₂ ), chromium nitride silicide (CrSiN), and chromium silicon oxy (CrSi0). Used.
In a semiconductor device provided with a metal thin film resistor, in order to satisfy the demand for higher integration, the metal thin film resistor is often formed with a thin film thickness of 1000 Å (angstrom) or less with the aim of higher sheet resistance.

  Further, in a semiconductor device, a laser trimming process is performed in which a fuse element or a resistance element is irradiated with a laser beam to cut or alter it for performance adjustment after completion of the physical device (for example, Patent Document 1). reference.).

Conventionally, there are the following methods for electrically connecting metal thin film resistors.
1) A method of directly connecting metal wiring to a metal thin film resistor (see, for example, Patent Document 2).
2) A method of forming an interlayer insulating film after forming a metal thin film resistor, forming a connection hole in the interlayer insulating film, and connecting a metal wiring through the connection hole (see, for example, Patent Document 3 and Patent Document 4) .)
3) A method of forming a barrier film on the metal thin film resistor layer and connecting metal wiring to the barrier film (see, for example, Patent Document 5 and Patent Document 6).
4) An electrode is formed in the connection hole formed in the insulating film, a resistor film is formed on the insulating film, and then the resistor film is dry-etched so as to connect to the electrode to form a resistor pattern. (For example, refer patent document 2).
Hereinafter, the metal wiring is also referred to as a wiring metal pattern.

A method for electrically connecting the metal thin film resistors 1) to 4) will be described below.
Referring to FIG. 24, 1) a method of directly forming metal wiring on a metal thin film resistor will be described.
A first interlayer insulating film 5 is formed on a wafer-like silicon substrate 1 on which an element isolation oxide film 3 and transistor elements (not shown) have been formed, and a metal is formed on the first interlayer insulating film 5. A thin film resistor 101 is formed. A wiring metal film is formed on the entire surface of the first layer interlayer insulating film 5 including the metal thin film resistor 101, and the wiring metal film is patterned by a wet etching technique to form a first layer wiring metal pattern 103. Form.
In a general manufacturing process of a semiconductor device, a dry etching technique is used for etching a metal film for wiring. However, in a situation where a thin metal thin film resistor 101 exists directly under the metal film for wiring, Since the metal thin film resistor 101 is etched by over-etching, the dry etching technique cannot be used. Therefore, it is necessary to form the first-layer wiring metal pattern 103 by patterning the wiring metal film by the wet etching technique.

Referring to FIG. 25, 2) a method of forming a metal thin film resistor, forming an interlayer insulating film, forming a connection hole in the interlayer insulating film, and connecting metal wiring through the connection hole will be described. .
After the element isolation oxide film 3, the first layer interlayer insulating film 5 and the metal thin film resistor 101 are formed on the silicon substrate 1, a metal is formed on the first layer interlayer insulating film 5 including the metal thin film resistor 101. A CVD (chemical vapor deposition) oxide film 105 is formed as an interlayer insulating film with the wiring. On the CVD oxide film 105, a resist pattern having openings corresponding to both ends of the metal thin film resistor 101 for forming a metal wiring connection hole is formed, and the resist pattern is formed by wet etching technology. As a mask, the CVD oxide film 105 is selectively removed to form a connection hole 107. After removing the resist pattern, a wiring metal film made of an AlSiCu film is formed on the CVD oxide film 105 including the inside of the connection hole 107, and the first metal wiring pattern 109 is formed by patterning the wiring metal film. To do.
In a general semiconductor device manufacturing process, a dry etching technique is used to form the connection hole 107. However, if the metal thin film resistor 101 is thinner than 1000 mm, the connection hole 107 penetrates the metal thin film resistor 101. It is difficult to prevent this, and it is necessary to form the connection hole 107 by a wet etching technique.

Referring to FIG. 26, 3) a method of forming a barrier film on the metal thin film resistor layer and connecting metal wiring to the barrier film will be described.
After the element isolation oxide film 3, the first layer interlayer insulating film 5 and the metal thin film resistor 101 are formed on the silicon substrate 1, a metal is formed on the first layer interlayer insulating film 5 including the metal thin film resistor 101. A refractory metal film such as TiW is formed as a barrier film with the wiring, a wiring metal film is further formed thereon, and the wiring metal film is patterned by a dry etching technique to form a first layer wiring metal. A pattern 111 is formed. At this time, since the refractory metal film is formed under the wiring metal film, the metal thin film resistor 101 is not etched even if the dry etching technique is used. Thereafter, the refractory metal film pattern 113 is formed by selectively removing the refractory metal film by wet etching technique using the first-layer wiring metal pattern 111 as a mask. Here, since the refractory metal film is located immediately above the metal thin film resistor 101, it is difficult to pattern the refractory metal film by a dry etching technique.

Referring to FIG. 27, 4) an electrode is formed in the connection hole formed in the insulating film, a resistor film is formed on the insulating film, and then dry-etched so as to connect to the electrode. A method of forming a resistor pattern will be described. Here, the case where the wiring metal pattern is further formed on the upper layer of the wiring metal pattern provided under the connection hole will be described.
After the first layer interlayer insulating film 5 is formed on the silicon substrate 1, a first layer wiring metal pattern 115 is formed on the first layer interlayer insulating film 5. After the insulating film 117 is formed on the first layer interlayer insulating film 5, the first connection is made to the insulating film 117 on the first layer wiring metal pattern 115 disposed corresponding to both ends of the metal thin film resistor. A hole 119 is formed, and a conductive plug (electrode) 121 is formed by embedding a conductive material in the first connection hole 119. At this time, a connection hole for electrically connecting the first-layer wiring metal pattern 115 and the second-layer wiring metal pattern formed in a later step is not formed. Next, a metal thin film for a metal thin film resistor is formed on the entire surface of the insulating film 117, and the metal thin film is patterned to form the metal thin film resistor 101 on the conductive plug 121 and the insulating film 117.

  An insulating film 123 is formed on the entire surface of the insulating film 117 to prevent the metal thin film resistor 101 from being etched when a second-layer wiring metal pattern formed in a later step is patterned by a dry etching technique. To do. Insulating films 117 and 123 on the first-layer wiring metal pattern 115 arranged to establish electrical connection with the second-layer wiring metal pattern in a region different from the region where the metal thin film resistor 101 is formed Two connection holes 125 are formed, and a conductive material is embedded in the second connection holes 125 to form second conductive plugs 127. A metal film for the second-layer wiring metal pattern is formed on the insulating film 123 including the formation region of the second conductive plug 127, and the metal film is patterned by a photoengraving technique and a dry etching technique. A second-layer wiring metal pattern 129 is formed on the second conductive plug 127 and the insulating film 123.

Further, although not a metal thin film resistor, a semiconductor integrated circuit device including a resistor formed on an uppermost wiring electrode via an insulating film and connected to the uppermost wiring electrode is disclosed ( For example, see Patent Document 7.)
With reference to FIG. 28, the case where such a structure is applied to a metal thin film resistor will be described.

  After forming the first layer interlayer insulating film 5 on the silicon substrate 1 on which the element isolation oxide film 3 is formed, and forming the first layer wiring metal pattern 115 on the first layer interlayer insulating film 5, A base insulating film 131 is formed on the entire surface of the first-layer interlayer insulating film 5 including the first-layer wiring metal pattern 115. A connection hole 133 is formed in the base insulating film 131 on the first-layer wiring metal pattern 115 by photolithography and dry etching. A metal thin film for forming a metal thin film resistor is formed on the entire surface of the base insulating film 131 including the formation region of the connection hole 133, and the metal thin film is patterned into a predetermined shape to form the metal thin film resistor 101. .

  Further, as a semiconductor device provided with a metal thin film resistor, an integrated circuit in which a metal thin film resistor is mounted on an insulating film of a semiconductor integrated circuit, wherein the metal thin film resistor is in contact with the metal wiring at the electrode portion of the metal thin film resistor. In addition, there is disclosed one configured to be formed on at least a part of an end surface and an upper surface of an end portion of a metal wiring (see, for example, Patent Document 8).

With reference to FIG. 29, a method of making contact between the metal thin film resistor and the metal wiring on at least a part of the end face and the upper surface of the end of the metal wiring will be described.
A first-layer interlayer insulating film 5 is formed on the silicon substrate 1 on which the element isolation oxide film 3 is formed, a first-layer wiring metal pattern 115 is formed on the first-layer interlayer insulating film 5, After the plasma nitride film 135 is formed on the entire surface of the first layer interlayer insulating film 5 including the first layer wiring metal pattern 115, a part of the plasma nitride film 135 is removed to form the first layer wiring metal pattern 115. The end face and a part of the upper face are exposed. Thereafter, a metal thin film for the metal thin film resistor is deposited, and the metal thin film is patterned to form the metal thin film resistor 101.

JP-A-8-124729 JP 2002-124039 A JP 2002-261237 A Japanese Patent No. 2699559 Japanese Patent No. 2932940 Japanese Patent No. 3185777 JP 58-148443 A JP-A-61-100956

In the laser trimming process, when a laser beam is irradiated onto a laser beam irradiation body such as a fuse element or a resistor, a peripheral region at a position where the laser beam is irradiated generates heat. This heat changes the contact resistance between the metal thin film resistor and the metal material for electrical connection between the metal thin film resistor. Such a change in contact resistance is such that the laser light irradiation body is electrically insulated after being insulated once in the laser trimming process in which the laser light irradiation body is electrically insulated to adjust the performance of the apparatus. There was no problem because it was not.
On the other hand, as described in Patent Document 1, for example, laser light is irradiated while scanning on the metal thin film resistor to insulate a part of the metal thin film resistor, and trimming is performed while measuring the performance of the semiconductor device. In the laser trimming process (referred to as online trimming process) to be performed, the metal thin film resistor is not completely insulated but is in a conductive state even after the trimming process. For this reason, in the on-line trimming process, the contact resistance is different at the time of measurement and after the measurement, so that the performance measurement cannot be performed correctly, and there is a problem that the highly accurate trimming process cannot be performed.

  Therefore, according to the present invention, the contact resistance between the metal thin film resistor and the metal material for electrically connecting the metal thin film resistor changes due to the heat generated by laser light irradiation to the metal thin film resistor during the laser trimming process. An object of the present invention is to provide a semiconductor device capable of reducing the above.

The semiconductor device of the present invention includes a lower-layer insulating film formed on a semiconductor substrate, a wiring metal pattern and a heat-dissipating metal pattern formed on the lower-layer insulating film, the lower-layer insulating film, and the wiring A base insulating film (also simply referred to as a base film) formed on the metal pattern for heat dissipation and the metal pattern for heat dissipation, a connection hole formed in the base insulating film on the metal pattern for wiring, and the base insulating film A metal thin film resistor formed over the connection hole and electrically connected to the wiring metal pattern in the connection hole, and a part of the heat dissipation metal pattern is a region under the metal thin film resistor. Is arranged.
In the claims and the specification of the present application, the base insulating film that is the base film of the metal thin film resistor may be a single-layer insulating film or a laminated film including a plurality of insulating films. .

  In the semiconductor device of the present invention, an opening may be formed in the insulating film on the heat radiating metal pattern including the base insulating film in a region different from the region where the metal thin film resistor is formed.

  Further, the wiring metal pattern may be the uppermost wiring metal pattern.

  Further, the upper insulating film formed on the metal thin film resistor and the base insulating film, and at least the region on the metal thin film resistor except the region where the metal thin film resistor is irradiated with laser light. You may make it further provide the 2nd metal pattern for thermal radiation which consists of a metal material arrange | positioned on the said upper layer side insulating film.

  Furthermore, a second opening may be formed in the insulating film formed on the second metal pattern for heat dissipation.

  Further, the heat dissipation metal pattern and the second heat dissipation metal pattern may be connected via a second connection hole formed in the base insulating film and the upper insulating film.

  Furthermore, the metal pattern for wiring may be constituted by a metal material pattern and a refractory metal film formed on at least the upper surface of the metal material pattern.

  Further, the second wiring metal pattern may be the uppermost wiring metal pattern.

Further, at least an upper end portion of the connection hole is formed in a tapered shape, and a reverse sputtering residue containing at least the wiring metal pattern, the insulating film material, and Ar (argon) as components is formed in the connection hole. It may be formed on the inner wall.
Such a reverse sputtering residue and the tapered shape of the upper end of the connection hole are formed by forming a connection hole in the insulating film on the metal pattern for wiring and then performing reverse sputtering using Ar gas (hereinafter referred to as Ar reverse sputtering). Can be formed.

  In the semiconductor device of the present invention, the metal thin film resistor may have a thickness of 5 to 1000 mm, preferably 20 to 500 mm.

  Further, the base insulating film may be planarized.

  Furthermore, a metal nitride film covering the upper surface of the metal thin film resistor may be provided, and no metal oxide film may be formed between the upper surface of the metal thin film resistor and the metal nitride film.

  As an example of a semiconductor device to which the semiconductor device of the present invention is applied, a semiconductor device provided with a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by laser irradiation to the resistor elements. Can be mentioned.

  As another example of the semiconductor device to which the semiconductor device of the present invention is applied, a divided resistor circuit for dividing an input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the division A semiconductor device including a voltage detection circuit having a comparison circuit for comparing the divided voltage from the resistor circuit with the reference voltage from the reference voltage generation circuit can be given. The divided resistance circuit constituting the voltage detection circuit includes a metal thin film resistor constituting the semiconductor device of the present invention and a resistance element to which the heat radiation metal pattern is applied.

  As still another example of a semiconductor device to which the semiconductor device of the present invention is applied, an output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying the divided voltage, and a reference voltage A reference voltage generation circuit for supplying, and a comparison circuit for comparing the divided voltage from the division resistor circuit and the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result A semiconductor device provided with a constant voltage generation circuit can be given. The divided resistor circuit constituting the constant voltage generating circuit includes a metal thin film resistor constituting the semiconductor device of the present invention and a resistor element to which a heat dissipating metal pattern is applied.

  In the semiconductor device of the present invention, the lower-layer side insulating film formed on the semiconductor substrate, the wiring metal pattern and the heat-dissipating metal pattern formed on the lower-layer side insulating film, the lower-layer insulating film, and the wiring metal pattern A base insulating film formed on the upper and heat dissipation metal pattern, a connection hole formed in the base insulating film on the wiring metal pattern, and a wiring formed in the connection hole from the base insulating film to the inside of the connection hole. A metal thin film resistor that is electrically connected to the metal pattern is provided, and a part of the metal pattern for heat dissipation is arranged in a region under the metal thin film resistor. A region where a metal pattern having a higher conductivity than that of the insulating film is disposed can be increased, and heat dissipation can be improved. As a result, the contact resistance between the metal thin film resistor and the metal material (metal pattern for wiring) for electrical connection between the metal thin film resistor changes due to heat generated by laser light irradiation during the laser trimming process. Can be reduced.

  In the semiconductor device of the present invention, if the opening is formed in the insulating film on the heat radiation metal pattern including the base insulating film in a region different from the region where the metal thin film resistor is formed, the opening is formed. The heat of the metal pattern for heat dissipation can be dissipated through, and the heat dissipation can be further improved.

  Further, the upper insulating film formed on the metal thin film resistor and the base insulating film, and at least the region on the metal thin film resistor except the region where the metal thin film resistor is irradiated with laser light. If the second heat dissipating metal pattern made of the metal material disposed on the upper insulating film is further provided, the region where the metal pattern is disposed in the vicinity of the metal thin film resistor is further increased. The heat dissipation can be further improved.

  Further, if the second opening is formed in the insulating film formed on the second heat radiating metal pattern, the heat of the second heat radiating metal pattern can be radiated from the second opening. The heat dissipation can be further improved.

  Furthermore, if the metal pattern for heat dissipation and the second metal pattern for heat dissipation are connected through the second connection hole formed in the base insulating film and the upper insulating film, the heat of the metal pattern for heat dissipation can be obtained. Can be radiated through the second connection hole and the second metal pattern for heat dissipation, and the heat dissipation can be further improved.

  When a part of the metal thin film resistor is formed in the connection hole formed in the insulating film on the metal pattern for wiring, as shown in FIG. 28, the inner wall side surface of the connection hole 133, particularly the bottom of the connection hole 133 is formed. On the side, the step coverage (step coverage) of the metal thin film resistor 101 is deteriorated, and there is a problem that the contact resistance between the metal thin film resistor 101 and the first-layer wiring metal pattern 115 increases and varies.

Therefore, at least the upper end portion of the connection hole is formed in a tapered shape, and the reverse sputtering residue containing at least the wiring metal pattern and the insulating film material and Ar as components in the inner wall of the connection hole. If formed, the step coverage of the metal thin film resistor in the connection hole can be improved by the presence of the reverse sputtering residue, and the contact resistance with the wiring pattern of the metal thin film resistor can be stabilized. can do. Further, the tapered shape formed at least at the upper end of the connection hole prevents the metal thin film deposited near the upper end of the connection hole from being formed in the connection hole when forming the metal thin film for the metal thin film resistor. The influence of the metal thin film on the deposition of the metal thin film can be reduced, and the step coverage of the metal thin film, and thus the step coverage of the metal thin film resistor can be improved.
Conventionally, the metal thin film resistor has a problem in that the resistance value fluctuates due to the composition of the base film, the elapsed time from the base film formation, and the like, and the metal thin film resistor is affected by the base film. As described above, the reverse sputtering residue and the tapered shape of the upper end portion of the connection hole in this embodiment can be formed by performing the Ar reverse sputtering process after forming the connection hole in the insulating film on the wiring metal pattern. However, by applying Ar reverse sputtering treatment to the base film of the metal thin film resistor before forming the metal thin film for the metal thin film resistor, the sheet resistance of the metal thin film resistor is reduced and the aging is reduced. There is also an effect that the change can be reduced.
The effect obtained by applying the Ar reverse sputtering process to the base film of the metal thin film resistor will be described in detail later.

  Furthermore, if the metal pattern for wiring is composed of a metal material pattern and a refractory metal film formed on at least the upper surface of the metal material pattern, the wiring metal pattern is interposed between the metal thin film resistor and the metal material pattern. Since the refractory metal film can be interposed, variation in contact resistance between the metal thin film resistor and the wiring metal pattern can be reduced, and the accuracy of the resistance value and the yield can be improved. Furthermore, in general, in a structure in which a metal thin film resistor and a metal material are in direct contact, the contact resistance largely fluctuates due to heat treatment at a relatively low temperature of about 300 to 400 ° C., but such a problem can be eliminated.

Further, in the aspect not including the second heat dissipation metal pattern, the wiring metal pattern is the uppermost wiring metal pattern, or in the aspect including the second heat dissipation metal pattern, the second heat dissipation metal pattern. If the wiring metal pattern in the same layer as the metal pattern is the uppermost wiring metal pattern, for example, the layout change of the metal thin film resistor can be realized by changing the layout of the metal thin film resistor and the uppermost wiring pattern. The degree of freedom of design can be improved.
In addition, a final protective film made of an insulating material is formed on the upper layer of the metal thin film resistor, and the upper layer of the metal thin film resistor has an insulating film other than the final protective film on the metal thin film resistor. It is possible to reduce the film thickness variation by reducing the film thickness of the insulating material. As a result, when the metal thin film resistor is irradiated with laser light and subjected to trimming processing, the laser provided with the metal thin film resistor with reduced variation in the interference of the laser light in the insulating material on the metal thin film resistor Variations in energy can be reduced, and trimming accuracy can be improved. Furthermore, by reducing the thickness of the insulating material on the metal thin film resistor, it is possible to improve the heat dissipation capability against the temperature rise of the metal thin film resistor caused by laser irradiation during the trimming process.

  Furthermore, if the base insulating film is flattened, it can be prevented that the resistance value of the metal thin film resistor varies due to the step of the insulating film.

  Furthermore, if a metal nitride film is provided to cover the upper surface of the metal thin film resistor, and no metal oxide film is formed between the upper surface of the metal thin film resistor and the metal nitride film, the upper surface of the metal thin film resistor is Oxidation can be eliminated, and the resistance value of the metal thin film resistor can be stabilized and the accuracy can be improved.

  In addition, in a semiconductor device including a divided resistor circuit that can obtain a voltage output by dividing by two or more resistors and adjust the voltage output by laser irradiation to the resistor element, the resistor element constituting the divided resistor circuit is Since the metal thin film resistor and the heat radiating metal pattern constituting the semiconductor device are provided, in order to establish electrical connection between the metal thin film resistor and the metal thin film resistor due to heat generated by laser light irradiation during the laser trimming process. The change in the contact resistance with the metal material can be reduced, and the measurement accuracy during the online trimming process can be improved to improve the accuracy of the output voltage of the divided resistor circuit.

  Also, a dividing resistor circuit for dividing the input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the dividing resistor circuit, and a reference from the reference voltage generating circuit In a semiconductor device having a voltage detection circuit having a comparison circuit for comparing voltages, a metal thin film resistor constituting the semiconductor device of the present invention and a heat dissipation metal pattern are applied as a resistance dividing circuit. By doing so, the divided resistor circuit to which the present invention is applied can improve the accuracy of the output voltage, and hence the accuracy of the voltage detection capability of the voltage detection circuit can be improved.

  Further, an output driver for controlling the output of the input voltage, a dividing resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the dividing resistor circuit In a semiconductor device having a constant voltage generation circuit having a comparison circuit for comparing the divided voltage with the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result, as a divided resistance circuit By providing the divided resistor circuit to which the metal thin film resistor and the heat radiation metal pattern constituting the semiconductor device of the present invention are applied, the divided resistor circuit to which the present invention is applied improves the accuracy of the output voltage. As a result, the output voltage of the constant voltage generation circuit can be stabilized.

  FIG. 1 is a cross-sectional view showing an embodiment, (A) is a plan view showing the vicinity of a formation region of a metal thin film resistor, (B) is a cross-sectional view at the position AA in (A), (C) These are sectional drawings in the BB position of (A). FIG. 2 is an enlarged cross-sectional view showing an enlarged portion surrounded by a broken line in FIG. Illustration of the base insulating film and the passivation film in FIG. In the embodiments described below, transistor elements, capacitor elements, and the like are formed on the same substrate, but these elements are not shown in the drawing.

  An element isolation oxide film 3 is formed on the silicon substrate 1. A first interlayer insulating film (lower insulating film) 5 made of a BPSG (Borophospho silicate glass) film or a PSG (phospho silicate glass) film is formed on the silicon substrate 1 including the formation region of the element isolation oxide film 3. ing. On the first-layer interlayer insulating film 5, a first-layer wiring metal pattern 11 and a heat-dissipating metal pattern 13 made of a metal material pattern 7 and a refractory metal film 9 formed on the surface of the metal material pattern 7 are formed. ing. The metal material pattern 7 is formed of, for example, an AlSiCu film. The refractory metal film 9 is formed of, for example, a TiN film and functions as an antireflection film / barrier film. The heat dissipating metal pattern 13 is continuously formed on one of the first layer wiring metal patterns 11 of the pair of first layer wiring metal patterns 11 and 11 electrically connected to the metal thin film resistor. Yes. A part of the heat radiation metal pattern 13 is formed in the formation region of the metal thin film resistor.

  For example, a plasma CVD oxide film, an SOG film, and a plasma CVD oxide film are formed on the first-layer interlayer insulating film 5 including the formation region of the first-layer wiring metal pattern 11 and the heat-dissipation metal pattern 13 in order from the lower layer side. A base insulating film 15 (shown integrally in FIG. 1) is formed. Connection holes 17 are formed in the base insulating film 15 so as to correspond to both end portions of the metal thin film resistor and the first-layer wiring metal pattern 11.

  As shown in FIG. 2, the bottom surface of the connection hole 17 is formed by removing a part of the surface side of the refractory metal film 9, and the upper end portion of the connection hole 17 is formed in a tapered shape. A reverse sputtering residue 19 is formed on the inner wall of the connection hole 17. The taper shape at the upper end of the connection hole 17 and the reverse sputtering residue 19 are not shown in FIGS. The tapered shape of the upper end portion of the connection hole 17 and the reverse sputtering residue 19 are formed by performing Ar reverse sputtering treatment on the base insulating film 15 in which the connection hole 17 is formed. Therefore, the reverse sputtering residue 19 contains the materials of the refractory metal film 9 and the base insulating film 15 and Ar as components, and here, Ti, N, Si, O, and Ar are included.

  A CrSi thin film resistor (metal thin film resistor) 21 is formed on the base insulating film 15 from the region between the connection holes 17 and 17 to the inside of the connection hole 17 and the metal pattern 11 for the first layer wiring. Both ends of the CrSi thin film resistor 21 are electrically connected to the first-layer wiring metal pattern 11 in the connection hole 17. Under the CrSi thin film resistor 21, a metal pattern 13 for heat dissipation is disposed via a base insulating film 15.

A passivation film 23 as a final protective film (illustrated integrally in FIG. 1) comprising a silicon oxide film on the lower layer side and a silicon nitride film on the upper layer side on the base insulating film 15 including the formation region of the CrSi thin film resistor 21. Is formed).
In the passivation film 23, an opening 25 is formed in the base insulating film 15 and the passivation film 23 on the heat dissipation metal pattern 13 in a region different from the region where the CrSi thin film resistor 21 is formed.

  In this embodiment, since the heat radiation metal pattern 13 is provided under the CrSi thin film resistor 21, a metal pattern having higher thermal conductivity than the base insulating film 15 and the passivation film 23 is provided in the vicinity of the CrSi thin film resistor 21. The area | region where 11 and 13 are arrange | positioned can be enlarged, and heat dissipation can be improved. Thereby, it is possible to reduce the change in the contact resistance between the metal thin film resistor and the first-layer wiring metal pattern 11 due to the heat generated by the laser beam irradiation during the laser trimming process.

  Furthermore, since the opening 25 is formed in the base insulating film 15 and the passivation film 23 on the heat dissipation metal pattern 13 in a region different from the region where the CrSi thin film resistor 21 is formed, the heat dissipation is performed via the opening 25. The heat of the metal pattern 13 can be dissipated and the heat dissipation can be further improved.

Furthermore, as shown in (B), since the reverse sputtering residue 19 is formed on the inner wall of the connection hole 17, the step coverage of the CrSi thin film resistor 21 in the connection hole 17 is improved. Thereby, stabilization of contact resistance with the metal pattern 11 for 1st layer wiring of the CrSi thin film resistor 21 is realizable.
Furthermore, since the upper end portion of the connection hole 17 is tapered, an overhang of the CrSi thin film deposited in the vicinity of the upper end portion of the connection hole 17 during the formation of the CrSi thin film for forming the CrSi thin film resistor 21 is prevented. Thus, the influence on the deposition of the CrSi thin film in the connection hole 17 can be reduced, and the step coverage of the CrSi thin film and, consequently, the step coverage of the CrSi thin film resistor 21 can be improved.

By the way, in a semiconductor device having a metal thin film resistor on a base insulating film formed on a semiconductor substrate, laser light passes through an insulating film such as a silicon oxide film when a laser trimming process is performed on the metal thin film resistor. When the semiconductor substrate, for example, a silicon substrate is irradiated, there is a problem that the insulating film and the silicon substrate irradiated with the laser beam are damaged, and the reliability of the semiconductor device is lowered. In addition, when online trimming is performed, a laser beam is applied to the silicon substrate, whereby electron-hole pairs are generated in the silicon substrate. Such electron-hole pairs become noise during performance measurement, and cannot be measured correctly, and there is a problem that high-precision trimming cannot be performed.
In order not to cause such a problem, the laser power must be set to an intensity between the minimum laser power that cuts or alters the metal thin film resistor and the maximum laser power that does not affect the semiconductor substrate. However, there is a problem that the margin for laser power is small and stable trimming cannot be performed.

  In this embodiment, since the heat dissipating metal pattern 13 made of a metal material is provided between the base insulating film 15 and the silicon substrate 1 in the region below the CrSi thin film resistor 21, the CrSi thin film resistor 21 is provided during the laser trimming process. Even if the CrSi thin film resistor 21 is irradiated with a laser beam having sufficient intensity to be cut or altered, the laser beam that has passed through the base insulating film 15 is placed on the side opposite to the silicon substrate 1 by the heat radiating metal pattern 13. Since the light is reflected, it is possible to prevent the laser light from being irradiated onto the silicon substrate 1. Thereby, it is possible to prevent the reliability of the semiconductor device from being lowered due to the irradiation of the laser beam onto the silicon substrate 1 during the trimming process. Furthermore, at the time of online trimming processing, generation of electron-hole pairs due to irradiation of laser light onto the silicon substrate 1 can be prevented, and highly accurate trimming processing can be performed.

  However, the semiconductor device of the present invention is not limited to the part where the metal pattern for heat dissipation is disposed in the region irradiated with the laser beam during the trimming process, but the region irradiated with the laser beam during the trimming process. The metal pattern for heat dissipation may not be arranged in part or all of the region. Even in this case, the effect of improving heat dissipation can be obtained.

In addition, regarding the method of establishing electrical connection between the metal thin film resistors, in the method 1) described above with reference to FIG. 24, the metal for the first layer wiring is directly formed on the metal thin film resistor 101 as described above. Although the pattern 103 is formed, the patterning of the metal film for the first-layer wiring metal pattern 103 cannot be performed by the dry etching technique, and it is difficult to form a fine pattern, and the circuit is highly integrated. There was a problem that hindered.
In addition, the metal thin film resistor 101 is generally easily oxidized, and even if the metal film for the first layer wiring metal pattern 103 is formed in a state where the surface of the metal thin film resistor 101 is oxidized, the metal thin film resistor 101 There is a problem that good electrical connection between the body 101 and the first-layer wiring metal pattern 103 cannot be obtained. In a general semiconductor device manufacturing process, a natural oxide film on the surface of a silicon substrate or the like can be removed with a hydrofluoric acid aqueous solution to obtain a good electrical connection with a metal wiring. Since the etching is not a little caused by the acid, if the oxide film removal treatment with hydrofluoric acid is performed before the metal film for the first-layer wiring metal pattern 103 is formed, the resistance value of the metal thin film resistor 101 varies. There was a fear.

In the method 2) described with reference to FIG. 25, the metal film patterning for the first-layer wiring metal pattern 109 is performed by forming the interlayer insulating film 85 on the metal thin film resistor 101. Can be performed by a dry etching technique.
However, as described above, the formation of the connection hole 107 for electrically connecting the metal thin film resistor 101 and the first-layer wiring metal pattern 109 needs to be opened by the wet etching technique. This hinders high integration. Further, a hydrofluoric acid aqueous solution is used in the wet etching process for forming the connection hole 107. To prevent the metal thin film resistor 101 from being etched by the hydrofluoric acid, a barrier is formed on the metal thin film resistor 101. Measures such as newly adding a process for forming and patterning a film are necessary, and there is a problem that the number of processes increases.

In the method 3) described with reference to FIG. 26, the etching process of the metal film for the first-layer wiring metal pattern 111 can be performed by the dry etching technique, and the formation of the connection hole is unnecessary. is there. However, as described above, since it is necessary to perform patterning of the refractory metal film for forming the refractory metal film pattern 113 that substantially determines the length of the metal thin film resistor 101 by the wet etching technique, The melting point metal film pattern 113 is etched wider than the desired etching region, the substantial length of the metal thin film resistor 101 varies, and as a result, the resistance value varies greatly and miniaturization is difficult. There was a problem of becoming.
Further, when the refractory metal film for the refractory metal film pattern 113 is formed, the surface of the metal thin film resistor 101 is oxidized, so that the electrical connection with the refractory metal film pattern 113 is good. The oxide film on the surface of the metal thin film resistor 101 needs to be removed with an aqueous hydrofluoric acid solution. If the oxide film removal process using hydrofluoric acid is performed before the refractory metal film pattern 113 is formed, the resistance value of the metal thin film resistor 101 is reduced. There was a risk of causing variation.

As described above, in the above methods 1) to 3) described with reference to FIGS. 24 to 26, the wet etching process is required in any step due to the thin film thickness of the metal thin film resistor. In other words, miniaturization is hindered and resistance values are varied.
Furthermore, since the metal thin film resistor is easily oxidized and it is difficult to form a good electrical connection with the metal wiring, the addition of a barrier film formation process dedicated to the metal thin film resistor and the removal of the surface oxide film with hydrofluoric acid aqueous solution Processing is required, which increases the number of processes and causes variations in resistance value.

  The semiconductor device of the present invention can also solve such problems. Hereinafter, this effect will be described while explaining an example of the manufacturing method of the above embodiment.

  FIG. 3 is a process cross-sectional view showing a formation region of a metal thin film resistor for explaining an example of a manufacturing method for manufacturing the embodiment described with reference to FIGS. 1 and 2. FIG. 4 is an enlarged cross-sectional view showing the vicinity of the connection hole after the Ar reverse sputtering process in the manufacturing method. In FIG. 3, illustration of the tapered shape of the side wall formed on the inner wall of the connection hole and the upper end portion of the connection hole is omitted. An example of this manufacturing method will be described with reference to FIGS.

(1) A first layer made of a BPSG film or a PSG film on a wafer-like silicon substrate 1 on which an element isolation oxide film 3 and transistor elements (not shown) have been formed using, for example, an atmospheric pressure CVD apparatus An eye interlayer insulating film 5 is formed to a thickness of about 8000 mm. Thereafter, a heat treatment such as reflow is performed to flatten the surface of the first interlayer insulating film 5.

  For example, using a DC magnetron sputtering apparatus, a wiring metal film made of an AlSiCu film is formed on the first interlayer insulating film 5 to a film thickness of about 5000 mm, and further, a known technique is antireflection. A refractory metal film as a film, here, a TiN film is continuously formed in a thickness of about 800 mm in a vacuum. Here, since the refractory metal film finally functions as a barrier film for stabilizing the contact resistance between the metal material pattern formed from the metal film for wiring in the subsequent process and the metal thin film resistor, It is preferable to continuously form the wiring metal film and the refractory metal film in a vacuum.

  The refractory metal film and the wiring metal film are patterned by a known photolithography technique and etching technique to form a first-layer wiring metal pattern 11 including the wiring metal pattern 7 and the refractory metal film 9 ( (See FIG. 3 (a)). At this time, since the refractory metal film functioning as an antireflection film is formed on the wiring metal film, the resist pattern is thickened or thinned to define the formation region of the first-layer wiring metal pattern 11. Etc. can be minimized. A part of the metal pattern 11 for the first layer wiring is formed to extend in the formation region of the metal thin film resistor to constitute the metal pattern 13 for heat dissipation.

  Further, at this stage, the metal thin film resistor is not formed, and the base film of the first layer wiring metal pattern 11 is formed by the first layer interlayer insulating film 5, and therefore, for the first layer wiring. The patterning of the metal pattern 11 can be performed with sufficient over-etching by the dry etching technique, and there is no need to apply the patterning by the wet etching technique, which has been a problem of the prior art. There is no impact.

(2) A plasma CVD oxide film having a thickness of about 6000 mm is formed on the first interlayer insulating film 5 including the formation region of the first layer wiring metal pattern 11 by plasma CVD, for example. By performing a known SOG coating process and etch back process, an SOG film is formed on the plasma CVD oxide film and planarized. Further, a plasma CVD oxide film for preventing diffusion of components from the SOG film is formed to a thickness of about 2000 mm. Thereby, a base insulating film 15 made of a plasma CVD oxide film, an SOG film, and a plasma CVD oxide film is formed in order from the lower layer side (see FIG. 3B).

(3) A resist pattern for forming a connection hole in the base insulating film 15 corresponding to the formation planned region at both ends of the metal thin film resistor and the first-layer wiring metal pattern 11 by a known photolithography technique. Form.
For example, using a parallel plate type plasma etching apparatus, resist is applied under the conditions of RF power: 700 W (watts), Ar: 500 sccm (standard cc / min), CHF ₃ : 500 sccm, CF ₄ : 500 sccm, pressure: 3.5 Torr (torr). Using the pattern as a mask, the base insulating film 15 is selectively removed to form connection holes 17 in the base insulating film 15. At the bottom of the connection hole 17, the refractory metal film 9 as an antireflection film / barrier film remains with a thickness of about 600 mm.
Thereafter, the resist pattern is removed (see FIG. 3C).

  Here, after the connection hole 17 is formed, a by-product removal step during etching attached to the side wall of the connection hole 17 or the like may be performed. In addition, for the purpose of improving the step coverage of the metal thin film resistor inside the connection hole 17, the shape of the connection hole 17 is formed by taper etching by changing etching conditions, etching processing combining wet etching technology and dry etching technology, or the like. Improvements may be made.

  In the step (3), it is possible to further suppress the etching rate of the refractory metal film 9 relative to the etching rate of the base insulating film 15 by optimizing the plasma etching conditions. The film thickness of the refractory metal film 9 remaining at the bottom can be made larger than that in this manufacturing method example. Furthermore, the remaining film thickness of the refractory metal film 9 after the connection hole 17 is formed can be secured while suppressing the film thickness at the time of forming the refractory metal film 9 to be low. As described above, since the step (3) for forming the connection hole 17 is performed at a stage where the metal thin film resistor is not formed, the connection hole 17 is not subject to any restrictions due to the thinness of the metal thin film resistor. Processing is possible, and the pursuit of miniaturization by applying dry etching technology is sufficiently possible.

(4) For example, in the Ar sputter etching chamber of a multi-chamber sputtering apparatus, in the vacuum, the connection hole 17 under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr (millitorr), treatment time: 20 seconds Ar reverse sputtering treatment is performed on the surface of the underlying insulating film 15 including the inside. This etching condition is the same as that for etching a thermal oxide film formed in a wet atmosphere at 1000 ° C. by about 50 mm. The thickness of the refractory metal film 9 remaining at the bottom of the connection hole 17 after this treatment was about 500 mm.

  Subsequently, a CrSi thin film (metal thin film) 27 for the metal thin film resistor is continuously formed without breaking the vacuum state after completion of the Ar reverse sputtering process. Here, after a semiconductor wafer is transferred from an Ar sputter etching chamber to a sputter chamber equipped with a CrSi target, a Si / Cr = 80/20 wt% (weight percent) CrSi target is used and a DC power of 0.7 kW ( (Kilowatt), Ar: 85 sccm, pressure: 8.5 mTorr, treatment time: 9 seconds, and a CrSi thin film 27 is formed on the entire surface of the base insulating film 15 including the inside of the connection hole 17 to a thickness of about 50 mm. (See FIG. 3 (d)).

  Thus, before forming the CrSi thin film 27 for the metal thin film resistor, by performing the Ar reverse sputtering process on the base insulating film 15 including the inside of the connection hole 17, as shown in FIG. A reverse sputtering residue 19 made of the material of the refractory metal film 9 and the base insulating film 15 and a material containing Ar can be formed on the inner wall of the substrate 17, and the upper end portion of the connection hole 17 can be tapered. it can. Further, the step coverage of the CrSi thin film 27 in the connection hole 17 can be improved by the presence of the reverse sputtering residue 19, and the taper shape formed at the upper end portion of the connection hole 17 allows the CrSi thin film 27 to be formed. In this case, the overhang of the CrSi thin film 27 deposited in the vicinity of the upper end of the connection hole 17 can be prevented to reduce the influence on the deposition of the CrSi thin film 27 in the connection hole 17, and the step coverage of the CrSi thin film 27 can be reduced. Can be improved.

Further, by performing the Ar reverse sputtering process, a very small amount of natural oxide film formed on the surface of the refractory metal film 9 at the bottom of the connection hole 17 can be removed, and the first-layer wiring metal pattern 11 can be removed. And a good electrical connection between the CrSi thin film 27 can be formed.
Furthermore, by performing the Ar reverse sputtering treatment, the dependency of the CrSi thin film resistor formed from the CrSi thin film 27 on the subsequent process can be improved. This effect will be described later.

(5) A resist pattern for defining the formation region of the metal thin film resistor is formed on the CrSi thin film 27 by photolithography, and the resist pattern is used as a mask using, for example, an RIE (reactive ion etching) apparatus. The CrSi thin film 27 is patterned to form the CrSi thin film resistor 21, and then the resist pattern is removed. Here, since the CrSi thin film resistor 21 is electrically connected to the first-layer wiring metal pattern 11 in the connection hole 17, electrical connection is established on the upper surface of the metal thin film resistor as in the prior art. Therefore, it is not necessary to perform the metal oxide film removal process on the surface of the CrSi thin film resistor 21 with a hydrofluoric acid aqueous solution.
For example, a silicon oxide film and a silicon nitride film as the passivation film 23 are sequentially formed on the base insulating film 15 including the formation region of the CrSi thin film resistor 21 by plasma CVD. Thereafter, an opening 25 is formed in the base insulating film 15 and the passivation film 23 on the heat dissipation metal pattern 13 in a region different from the formation region of the CrSi thin film resistor 21 by photolithography and dry etching technology (see FIG. 1). ). Thus, the manufacturing process of the semiconductor device is completed.

  As described above, according to the embodiment described with reference to FIGS. 1 and 2, after the first-layer wiring metal pattern 11 and the connection hole 17 are formed, the CrSi thin film resistor 21 is formed and the connection hole is formed. Since the electrical connection between the CrSi thin film resistor 21 and the first layer wiring metal pattern 11 can be formed in the circuit 17, it is not necessary to perform patterning by wet etching technology after patterning the CrSi thin film resistor 21.

Further, since the contact surface of the CrSi thin film resistor 21 with the first-layer wiring metal pattern 11 is not exposed to the atmosphere, the surface oxide film removal treatment and the etching prevention barrier film formation for the CrSi thin film resistor 21 are performed. Even if not, good electrical connection between the CrSi thin film resistor 21 and the first layer wiring metal pattern 11 can be stably obtained.
Thereby, the miniaturization of the CrSi thin film resistor 21 and the stabilization of the resistance value can be realized without increasing the number of processes regardless of the film thickness of the CrSi thin film resistor 21.

Thus, it is not necessary to perform patterning by wet etching technology after forming the metal thin film resistor, and the contact surface of the metal thin film resistor with the wiring pattern is not exposed to the atmosphere. Therefore, it is possible to stably obtain a good electrical connection between the metal thin film resistor and the wiring pattern without performing the surface oxide film removal treatment and the etching prevention barrier film formation. Even if the present invention is applied to a semiconductor device having a metal thin film resistor of 5 to 1000 mm, preferably 20 to 500 mm, the metal thin film resistor can be miniaturized and the resistance value can be stabilized without increasing the number of steps. Can be realized.
In particular, according to the aspect provided with the reverse sputtering residue, as described later, it is possible to reduce the base film dependency of the sheet resistance of the metal thin film resistor. Even if it is applied to a semiconductor device having a body, the resistance value of the metal thin film resistor can be stabilized.

  Further, since the refractory metal film 9 functioning as a barrier film is interposed between the CrSi thin film resistor 21 and the metal material pattern 7, the contact resistance between the CrSi thin film resistor 21 and the first-layer wiring metal pattern 11. Variation in resistance can be reduced, and the accuracy of the resistance value and the yield can be improved.

  Further, the refractory metal film 9 also functions as a barrier film and antireflection film, and the refractory metal film 9 can be formed without increasing the number of manufacturing steps compared to the prior art, so that the manufacturing cost is increased. The contact resistance between the metal thin film resistor and the wiring metal pattern can be stabilized.

With reference to FIG. 5 and FIG. 6, the result of having investigated the characteristic of the metal thin film resistor formed by the same structure as the said Example is shown.
FIG. 5 shows the relationship between the sheet resistance and the film thickness of the metal thin film resistor, the vertical axis shows the sheet resistance (Ω / □), and the horizontal axis shows the CrSi film thickness (Å).
FIG. 6 shows the relationship between the standard deviation (σ) of the measurement results at 63 points in the wafer surface of the sheet resistance of the metal thin film resistor (σ) divided by the average value (AVE) (σ / AVE) and the CrSi film thickness. The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å).

The conditions for forming the metal thin film resistor are as follows.
Using a multi-chamber sputtering apparatus, the volume time is adjusted for two types of DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, target: Si / Cr = 50/50 wt% and 80/20 wt%. Thus, a sample was prepared with a CrSi thin film having a thickness of 25 to 500 mm. In addition, about the sample of Si / Cr = 50/50 wt%, the film thickness of 500 mm is not produced.

In addition, the Ar reverse sputtering treatment before forming the CrSi thin film was performed using the multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
In this sample, an AlSiCu film having a thickness of 5000 mm is used as the lower layer metal wiring connected to the metal thin film resistor, and a TiN film on the AlSiCu film is formed at the bottom of the connection hole between the AlSiCu film and the CrSi thin film. Adopted a structure that is not.

Sheet resistance was measured by applying a voltage of 1V across one metal thin film resistor of 20 strips with a width of 0.5 μm (micrometer) and a length of 50 μm arranged at intervals of 0.5 μm. The two-terminal method for measuring the current value was performed.
The plane dimension of the connection hole connecting the metal wiring and the CrSi thin film resistor was 0.6 μm × 0.6 μm.

  As shown in FIG. 5, regardless of the composition of the target (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%), the film thickness is increased from a thickness of 200 mm or more to a very thin film thickness of 25 mm. It can be seen that the linearity of the sheet resistance is maintained, and a metal thin film resistor having a fine dimension that cannot be formed by the conventional technique can be formed in a thin film thickness.

  Moreover, even if it sees FIG. 6 which shows the variation of the sheet resistance in 63 places in a wafer surface, the variation in resistance value of both targets (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%) It can be seen that the film is hardly affected by the film thickness, and the variation in resistance value is very small and stable. From this, if Ar reverse sputtering treatment is employed as a method for forming the sidewall in the connection hole, an extremely fine metal thin film resistor pattern can be stably formed regardless of the film thickness of the metal thin film resistor.

  FIG. 7 shows the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor when the Ar reverse sputtering treatment is performed and not performed before forming the metal thin film for the metal thin film resistor. It is a figure which shows the relationship with the time which passed since (A) when it does, (B) shows the case where it does not perform. In FIG. 7, the vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the elapsed time (time) after forming the base film.

  As a sample of FIG. 7, two silicon wafers of a plasma SiN film and a plasma NSG (non-doped silicate glass) film formed to a film thickness of 2000 mm by a plasma CVD method as a base film were prepared and formed on these silicon wafers. Using a CrSi thin film resistor, the sheet resistance of the CrSi thin film resistor was measured by the four-terminal method.

The plasma SiN film as a base film is formed using a parallel plate type plasma CVD apparatus under conditions of temperature: 360 ° C., pressure: 5.5 Torr, RF power: 200 W, SiH ₄ : 70 sccm, N ₂ : 3500 sccm, NH ₃ : 40 sccm. Formed with.
The plasma NSG film was formed using a parallel plate plasma CVD apparatus under the conditions of temperature: 400 ° C., pressure: 3.0 Torr, RF power: 250 W, SiH ₄ : 16 sccm, N ₂ O: 1000 sccm.

  The CrSi thin film resistor is formed using a multi-chamber sputtering apparatus under the conditions of Si / Cr = 80/20 wt% target, DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 13 seconds. By performing the treatment, a film thickness of 100 mm was formed.

  A sample subjected to Ar reverse sputtering treatment was subjected to the above-described multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 80 seconds. This is a process corresponding to etching and removing a thermal oxide film formed at 1000 ° C. in a wet atmosphere by 200 mm.

As shown in (B), when the Ar reverse sputtering treatment is not performed before the formation of the CrSi thin film, it can be seen that the sheet resistance is greatly different depending on the difference in the base film (on the SiN film and on the NSG film). Furthermore, it can be seen that the time elapsed from the formation of the base film to the formation of the CrSi thin film resistor is greatly affected.
On the other hand, as shown in (A), when Ar reverse sputtering treatment is performed, it can be seen that both the type of the underlying film and the elapsed time have little influence on the sheet resistance of the CrSi thin film resistor.

  From this, after performing Ar reverse sputtering treatment, by forming a metal thin film for a metal thin film resistor continuously in a vacuum, depending on the elapsed time from the previous process, the difference in the underlying film for each product, etc. It can be seen that the variation in the generated resistance value can be greatly improved.

  FIG. 8 is a diagram showing the relationship between the amount of Ar reverse sputtering treatment and the sheet resistance. The vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the etching amount (in terms of thermal oxide film etching amount) (Å). For the sample of FIG. 8, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 7 were used as the base film and the CrSi thin film resistor. In addition, after performing Ar reverse sputtering process with respect to the plasma NSG film which passed for one week after film-forming, the CrSi thin film resistor was formed on the plasma NSG film. Ar reverse sputtering treatment was performed under the same conditions as the sample in FIG. 7 except for the etching amount. And it adjusted so that it might be set to 0 (no Ar reverse sputtering process), 25 (s), 50 (s), 100 (s), 200 (s), 400 (s), and 1000 (s) in conversion of the etching amount of the thermal oxide film formed in wet atmosphere. The sheet resistance of the CrSi thin film resistor was measured by the 4-terminal method.

  From the results of FIG. 8, it can be seen that if the Ar reverse sputtering process is performed for a film thickness of 25 mm or more in terms of the etching amount of the thermal oxide film formed in the wet atmosphere, the effect of stabilizing the resistance value of the CrSi thin film resistor can be obtained. I understood. In FIG. 8, the sample is manufactured only up to the etching thickness of 1000 mm in terms of the thermal oxide film etching amount under the Ar reverse sputtering treatment condition, but the film thickness is larger than 1000 mm in terms of the thermal oxide film etching amount. Even if the etching is performed by the amount, if the base film remains in the formation region of the metal thin film resistor, the effect of the Ar reverse sputtering process can be expected.

Furthermore, it has been found that the effect of Ar reverse sputtering treatment affects not only the influence of the underlayer but also the stability of the resistance value itself of the CrSi thin film.
FIG. 9 shows the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% after the formation of the CrSi thin film and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance (R0) immediately after formation. The vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hours).

For the sample of FIG. 9, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 7 were used as the base film and the CrSi thin film resistor.
As for Ar reverse sputtering treatment, no treatment is performed (without Ar etching), thermal oxide film conversion is 100 liters with a treatment time of 40 seconds (Ar etch: 100 liters), thermal oxide film conversion is 200 liters with a processing time of 80 seconds. Three types (Ar etch: 200 mm) were prepared.

In the sample not subjected to Ar reverse sputtering treatment (without Ar etching), the resistance value increased with time after formation, and the resistance value fluctuated by 3% or more when left for 300 hours or longer. I understand.
In contrast, in the samples subjected to Ar reverse sputtering treatment (Ar etch: 100 Å and Ar etch: 200 Å), the rate of change in resistance value is greatly reduced, and the sheet resistance immediately after formation even after being left for 300 hours or more. There was no deviation from ± 1%.
Further, when comparing Ar etch: 100 Å with Ar etch: 200 影響, it was found that the influence of the Ar reverse sputtering treatment amount is small, and the effect is small with a small etching amount.

As described above, with reference to FIGS. 5 to 9, the effect of the Ar reverse sputtering treatment on the influence of the base film on the sheet resistance and the influence of the air standing time has been described. It is not limited to a CrSi thin film resistor of Si / Cr = 50/50 wt% or 80/20 wt%. In addition, the same effect as the above is observed in all of the CrSi thin film and the CrSiN film formed with the target of Si / Cr = 50/50 to 90/10 wt%.
Also, the Ar reverse sputtering method is not limited to the DC bias sputter etching method used this time.

  FIG. 10 is a diagram showing the results of examining the fluctuations in the metal thin film resistance and the metal wiring contact resistance caused by the heat treatment for the sample in which the refractory metal film is left at the bottom of the connection hole when the connection hole is formed and the sample that is completely removed. It is. The vertical axis represents the value normalized by the contact resistance value before heat treatment, and the horizontal axis represents the number of heat treatments.

As the sample of FIG. 10, by adjusting the dry etching time at the time of forming the connection hole, a sample in which about 500 mm of the refractory metal film at the bottom of the connection hole was left and a sample from which the complete removal was made were prepared.
A TiN film was used as the refractory metal film.
The CrSi thin film resistor was formed to a thickness of 50 mm under the conditions of Si / Cr = 80/20 wt%, DC power: 0.7 KW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 6 seconds.
The Ar reverse sputtering treatment before forming the CrSi thin film was performed under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
The plane dimension of the connection hole was 0.6 μm × 0.6 μm. A four-terminal method was used as the contact resistance measurement method.

About said sample, it was investigated how contact resistance changed by adding heat processing for 30 minutes in 350 degreeC and nitrogen atmosphere.
A sample (with TiN) having a TiN film at the bottom of the connection hole hardly changes from the contact resistance before the heat treatment even if the heat treatment is added twice. On the other hand, in the sample from which the TiN film was completely removed (without TiN), the contact resistance fluctuated by 20% or more compared to before the heat treatment due to the addition of two heat treatments. This means that the TiN film has a function as a barrier film that prevents resistance fluctuation due to the interaction between the CrSi thin film and the metal wiring.

  The presence of the TiN film between the CrSi thin film resistor and the metal wiring makes it possible to extremely reduce fluctuations in contact resistance due to heat treatment performed in the manufacturing process such as sintering and CVD, and to perform assembly work as a subsequent process. Fluctuations in contact resistance due to heat treatment such as soldering. As a result, the contact resistance as set can be stably obtained, the fluctuation of the contact resistance before and after assembly can be prevented, and the product can be highly accurate and the yield can be improved.

In the manufacturing method described with reference to FIGS. 1 to 4, in the step (1), the metal film for the first-layer wiring metal pattern 11 and the refractory metal film are continuously formed in a vacuum. However, the manufacturing method is not limited to this.
For example, when a metal film for the first layer wiring metal pattern 11 is formed, once exposed to the atmosphere, and then a refractory metal film is formed, a natural oxide film formed on the surface of the wiring metal film is formed. Due to the influence, it becomes difficult to ensure electrical conduction between the metal film and the refractory metal film. In such a case, the connection hole 17 is formed in the base insulating film 15 on the first-layer wiring metal pattern 11 composed of the metal material pattern 7 and the refractory metal film 9 formed by patterning the metal film and the refractory metal film. In the step of forming, the refractory metal film 9 at the bottom of the connection hole 17 is completely removed, whereby the electrical connection between the first layer wiring metal pattern 11 and the CrSi thin film resistor 21 can be obtained.

In the step (1), the refractory metal film functioning as an antireflection film / barrier film is formed to a thickness of 800 mm, but the manufacturing method is not limited to this.
In general, the refractory metal film as the antireflection film is formed to a thickness of 500 mm or less. However, when the refractory metal film 9 as the barrier film is desired to remain at the bottom of the connection hole 17, the connection hole 17 is formed. In the case of over-etching (see step (3) above) and Ar reverse sputtering treatment (see step (4) above) during the formation of the metal thin film, a slight film beveling of the refractory metal film 9 occurs. In order to stably obtain the function as, it is preferable to form a film with a thickness of 500 mm or more.

  However, as described above, by optimizing the etching conditions for forming the connection holes 17 and the Ar reverse sputtering treatment conditions, the film verifica- tion of the refractory metal film 9 is minimized even if the film thickness of the refractory metal film 9 is 500 mm or less. It is possible to exhibit the function as a barrier film while limiting to the limit.

  In the step (4), Ar reverse sputtering is performed immediately before the formation of the CrSi thin film 27. If the refractory metal film 9 as a barrier film remains at the bottom of the connection hole 17, TiN Since the refractory metal film 9 made of a film does not form a natural oxide film that is as strong as the AlSiCu film even when exposed to the atmosphere, the CrSi thin film 27 and the first-layer wiring metal pattern can be formed without performing the Ar reverse sputtering process. Eleven electrical connections can be obtained. In this case, the tapered shape of the upper end portion of the connection hole 17 and the reverse sputtering residue 19 are not formed. However, as described above, the stability of the resistance value of the CrSi thin film resistor 21 can be improved by performing the Ar reverse sputtering process immediately before the formation of the CrSi thin film 27. Therefore, the Ar reverse sputtering process can be performed. preferable.

  In the above embodiment, the base insulating film 15 is flattened by using an SOG film formation and etch-back technique, but the insulating film serving as the base of the metal thin film resistor is not limited to this. It is not something. As an insulating film as a base of the metal thin film resistor, for example, an insulating film that has been flattened using a known chemical mechanical polish (CMP) technique, a plasma CVD oxide film that has not been flattened, or SOG Other insulating films such as an SOG film that has been flattened by applying a heat treatment after coating, and a CVD insulating film formed by HDP (high-density-plasma) -CVD method that has been planarized by etching back Good. However, since many analog resistance elements are used not only in the TCR but also in a configuration in which pairability and specific accuracy are important, in particular, the metal thin film resistor constituting the semiconductor device of the present invention. When the body is applied to an analog resistance element, it is preferable that the insulating film serving as the base of the metal thin film resistor is subjected to a planarization process.

  In the above embodiment, the passivation film 23 is formed on the CrSi thin film resistor 21. However, the present invention is not limited to this, and the insulation formed on the CrSi thin film resistor 21. The film may be any insulating film such as an interlayer insulating film for forming a second-layer wiring metal pattern.

  FIG. 11 is a cross-sectional view showing another embodiment, (A) is a plan view showing the vicinity of the formation region of the metal thin film resistor, (B) is a cross-sectional view at the position AA of (A), ) Is a cross-sectional view taken along the line BB in FIG. FIG. 12 is an enlarged cross-sectional view showing an enlarged portion surrounded by a broken line in FIG. Illustration of the base insulating film and the passivation film in FIG. 11 and 12, the same reference numerals are given to the portions that perform the same functions as those in FIGS. 1 and 2, and detailed descriptions thereof are omitted.

  An element isolation oxide film 3, a first layer interlayer insulating film 5, a metal material pattern 7 and a refractory metal film 9, a first layer wiring metal pattern 11 and a heat dissipation metal pattern 13 on a silicon substrate 1, and a base An insulating film 15 is formed. Connection holes 17 are formed in the base insulating film 15 so as to correspond to both end portions of the metal thin film resistor and the first-layer wiring metal pattern 11. A reverse sputtering residue 19 is formed on the inner wall of the connection hole 17. The upper end portion of the connection hole 17 is formed in a tapered shape (see FIG. 12).

A CrSi thin film resistor 21 is formed on the base insulating film 15 from the region between the connection holes 17 and 17 to the inside of the connection hole 17 and the metal pattern 11 for the first layer wiring. Under the CrSi thin film resistor 21, a metal pattern 13 for heat dissipation is disposed via a base insulating film 15. A CrSiN film (metal nitride film) 29 is formed on the upper surface of the CrSi thin film resistor 21. CrSiO is not formed between the CrSi thin film resistor 21 and the CrSiN film 29.
A passivation film 23 is formed on the base insulating film 15 including the formation region of the CrSi thin film resistor 21 and the CrSiN film 29. An opening 25 is formed in the passivation film 23.

  Also in this embodiment, as in the embodiment described with reference to FIG. 1 and FIG. 2, the effect of improving the heat dissipation by providing the heat radiation metal pattern 13 and the opening 25 under the CrSi thin film resistor 21. In addition, the effect of preventing the laser beam irradiation to the silicon substrate 1 by providing the metal pattern 13 for heat dissipation can be obtained.

A manufacturing method for manufacturing this embodiment will be described.
On the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 3 has been completed by the same steps as the steps (1) to (3) described with reference to FIGS. A first-layer wiring metal pattern 11 and a heat-dissipating metal pattern 13 composed of a layer interlayer insulating film 5, a wiring metal pattern 7 and a refractory metal film 9, a base insulating film 15, and a connection hole 17 are formed.

  Under the same conditions as the Ar reverse sputtering process and the CrSi thin film deposition process in the step (4) described with reference to FIG. 3D, for example, in an Ar sputter etching chamber of a multi-chamber sputtering apparatus, in a vacuum, An Ar reverse sputtering process is performed on the surface of the interlayer insulating film 5 to form a reverse sputtering residue 19 and a tapered shape of the upper end portion of the connection hole 17. Subsequently, after completion of the Ar reverse sputtering process, the vacuum is not broken. Then, a CrSi thin film for a metal thin film resistor is formed.

Further, after forming the CrSi thin film, a CrSiN film is formed on the CrSi thin film continuously without breaking the vacuum. For example, the Si / Cr = 80/20 wt% CrSi target used in the formation of the CrSi thin film was used, DC power: 0.7 kW (kilowatt), Ar + N ₂ (mixed gas of argon and nitrogen): 85 sccm, pressure: 8 Processing is performed under conditions of 0.5 mTorr, processing time: 6 seconds, and a CrSiN film is formed on the CrSi thin film to a thickness of about 50 mm. Next, the CrSiN film and the CrSi thin film are patterned to form a laminated pattern composed of the CrSiN film 29 and the CrSi thin film resistor 21.
Thereafter, a passivation film 23 is formed on the base insulating film 15, and an opening 25 is formed in the passivation film 23.

As described above, in the embodiment described with reference to FIGS. 11 and 12, as in the embodiment described with reference to FIGS. Since the metal pattern 11 is electrically connected, the metal oxide film can be formed on the surface of the CrSi thin film resistor 21 with a hydrofluoric acid aqueous solution without performing the metal oxide film removal process as in the prior art.
Further, since the upper surface of the CrSi thin film resistor 21 is covered with the CrSiN film 29, the upper surface of the CrSi thin film resistor 21 is not oxidized even when exposed to an atmosphere containing oxygen, such as air.

In general, a metal thin film has high reactivity with oxygen, and it is known that the resistance value fluctuates when the metal thin film is left for a long time in a state exposed to the atmosphere.
In the embodiment described with reference to FIGS. 11 and 12, by forming the CrSiN film 29 on the upper surface of the CrSi thin film resistor 21, the upper surface of the CrSi thin film resistor 21 is exposed to the atmosphere and the CrSi thin film resistor 21 is exposed. This prevents the resistance value from fluctuating. Here, when the CrSi thin film for forming the CrSi thin film resistor 21 is formed, the electrical connection between the CrSi thin film and the wiring pattern 11 is completed, so that a new thin film is formed on the CrSi thin film 21. Even if the film is formed, there is no influence on the characteristics.

FIG. 13 is a diagram showing the relationship between the N ₂ partial pressure of the gas for forming the CrSiN film and the resistivity of the CrSiN film, where the vertical axis represents resistivity ρ (mohm · cm (mohm · cm)), and the horizontal axis represents N ₂ partial pressure (%) is indicated. Here, the N ₂ partial pressure of Ar + N ₂ gas is adjusted under the conditions of target: Si / Cr = 50/50 wt%, DC power: 0.7 kW, Ar + N ₂ : 85 sccm, pressure: 8.5 mTorr, treatment time: 6 seconds. Thus, a CrSiN film was formed.

The CrSiN film formed by reactive sputtering with an N ₂ partial pressure of 18% or more is 10 times higher than when a gas not containing N ₂ is used at all (N ₂ partial pressure is 0%). Resistivity is shown. Therefore, if the CrSiN film is formed by setting the N ₂ partial pressure to 18% or more, even if the CrSiN film is directly formed on the CrSi thin film resistor, the resistance value of the entire CrSi thin film resistor is CrSi. The thin film is determined, and the CrSiN film has little influence on the resistance value. Here, the upper limit of the N ₂ partial pressure is about 90%. If the N ₂ partial pressure is set to be larger than 90%, it is not preferable because the sputtering rate is significantly reduced and the production efficiency is lowered.
Note that the CrSiN film itself can be used as a metal thin film resistor if the CrSiN film is formed by reactive sputtering with an N ₂ partial pressure of about 6 to 11%, for example.

In the above embodiment, the CrSiN film 29 is provided on the CrSi thin film resistor 21, but a CVD insulating film such as a silicon nitride film may be provided on the CrSi thin film resistor 21. Good. However, a CVD chamber is not connected to a general multi-chamber sputtering apparatus, and in order to continuously form a CVD-based insulating film on the CrSi thin film resistor 21 in a vacuum, a corresponding new facility is required. It is necessary to purchase, and the production cost is greatly affected.
If the CrSiN film 29 is formed on the CrSi thin film 27 for the CrSi thin film resistor 21 as in the above manufacturing method example, the CrSi thin film can be obtained using an existing multi-chamber sputtering apparatus without purchasing a new apparatus. The CrSiN film 29 serving as the oxidation resistant cover film of the resistor 21 can be formed without breaking the vacuum state.

  14A and 14B are cross-sectional views showing still another embodiment, in which FIG. 14A is a plan view showing the vicinity of a metal thin film resistor forming region, FIG. 14B is a cross-sectional view taken along the line AA in FIG. (C) is sectional drawing in the BB position of (A). Illustration of the base insulating film and the passivation film in FIG. 14A is omitted. The structure of the portion in the vicinity of the connection hole surrounded by the broken-line circle in (B) is the same as that in FIG. 14, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

  This embodiment is different from the embodiment described with reference to FIGS. 1 and 2 in that the metal pattern 13 for heat dissipation composed of the metal material pattern 7 and the refractory metal film 9 is different from the metal pattern 11 for the first layer wiring. Is provided separately. Other structures are the same as those of the embodiment described with reference to FIGS. Such a structure is similarly obtained by changing the mask for patterning the first layer wiring metal pattern 11 and the heat radiation metal pattern 13 in the manufacturing method described with reference to FIGS. Can be formed.

  In the embodiment shown in FIG. 14 as well, since the heat dissipating metal pattern 13 made of a metal material is provided between the base insulating film 15 and the silicon substrate 1 in the region below the CrSi thin film resistor 21, FIGS. As in the embodiment described with reference to FIG. 5, the effect of improving the heat dissipation due to the provision of the heat dissipation metal pattern 13 and the opening 25 under the CrSi thin film resistor 21, and the heat dissipation metal pattern 13 are provided. Thus, the effect of preventing the laser beam from being irradiated onto the silicon substrate 1 can be obtained. In addition, the effect obtained by forming the electrical connection with the wiring metal pattern 11 on the lower surface of the CrSi thin film resistor 21 and the effect obtained by performing the Ar reverse sputtering process before the formation of the CrSi thin film are obtained. be able to.

  Further, as shown in FIG. 15, in addition to the configuration of the embodiment shown in FIG. 14, the CrSiN film 29 is formed on the upper surface of the CrSi thin film resistor 21 in the same manner as the embodiment described with reference to FIGS. May be provided. The structure of the portion in the vicinity of the connection hole surrounded by the broken-line circle in FIG. 15B is the same as that in FIG. Thereby, the same effect as the Example demonstrated with reference to FIG.11 and FIG.12 can be acquired.

  In the embodiment shown in FIG. 1, FIG. 11, FIG. 14 and FIG. 15, the opening 25 is provided on the metal pattern 13 for heat dissipation, but the present invention is not limited to this. As shown, openings may not be formed in the base insulating film 15 and the passivation film 23 on the metal pattern 13 for heat dissipation. Even with this structure, it is possible to obtain the effect of improving heat dissipation by disposing the heat dissipation metal pattern 13 in the vicinity of the CrSi thin film resistor 21.

  FIG. 17 is a cross-sectional view showing still another embodiment, (A) is a plan view showing the vicinity of the formation region of the metal thin film resistor, (B) is a cross-sectional view at the position AA in (A), (C) is sectional drawing in the BB position of (A). Illustration of the base insulating film, the upper insulating film, and the passivation film in FIG. 17A is omitted. The structure of the portion in the vicinity of the connection hole surrounded by the broken-line circle in (B) is the same as that in FIG. In FIG. 17, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

  An element isolation oxide film 3, a first layer interlayer insulating film 5, a metal material pattern 7 and a refractory metal film 9, a first layer wiring metal pattern 11 and a heat dissipation metal pattern 13 on a silicon substrate 1, and a base An insulating film 15 is formed. Connection holes 17 are formed in the base insulating film 15 so as to correspond to both end portions of the metal thin film resistor and the first-layer wiring metal pattern 11. A reverse sputtering residue 19 is formed on the inner wall of the connection hole 17. The upper end portion of the connection hole 17 is formed in a tapered shape (see FIG. 2).

  A CrSi thin film resistor 21 is formed on the base insulating film 15 from the region between the connection holes 17 and 17 to the inside of the connection hole 17 and the metal pattern 11 for the first layer wiring. Under the CrSi thin film resistor 21, a metal pattern 13 for heat dissipation is disposed via a base insulating film 15.

An upper insulating film 31 made of a plasma CVD oxide film having a thickness of, for example, about 4000 mm is formed on the base insulating film 15 including the region where the CrSi thin film resistor 21 is formed.
A second connection hole 33 is formed in the base insulating film 15 and the upper insulating film 31 on the heat dissipation metal pattern 13 in a region different from the formation region of the CrSi thin film resistor 21.

  A second heat radiating metal pattern 39 made of the metal material pattern 35 and the refractory metal film 37 formed on the surface of the metal material pattern 35 is formed on the upper insulating film 31 including the formation region of the second connection hole 33. ing. The metal material pattern 35 is formed of, for example, an AlSiCu film. The refractory metal film 37 is made of, for example, a TiN film. The second heat radiating metal pattern 39 is a second region from the region on the CrSi thin film resistor 21 in the region in the vicinity of the connection holes 17 and 17 except at least the region where the CrSi thin film resistor 21 is irradiated with laser light. It is formed over the region where the connection hole 33 is formed. Further, the second heat radiating metal pattern 39 is connected to the heat radiating metal pattern 13 through the second connection hole 33. Further, in a region on the upper insulating film 31 (not shown), a second-layer wiring metal pattern composed of the metal material pattern 35 and the refractory metal film 37 is formed.

  A passivation film 23 is formed on the upper insulating film 31 including the formation region of the second heat radiating metal pattern 39. A second opening 41 is formed in the passivation film 23 on the second heat radiating metal pattern 39.

  In this embodiment, since the heat radiation metal pattern 13 is provided under the CrSi thin film resistor 21 and the second heat radiation metal pattern 39 is provided in a part of the region on the CrSi thin film resistor 21, the CrSi thin film resistor 21 is provided. The region where the metal patterns 11, 13, and 39 having higher thermal conductivity than the base insulating film 15 and the passivation film 23 are disposed in the vicinity can be increased, and the heat dissipation can be improved. Thereby, it is possible to reduce the change in the contact resistance between the metal thin film resistor and the first-layer wiring metal pattern 11 due to the heat generated by the laser beam irradiation during the laser trimming process. In particular, since a part of the second heat radiating metal pattern 39 is disposed on the connection hole 17, the heat dissipation near the connection hole 17 can be improved.

  Furthermore, since the opening 41 is formed in the passivation film 23 on the second heat radiating metal pattern 39, the heat of the second heat radiating metal pattern 39 can be radiated through the opening 41. Further improvement can be achieved.

  Further, since the metal pattern for heat dissipation 13 and the second metal pattern for heat dissipation 39 are connected via the second connection hole 33, the heat of the metal pattern for heat dissipation 13 is transferred to the second connection hole 33 and the second metal pattern for heat dissipation. The heat can be radiated from the opening 41 via 39, and the heat dissipation can be further improved.

  Further, since the heat dissipation metal pattern 13 made of a metal material is provided between the base insulating film 15 and the silicon substrate 1 in the region below the CrSi thin film resistor 21, the silicon substrate is provided with the heat dissipation metal pattern 13. The effect of preventing the laser beam 1 from being irradiated can also be obtained.

A manufacturing method for manufacturing this embodiment will be described.
On the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 3 is completed by the same steps as the steps (1) to (4) described with reference to FIGS. First-layer wiring metal pattern 11 and heat-dissipating metal pattern 13 composed of layer-layer interlayer insulating film 5, wiring metal pattern 7 and refractory metal film 9, base insulating film 15, connection hole 17 and CrSi thin film resistor 21 A CrSi thin film is formed.

After the CrSi thin film resistor 21 is formed by patterning the CrSi thin film, the plasma CVD oxide film is formed on the base insulating film 15 so as to have a film thickness of about 4000 mm including the region where the CrSi thin film resistor 21 is formed, for example, by plasma CVD. Then, the upper insulating film 31 is formed.
A second connection hole 33 is formed in the base insulating film 15 and the upper insulating film 31 on the heat dissipation metal pattern 13 in a region different from the formation region of the CrSi thin film resistor 21 by photolithography and dry etching technology.

The formation region of the second connection hole 33 is the same as that in which the first layer wiring metal pattern 11 and the heat dissipation metal pattern 13 are formed in the step (1) described with reference to FIG. A second heat radiating metal pattern 39 is formed on the upper insulating film 31.
Thereafter, the passivation film 23 is formed on the upper insulating film 31 including the formation region of the second heat radiating metal pattern 39, and the second opening 41 is formed in the passivation film 23 on the second heat radiating metal pattern 39. .

  As described above, in the embodiment described with reference to FIGS. 17 and 2, similarly to the embodiment described with reference to FIGS. 1 and 2, the wiring metal pattern 11 is formed on the lower surface of the CrSi thin film resistor 21. The effect obtained by forming the electrical connection and the effect obtained by performing the Ar reverse sputtering treatment before the formation of the CrSi thin film can be obtained.

  In the embodiment described with reference to FIGS. 17 and 2, the heat radiating metal pattern 13 and the second heat radiating metal pattern 39 are connected via the metal material pattern 35 filled in the second connection hole 33. However, the present invention is not limited to this, and the heat radiating metal pattern 13 and the second heat radiating metal pattern 39 are connected via a conductive plug formed by filling the second connection hole 33 with a conductive material. It may be connected. Further, the metal pattern for heat dissipation 13 and the second metal pattern for heat dissipation 39 are not necessarily connected, and the second connection hole 33 is formed between the metal pattern for heat dissipation 13 and the metal pattern for heat dissipation 39. It may not be possible.

  Further, the arrangement of the second heat radiation metal pattern 39 on the CrSi thin film resistor 21 is not limited to that shown in FIG. 17A, and at least the CrSi thin film resistor 21 is irradiated with laser light. What is necessary is just to arrange | position on the CrSi thin film resistor 21 except an area | region.

  Further, as shown in FIG. 18, the second heat radiating metal pattern 39 is arranged so as to be superimposed on the heat radiating metal pattern 13 in a region different from the formation region of the CrSi thin film resistor 21 and the opening 25. 13 and the second heat radiation metal pattern 39 are connected via the second connection hole 33, and an opening 25 is formed in the base insulating film 15, the upper insulating film 31, and the passivation film 23 on the heat radiation metal pattern 13. In addition, the second opening 41 may be formed in the passivation film 23 on the second heat radiating metal pattern 39. In FIG. 18, the structure of the portion in the vicinity of the connection hole surrounded by the broken-line circle in (B) is the same as that in FIG.

Further, as shown in FIG. 19, in addition to the configuration of the embodiment shown in FIG. 17, the CrSiN film 29 is formed on the upper surface of the CrSi thin film resistor 21 in the same manner as the embodiment described with reference to FIGS. May be provided. The structure of the portion near the connection hole surrounded by the broken-line circle in FIG. 19B is the same as that in FIG.
Further, the configuration in which the CrSiN film 29 is provided on the upper surface of the CrSi thin film resistor 21 can be applied to the embodiment shown in FIG.

  Moreover, in each Example shown in FIG.17, FIG.18 and FIG.19, you may make it the 2nd opening part 41 not being formed, and making it the 2nd connection hole 33 not be formed. However, both of them may not be formed.

  In the above embodiment, an example is given in which a TiN film is used as the refractory metal films 9 and 35 formed on the upper surface of the wiring metal pattern. However, the refractory metal film constituting the wiring metal pattern is However, the present invention is not limited to this, and other refractory metal films such as TiW and WSi may be used.

Moreover, although the example and sample which were shown in FIGS. 1-19 shown the example which used CrSi as a material of a metal thin film resistor, this invention is not limited to this, A metal thin film As the material of the resistor, other materials such as NiCr, TaN, CrSi ₂ , CrSiN, CrSi, and CrSi 0 may be used.

  In the above embodiment, the present invention is applied to a semiconductor device provided with a single-layer or two-layer wiring metal pattern. However, the present invention is not limited to this, and wiring of three or more layers is used. The present invention can also be applied to a semiconductor device having a multilayer metal wiring structure provided with a metal pattern. In that case, the metal wiring for the lower layer of the metal thin film resistor for obtaining the electrical connection of the metal thin film resistor may be any number of wiring metal patterns.

In the above embodiment, the wiring metal pattern 11 is the uppermost wiring metal pattern in the aspect in which the second heat dissipation metal pattern 39 is not provided, or the aspect in which the second heat dissipation metal pattern 39 is provided. Then, the wiring metal pattern in the same layer as the second heat radiation metal pattern 39 is the uppermost wiring metal pattern.
Thereby, for example, the layout change of the CrSi thin film resistor 21 can be realized by changing the layout of the CrSi thin film resistor 21 and the uppermost wiring metal pattern, and the degree of design freedom can be improved.

  Further, since the passivation film 23 made of an insulating material is formed on the upper layer of the CrSi thin film resistor 21 except for the thin CrSiN film 29, the other layer than the final protective film is formed on the upper layer of the metal thin film resistor. Compared to the case where an insulating film is also formed, the film thickness variation of the insulating material on the CrSi thin film resistor 21 can be reduced to reduce the film thickness variation. As a result, when the CrSi thin film resistor 21 is irradiated with laser light and subjected to trimming processing, the variation of the laser interference in the insulating material on the CrSi thin film resistor 21 is reduced and applied to the CrSi thin film resistor 21. The variation in the laser energy that is produced can be reduced, and the trimming accuracy can be improved. Furthermore, the heat dissipation capability can be improved against the temperature rise of the CrSi thin film resistor 21 caused by laser irradiation during the trimming process.

  In the above embodiment, the wiring metal patterns 11 and 37 are formed by forming a refractory metal film on the upper surface of the metal material pattern, but the present invention is not limited to this. As the wiring metal pattern, a wiring pattern made of a metal material pattern having no refractory metal film formed on the upper surface may be used. In this case, when, for example, an Al-based alloy is used as the metal material pattern, a strong natural oxide film is formed on the surface of the metal material pattern. It is preferable to perform a step of removing the natural oxide film on the surface of the metal material pattern at the bottom of the connection hole before. The natural oxide film removing step may also be performed in combination with the Ar reverse sputtering treatment for the purpose of suppressing the change in resistance value of the metal thin film resistor with time. The wiring metal pattern is not limited to the one containing an Al-based alloy, and may be a wiring metal pattern made of another metal material such as a Cu wiring formed by a so-called damascene method.

  The metal thin film resistor constituting the semiconductor device of the present invention can be applied to a semiconductor device provided with an analog circuit, for example. Embodiments of a semiconductor device including an analog circuit including a metal thin film resistor according to the present invention will be described below.

FIG. 20 is a circuit diagram showing an embodiment of a semiconductor device provided with a constant voltage generating circuit which is an analog circuit.
A constant voltage generation circuit 47 is provided to stably supply power from the DC power supply 43 to the load 45. The constant voltage generation circuit 47 includes an input terminal (Vbat) 49 to which the DC power source 43 is connected, a reference voltage generation circuit (Vref) 51, an operational amplifier (comparison circuit) 53, and a P channel MOS transistor (hereinafter referred to as an output driver). 55, abbreviated as PMOS), split resistance elements R1 and R2, and an output terminal (Vout) 57.

  In the operational amplifier 53 of the constant voltage generation circuit 47, the output terminal is connected to the gate electrode of the PMOS 55, the reference voltage Vref from the reference voltage generation circuit 51 is applied to the inverting input terminal (−), and the non-inverting input terminal (+). A voltage obtained by dividing the output voltage Vout by the resistance elements R1 and R2 is applied, and the division voltage of the resistance elements R1 and R2 is controlled to be equal to the reference voltage Vref.

FIG. 21 is a circuit diagram showing an embodiment of a semiconductor device provided with a voltage detection circuit which is an analog circuit.
In the voltage detection circuit 59, reference numeral 53 denotes an operational amplifier. A reference voltage generation circuit 51 is connected to an inverting input terminal (−) of the operational amplifier, and a reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vsens) 61 is divided by the dividing resistance elements R1 and R2 and input to the non-inverting input terminal (+) of the operational amplifier 53. The output of the operational amplifier 53 is output to the outside through an output terminal (Vout) 63.

  In the voltage detection circuit 59, when the voltage of the terminal to be measured is high and the voltage divided by the dividing resistance elements R1 and R2 is higher than the reference voltage Vref, the output of the operational amplifier 53 is maintained at the H level and should be measured. When the voltage at the terminal drops and the voltage divided by the dividing resistance elements R1 and R2 becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 53 becomes L level.

  In general, in the constant voltage generation circuit shown in FIG. 20 and the voltage detection circuit shown in FIG. 21, the reference voltage Vref from the reference voltage generation circuit fluctuates due to variations in the manufacturing process. For example, the resistance value of the divided resistive element is adjusted by using a resistive element circuit (referred to as a divided resistive circuit) whose resistance value can be adjusted by laser irradiation to the resistive element as the divided resistive element.

  FIG. 22 is a circuit diagram showing an example of a divided resistor circuit to which the metal thin film resistor of the present invention is applied. FIG. 23 is a layout diagram illustrating a layout example of the coarse adjustment resistor element and the fine adjustment resistor element in the divided resistor circuit.

As shown in FIG. 22, a resistance element Rbottom, a coarse adjustment resistance element 65, a fine adjustment resistance element 67, and a resistance element Rtop are connected in series.
As shown in FIG. 23, the coarse adjustment resistor element 65 is formed by connecting a plurality of strip-shaped metal thin film resistors 21a in parallel. The fine adjustment resistance element 67 is constituted by a plate-shaped metal thin film resistor 21a. A heat radiation metal pattern 13 is disposed under the metal thin film resistors 21a and 21b via an insulating film (not shown). As the metal thin film resistors 21a and 21b, metal thin film resistors constituting the present invention are used. In FIG. 23, only the metal thin film resistors 21a and 21b and the heat radiating metal pattern 13 are illustrated, and illustration of the connection holes, the second heat radiating metal pattern, the opening, and the like is omitted. In FIG. 23, the metal pattern for wiring and the metal pattern 13 for heat dissipation are arranged separately from each other, but the present invention is not limited to this.

  In such a divided resistor circuit, as shown in FIG. 23, for example, as shown by a laser beam locus 25a, an arbitrary number of metal thin film resistors 21a are cut or altered to be insulated, and as shown by a laser beam locus 25b. A desired series resistance value can be obtained by cutting or altering any region of the metal thin film resistor 21b.

  According to the metal thin film resistor and the heat radiating metal pattern constituting the semiconductor device of the present invention, even when laser light having sufficient intensity to cut or alter the metal thin film resistor is irradiated during the laser trimming process, the laser beam is irradiated. Can be prevented from being irradiated to the semiconductor substrate, and the accuracy of the output voltage of the divided resistor circuit shown in FIG. 22 can be improved.

When the divided resistor circuit shown in FIG. 22 is applied to the divided resistor elements R1 and R2 of the constant voltage generating circuit shown in FIG. 20, for example, the resistor element Rbottom end is grounded and the resistor element Rtop end is connected to the drain of the PMOS 55. . Further, the terminal NodeL between the resistance element Rbottom and the fine adjustment resistance element 67 or the terminal NodeM between the resistance element Rtop and the coarse adjustment resistance element 65 is connected to the non-inverting input terminal of the operational amplifier 53.
Since the accuracy of the output voltage of the divided resistor elements R1 and R2 can be improved by the divided resistor circuit to which the metal thin film resistor and the heat radiating metal pattern constituting the present invention are applied, the output voltage of the constant voltage generating circuit 47 is stabilized. Can be improved.

When the divided resistor circuit shown in FIG. 22 is applied to the divided resistor elements R1 and R2 of the voltage detection circuit shown in FIG. 21, for example, the resistor element Rbottom end is grounded and the resistor element Rtop end is connected to the input terminal 93. To do. Further, the terminal NodeL between the resistance element Rbottom and the fine adjustment resistance element 67 or the terminal NodeM between the resistance element Rtop and the coarse adjustment resistance element 65 is connected to the non-inverting input terminal of the operational amplifier 53.
The accuracy of the output voltage of the divided resistor elements R1 and R2 can be improved by the divided resistor circuit to which the metal thin film resistor and the heat radiating metal pattern constituting the present invention are applied. Can be improved.

20 to 23, an example of a semiconductor device to which a divided resistor circuit to which the metal thin film resistor and the heat radiating metal pattern constituting the present invention are applied has been described. The semiconductor device to be applied is not limited to a semiconductor device having a constant voltage generation circuit and a semiconductor device having a voltage detection circuit, and any semiconductor device having a divided resistance circuit can be applied.
Further, the semiconductor device to which the metal thin film resistor and the heat radiation metal pattern constituting the present invention are applied is not limited to the semiconductor device provided with the divided resistor circuit, and may be a semiconductor device provided with the metal thin film resistor. The present invention can be applied.

  The embodiments of the present invention have been described above. However, the present invention is not limited to these, and the dimensions, shapes, materials, arrangements, and the like are examples, and are within the scope of the present invention described in the claims. Various changes can be made.

It is sectional drawing which shows one Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is (A) It is sectional drawing in the BB position. It is an expanded sectional view which expands and shows the part enclosed with the broken line of FIG.1 (B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the Example. It is sectional drawing which expands and shows the state of the connection hole vicinity after giving Ar reverse sputtering process in the manufacturing method of FIG. It is a figure which shows the relationship between the sheet resistance and film thickness of the metal thin film resistor formed by this invention, a vertical axis | shaft shows sheet resistance (ohm / square) and a horizontal axis shows CrSi film thickness (Å). The relationship between the film thickness and the value (σ / AVE) obtained by dividing the standard deviation (σ) of the sheet resistance of the metal thin film resistor formed by the present invention at 63 locations in the wafer surface by the average value (AVE) The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å). The time elapsed since the formation of the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor with and without the Ar reverse sputtering treatment before forming the metal thin film for the metal thin film resistor (A) shows the case where it is performed, (B) shows the case where it is not performed, the vertical axis is the sheet resistance (Ω / □), and the horizontal axis is the elapsed time (hours) after the formation of the base film. ). It is a figure which shows the relationship between the quantity of Ar reverse sputtering processing, and sheet resistance, a vertical axis | shaft shows sheet resistance (ohm / square), and a horizontal axis shows etching amount (thermal oxide film etching amount conversion) (換算). After forming a CrSi thin film for metal thin film resistors, the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance immediately after formation is shown. In the figure, the vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hour). It is a figure showing the results of investigating fluctuations in the metal thin film resistance and metal wiring contact resistance caused by heat treatment for the sample with the refractory metal film remaining at the bottom of the connection hole and the sample completely removed at the time of forming the connection hole. The axis indicates the value normalized by the contact resistance value before heat treatment, and the horizontal axis indicates the number of heat treatments. It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is ( It is sectional drawing in the BB position of A). It is an expanded sectional view which expands and shows the part enclosed with the broken line of FIG. Is a diagram showing the relationship between the resistivity of the N ₂ partial pressure of the gas for CrSiN film formation and CrSiN film, and the vertical axis resistivity [rho (mohms · cm), the horizontal axis represents the N ₂ partial pressure (%). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). It is sectional drawing which shows another Example, (A) is a top view which shows the formation area vicinity of a metal thin film resistor, (B) is sectional drawing in the AA position of (A), (C) is It is sectional drawing in the BB position of (A). 1 is a circuit diagram showing an embodiment of a semiconductor device including a constant voltage generation circuit which is an analog circuit. It is a circuit diagram which shows one Example of the semiconductor device provided with the voltage detection circuit which is an analog circuit. It is a circuit diagram which shows an example of a division resistance circuit. FIG. 10 is a layout diagram illustrating a layout example of a coarse adjustment resistor element and a fine adjustment resistor element in the divided resistor circuit. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing for demonstrating the malfunction at the time of applying another conventional semiconductor device. It is sectional drawing for demonstrating the malfunction at the time of applying another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation oxide film 5 1st layer interlayer insulation film 7 Metal material pattern 9 Refractory metal film 11 First layer wiring metal pattern 13 Heat dissipation metal pattern 15 Base insulation film 17 Connection hole 19 Reverse sputtering residue 21 CrSi thin film resistor 21a, 21b Metal thin film resistor 23 Passivation film 25 Openings 25a, 25b Laser beam locus 27 CrSi thin film 29 CrSiN film 31 Upper layer side insulating film 33 Second connection hole 35 Metal material pattern 37 Refractory metal film 39 Second heat radiation metal pattern 41 Second opening 43 DC power supply 45 Load 47 Constant voltage generation circuit 49 Input terminal 51 Reference voltage generation circuit 53 Operational amplifier 55 P channel MOS transistor 57 Output terminal 59 Voltage detection circuit 61 Input terminal 63 Output terminal 65 Resistance element for coarse adjustment 67 Resistance element R1 for fine adjustment , R2 Split resistance element Rbottom, Rtop Resistance element NodeL, NodeM terminal

Claims (8)

A lower-layer-side insulating film formed on the semiconductor substrate;
A metal pattern for wiring and a metal pattern for heat dissipation formed on the lower insulating film;
A base insulating film formed on the lower insulating film, the wiring metal pattern and the heat dissipating metal pattern;
A connection hole formed in the base insulating film on the metal pattern for wiring;
A metal thin film resistor formed over the base insulating film from the inside of the connection hole and electrically connected to the wiring metal pattern in the connection hole;
A part of the metal pattern for heat dissipation is disposed in a region under the metal thin film resistor ,
An upper insulating film formed on the metal thin film resistor and the underlying insulating film;
A second heat radiation metal pattern made of a metal material disposed on the upper insulating film in a region on the metal thin film resistor except at least a region where the metal thin film resistor is irradiated with laser light is further provided. A semiconductor device.   The semiconductor device according to claim 1, wherein an opening is formed in an insulating film on the heat radiation metal pattern including the base insulating film in a region different from a region where the metal thin film resistor is formed. The semiconductor device according to claim 1 or 2 second opening is formed in an insulating film formed on the second radiating metal pattern. Metal pattern and the second radiator and the heat-dissipating metal pattern according to any one of claims 1-3, which is connected via a second connection hole formed in the base insulating film and the upper insulating film Semiconductor device. At least the upper end portion of the connection hole is formed in a taper shape, and a reverse sputtering residue containing at least the metal pattern for wiring, the material of the base insulating film, and Ar as components is formed on the inner wall of the connection hole. the semiconductor device according to claim 1 which is 4. In a semiconductor device provided with a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by laser irradiation to the resistor elements,
The resistive element is a semiconductor device which is characterized in that it comprises a metal thin film resistor and the radiating metal pattern according to any one of claims 1 to 5. A divided resistor circuit for dividing the input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit In a semiconductor device including a voltage detection circuit having a comparison circuit for comparison,
A semiconductor device comprising the divided resistor circuit according to claim 6 as the divided resistor circuit. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a semiconductor device including a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
A semiconductor device comprising the divided resistor circuit according to claim 6 as the divided resistor circuit.

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