JP4152124B2 - Feedback shift register circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a feedback shift register circuit, and more particularly to a feedback shift register circuit for generating an M-sequence pseudo-random number sequence.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, communication systems using spread spectrum modulation are known in which the spectrum of a large number of signals is spread over a wide band, multiplexed (encrypted), and transmitted by code division multiple access. ing. In this communication method, a process of adding a pseudo random number to the transmission data series by exclusive OR for multiplexing of transmission data is performed. In this case, an M sequence is generally used as a pseudo random number sequence (pseudo noise sequence).
[0003]
As shown in FIG. 9, the M-sequence pseudo-random sequence can be generated by a feedback shift register including m stages of flip-flops. The stage number m of the flip-flop is a value corresponding to the degree of the polynomial for generating the M series.
[0004]
The feedback shift register 100 includes selectors 101-1 to 101-m, and the selectors 101-1 to 101-m switch input data to the flip-flops 102-1 to 102-m.
[0005]
The initial value data DINIT, which is one of the inputs to the selectors 101-1 to 101-m, is an m-bit bus signal, and the bits DINIT-1 to DINIT-m of the initial value data DINIT are respectively selected by the selector 101-. Input to 1 to 101-m.
[0006]
When the initial value setting signal SSET = “1”, the selectors 101-1 to 101-m select the respective bits DINIT-1 to DINIT-m of the corresponding initial value data DINIT. When the initial value setting signal SSET = “0”, the selectors 101-1 to 101-m select the outputs of the preceding flip-flops 102-1 to 102- (m−1), and the selector 101-1 performs the operation. The output of the circuit 221 is selected.
[0007]
When the clock CK is supplied to the flip-flops 102-1 to 102- (m-1), the flip-flops 102-1 to 102- (m-1) hold outputs from the selectors 101-1 to 101- (m-1) in the previous stage as internal states and Are output to the selectors 101-2 to 101-m in the next stage and the multipliers 222-1 to 222- (m-1) in the arithmetic circuit 221.
[0008]
When the clock CK is supplied to the flip-flop 102 -m, the flip-flop 102 -m holds the output from the selector 101 -m in the previous stage as an internal state, and also stores the internal state in the shift result data DRES and the multiplier 222 -m in the arithmetic circuit 221. Output to.
[0009]
The arithmetic circuit 221 calculates a return value to the flip-flop 102-1. The arithmetic circuit 221 includes m multipliers 222-1 to 222-m and (m-1) adders 223-1 to 223- (m-1). The multiplier can be realized by an AND circuit (logical product circuit), and the adder can be realized by an EXOR circuit (exclusive OR circuit).
[0010]
  The feedback coefficient FB, which is one of the inputs to the multipliers 222-1 to 222-m, has a period (2 ^m -1) Is a coefficient for determining a feedback value to the flip-flop 102-1 for generating the M-sequence, and is an m-bit bus signal. Each bit of the feedback coefficient FB is set to FB-1 to FB-m.
[0011]
Each of multipliers 222-1 to 222-m receives the output of flip-flops 102-1 to 102- (m-1) as a multiplied value, and each bit FB-1 of feedback coefficient FB as a multiplied value. ~ FB-m is input.
[0012]
The outputs of the multipliers 222-1 to 222-m are input to (m-1) adders 223-1 to 223- (m-1), and the exclusive logic of the entire multipliers 222-1 to 222-m is obtained. The sum is calculated. The calculation result is output as a feedback value to the flip-flop 102-1.
[0013]
Next, the operation of the feedback shift register shown in FIG. 9 will be described.
[0014]
When the initial value setting signal SSET = "1", the selectors 101-1 to 101-m select the respective bits DINIT-1 to DINIT-m of the initial value data DINIT, and the flip-flops 102-1 to 102- (m Output to -1). When the clock CK is supplied to the flip-flops 102-1 to 102- (m-1), each bit DINIT- of the initial value data DINIT output from the selectors 101-1 to 101- (m-1) in the previous stage is supplied. 1 to DINIT-m are held as internal states.
[0015]
After the initial value data DINIT is set, the flip-flops 102-1 to 102- (m-1) hold the outputs of the preceding flip-flops 102-1 to 102- (m-1) as internal states, and the flip-flop 102 -1 holds the output of the arithmetic circuit 221 as an internal state. The output of the flip-flop 102-m is sequentially output as shift result data DRES. The shift result data DRES is an M series.
[0016]
[Problems to be solved by the invention]
In the conventional feedback shift register 100, the internal state of the flip-flops 102-1 to 102-m is shifted by 1 bit each time the clock is supplied, so that an M-sequence with a shifted phase is required. In this case, there is a problem in that a desired M sequence is not output until the number of clocks corresponding to the phase shift amount is supplied.
[0017]
  In the feedback shift register 100, one cycle (2 ^m -1) Since the M sequence of bits is output bit by bit, it is necessary to ensure the same processing speed as the transmission speed of the transmission data sequence of the encryption source, and as a result, the feedback shift register 100 is required to operate at high speed. There was a point.
[0018]
Accordingly, an object of the present invention is to generate an M-sequence pseudo-random number sequence corresponding to a desired phase shift amount with a small number of clocks, and to transmit an encryption source transmission data sequence that is an output destination of the shift result data DRES. An object of the present invention is to provide a feedback shift register capable of operating at an internal processing speed lower than the above processing speed.
[0019]
[Means for Solving the Problems]
  In order to solve the above problem, a feedback shift register circuit for generating an M-sequence pseudo-random number sequence according to the present invention includes:Entered1 bit of dataIn unitsA shift circuit for shifting;EnteredN (where n isBy a power of 22 or more natural number) bitsIn unitsAn n-shift circuit for shifting;A selection circuit that selects and outputs one of the output of the 1-shift circuit and the output of the n-shift circuit, internally holds data output from the selection circuit, and outputs it as shift data. Data is fed back to the inputs of the 1 shift circuit and the n shift circuit.Shift data generation circuit andThe number of selections of the output of the n shift circuit in the selection circuit is set to the number of integer solutions obtained by dividing the desired number of shifts by n, and the number of selections of the output of the one shift circuit is a remainder generated by the division A selection control circuit that sets the number of the shift data, and a latch circuit that latches the shift data output from the shift data generation circuit at a predetermined timing and outputs the latched data as output data to the outsideIt is provided with.
[0021]
  The latch circuit receives the output data.1 cycle (2 ^m -1) M bits of M-sequence pseudo-random sequence of bitsOutput as dataYou may do it.
[0022]
  further,The shift data generation circuit includes m flip-flops connected in parallel according to the order of a characteristic polynomial for generating the M-sequence pseudo-random sequence,Select circuit outputWhile holding as an internal state and outputting the internal state as an m-bit signal,The m-bit signal1 shift circuit and n shift circuitInputAn m-stage flip-flop circuit that feeds back the signal may be provided.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. First, prior to description of a specific embodiment, an operation principle of a feedback shift register circuit according to the present invention will be described.
[0025]
  In the present embodiment, a circuit for calculating the internal state of each flip-flop after performing a feedback shift operation once for the internal state of the m-stage feedback shift register, and feedback for the internal state of the m-stage feedback shift register Shift operation n times (n = 2 ^x ,n ≧ 2) Mainly characterized by having a circuit that calculates the internal state of each flip-flop after execution, by combining an operation that shifts once per clock and an operation that shifts n times per clock, An M-sequence pseudo-random sequence for a desired phase shift amount is generated with a smaller number of clocks than in the prior art.
[0026]
For example, in order to calculate the M series with the phase shifted by j (j ≧ n), the operation of shifting n by one clock is as follows:
INT (j / n) [times]
(Here, INT (X) represents the integer part of X.)
To perform one shift with one clock,
j- {n × INT (j / n)} [times]
Realize by doing.
[0027]
More specifically, when n = 4 is set, in order to calculate an M sequence in which the phase is shifted by j = 15, an operation of shifting 4 by one clock is performed.
INT (j / 4)
= INT (15/4)
= INT (3.75)
= 3 [times]
Done and the rest
j- {n * INT (j / 4)}
= 15− {4 × INT (15/4)}
= 15− {4 × INT (3.75)}
= 15- {4 × 3}
= 3
By performing the operation of shifting one time by one clock, the M series after j = 15 shift is calculated.
[0028]
In this embodiment, the internal state of the m-stage feedback shift register is output to the outside as a bus signal. Therefore, the m-stage feedback shift register sequentially outputs the m-th value of the flip-flop, so that when the m-th value is output at a certain time t, at the next time (t + 1), the time t The value of the (m−1) th stage at the time is output, and the value of the (m−2) th stage at the time t is output at the time (t + 2). Therefore, if the internal state of the m-stage feedback shift register at a certain time t is output as an m-bit bus signal, an M sequence from time t to time (t + m) can be obtained.
[0029]
  Furthermore, in this embodiment, since an M sequence for an arbitrary phase shift amount can be generated, after an m-bit M sequence is generated once, an m shift is performed with respect to the internal state of the m-stage feedback shift register at that time. The operation of calculating the subsequent internal state and outputting it as an m-bit M series is repeated. As a result, the same M sequence as when the M sequence is sequentially output in the conventional circuit is obtained in m bits. Therefore, one cycle (2 ^m -1It is possible to output M series of bits m bits at a time, eliminating the need to increase the internal operation of the feedback shift register in accordance with the transmission speed of the transmission data of the encryption source.
[0030]
Next, specific embodiments of the feedback shift register circuit according to the present invention will be described.
[0031]
FIG. 1 is a schematic configuration diagram showing an embodiment of a feedback shift register circuit according to the present invention. Note that the initial value setting signal SSET, initial value data DINIT, and feedback coefficient FB input to the present invention are equivalent to signals input to the conventional circuit in terms of signal function, bit width, and the like.
[0032]
The feedback shift register 200 includes a control circuit 210, a 1-shift circuit 220, an n-shift circuit 230, a first selector 240, a second selector 250, an m-stage flip-flop circuit 260, and a latch circuit 270.
[0033]
The control circuit 210 controls the operation of each circuit constituting the feedback shift register 200.
[0034]
The 1-shift circuit 220 generates shift data SD-1 to SD-m based on the shift data SD-1 to SD-m and feedback coefficients FB-1 to FB-m, which are outputs of the m-stage flip-flop 260. A value after the feedback shift operation is executed once (after 1 bit shift) is calculated.
[0035]
The n shift circuit 230 applies the shift data SD-1 to SD-m based on the shift data SD-1 to SD-m and the feedback coefficients FB-1 to FB-m that are the outputs of the m-stage flip-flop 260. A value after the feedback shift operation is executed n times is calculated. Here, the value of n is n = 2.^xCan be arbitrarily set as long as the processing delay of the n shift circuit 230 is smaller than the cycle of the clock CK.
[0036]
The first selector 240 switches between the 1 shift operation and the n shift operation based on the shift number SFN. The second selector 250 uses the input to the m-stage flip-flop 260 as either the output of the first selector 240 or the initial value data DINIT. When the clock CK is supplied when the initial value setting signal SSET is “1”, the m-stage flip-flop circuit 260 sets the initial value data DINIT-1 to DINIT-m output from the second selector 250 as an internal state. Hold. The m-stage flip-flop circuit 260 outputs the output of the first selector 240 output from the second selector 250 when the clock CK is supplied when the enable signal SEN output from the control circuit 210 is “1”. Hold as internal state. The latch circuit 270 executes the feedback shift operation for the number of times set by the shift number SFN, and outputs the obtained shift result as output data DR to the outside.
[0037]
Here, an outline operation of the feedback register 200 will be described. When the clock CK is supplied when the shift number setting signal SNSET is “1”, the control circuit 210 of the feedback register 200 takes in the value of the shift number SFN and based on the fetched shift number SFN, the first selector 240. The number of shifts serving as a switching control signal for selectively switching one of the 1-shift result data DS1R input from the 1-shift circuit 220 and the n-shift result data DSnR input from the n-shift circuit 230 in FIG. A control signal SFC is generated.
[0038]
Similarly, the control circuit 210 generates an enable signal SEN for controlling the timing for holding the input value in the m-stage flip-flop circuit 260 and a latch signal LT for controlling the timing for holding the input value in the latch circuit 270.
[0039]
The 1-shift circuit 220 generates shift data SD-1 to SD-m based on the shift data SD-1 to SD-m and the feedback coefficient bits FB-1 to FB-m, which are outputs of the m-stage flip-flop 260. Then, a value after the feedback shift operation is executed once is calculated, and the obtained calculation result is output to the first selector 240 as one shift result data DS1R.
[0040]
The n shift circuit 230 applies the shift data SD-1 to SD-m based on the shift data SD-1 to SD-m and the feedback coefficients FB-1 to FB-m that are the outputs of the m-stage flip-flop 260. A value after the feedback shift operation is executed n times is calculated, and the calculation result is output to the first selector 240 as n shift result data DSnR.
[0041]
The first selector 240 has a function of switching between a 1-shift operation and an n-shift operation depending on the shift number SFN. When the shift number control signal SFC output from the control circuit 210 is 1, the output of the n shift circuit 230 is selected, and when the shift number control signal SFC is 0, the output of the 1 shift circuit 220 is selected to select the second selector. The selection result is output to 250.
[0042]
The second selector 250 has a function of switching the input to the m-stage flip-flop 260. When the initial value setting signal SSET is 1, the initial value data DINIT is selected. When the initial value setting signal SSET is 0, the output of the first selector 240 is selected and output to the m-stage flip-flop 260.
[0043]
FIG. 2 is a schematic configuration block diagram of the m-stage flip-flop 260. The m-stage flip-flop 260 is roughly divided into flip-flops 261-1 to 261-m connected in parallel.
[0044]
When the initial value setting signal SSET = “1” is supplied to the load terminal Load and the clock CK is supplied to the clock terminal CKT, the flip-flops 261-1 to 261 -m of the m-stage flip-flop 260 are the second ones. The initial value data DINIT-1 to DINIT-m output from the selector 250 and input to each data terminal Data are held as internal states.
[0045]
When the enable signal SEN output from the control circuit 210 shown in FIG. 1 is “1” and the clock CK is supplied, the output of the first selector 240 output from the second selector 250 is held as the internal state. To do.
[0046]
The flip-flops 261-1 to 261-m output the internal state of the flip-flops 261-1 to 261-m as shift data bits SD-1 to SD-m. The shift data SD configured as an m-bit bus signal is output to the latch circuit 270 and fed back to the 1-shift circuit 220 and the n-shift circuit 230.
[0047]
  The latch circuit 270 executes the feedback shift operation for the number of times set by the shift number SFN, and outputs the obtained shift result output data DR to the outside. When the clock CK is supplied when the latch signal LT output from the control circuit 210 is “1”, the latch circuit 270 holds the output of the m-stage flip-flop 260 and outputs it as the shift result output data DR. The shift result output data DR is one cycle (2 ^m -1) M bits of the M sequence of bits.
[0048]
Hereinafter, the detailed configuration and detailed operation of each unit in this embodiment will be described.
[0049]
FIG. 3 is a block diagram illustrating a configuration example of the control circuit 210. FIG. 3 shows, as an example, a circuit configuration when the shift amount n = 4 in the n shift circuit 230 (see FIG. 1) and the shift number SFN is an 8-bit binary signal.
[0050]
The control circuit 210 is roughly divided into a first down counter 211, a first comparator 212, a second comparator 213, a first AND circuit 214, a second down counter 215, a third comparator 216, an OR circuit 217, a flip-flop. 218 and a second AND circuit 219.
[0051]
The first down counter 211 is used to determine how many times the n-shift operation needs to be executed in order to execute the shift operation of the shift amount set as the shift number SFN. When the clock CK is supplied when the shift number setting signal SNSET is “1”, the upper bits of the shift number SFN are held as an internal state. Here, the higher order bits are x bits (2 from the MSB when the MSB is 7 bits and the LSB is 0 bits for the 8-bit shift number SFN.^x= N). Therefore, in the case of FIG. 3, the MSB to 2 bits correspond to the upper bits. In parallel with this, the first down counter 211 executes decrement counting each time the clock CK is supplied while the output of the first comparator 212 is “1”.
[0052]
The first comparator 212 monitors whether the first down counter 211 is operating. The first comparator 212 determines whether the output of the first down counter 211 is “0”. If the output of the first down counter 211 is not “0”, the shift number control signal SFC = “ 1 "is output to the OR circuit 217 and the first down counter 211. In the present embodiment, the n shift operation is performed while the shift number control signal SFC is “1”.
[0053]
The second comparator 213 detects the operation end timing (operation end time) of the first down counter 211. The second comparator 213 determines whether or not the output of the first down counter 211 is “0”. When it is determined that the output is “0”, the second comparator 213 causes the first AND circuit 214 to operate the first down counter 211. “1” indicating the end timing is output.
[0054]
The first AND circuit 214 generates a signal that controls the operation of the second down counter 215. When both the output of the second comparator 213 and the output of the third comparator 216 are “1”, the first AND circuit 214 outputs “1” to the second down counter 215. By the output of the first AND circuit 214, the second down counter 215 causes the internal state of the second down counter 215, that is, the value of the second down counter 215 = 0 after the decrement count of the first down counter 211 is completed (countdown end) It is controlled to operate until it reaches (value).
[0055]
The second down counter 215 is used to determine how many times one shift operation needs to be performed in order to perform the shift operation the number of times set as the shift number SFN. When the clock CK is supplied when the shift number setting signal SNSET is “1”, the lower bits of the shift number SFN are held as the internal state. Here, the low-order bits are (x−1) bits (2 when the MSB is 7 bits and the LSB is 0 bits for the 8-bit shift number SFN.^x= N) to LSB. In the example of FIG. 3, 1 bit to LSB correspond to the lower bits.
[0056]
The second down counter 215 executes decrement counting each time the clock CK is supplied while the output of the first AND circuit 214 is “1”. Specifically, when the clock CK is supplied when the output of the second comparator 213 is “1”, the decrement counting starts, and the clock CK is supplied while the output of the third comparator 216 is “1”. The decrement count is executed every time it is done.
[0057]
The third comparator 216 monitors whether the second down counter 215 is operating. The third comparator 216 determines whether or not the output value of the second down counter 215 is 0, and when the output value of the second down counter 215 ≠ 0, that is, during the operation period of the second down counter 215. “1” is output to the first AND circuit 214 and the OR circuit 217.
[0058]
The OR circuit 217 generates a signal that controls the operation of the m-stage flip-flop 260. When at least one of the output of the first comparator 212 and the output of the third comparator 216 is “1”, “1” is output to the enable signal SEN and the flip-flop 218.
[0059]
As a result, “1” is output from the first comparator 212 during a period in which the feedback shift operation needs to be executed n times in one clock. On the other hand, the third comparator 216 outputs 1 for “1” during a period in which the feedback shift operation needs to be executed once in one clock.
[0060]
Therefore, the OR circuit 217 obtains the logical sum (OR) of the output of the first comparator 212 and the output of the third comparator 216, thereby obtaining a period during which the m-stage flip-flop needs to operate.
[0061]
The second AND circuit 219 generates a latch signal LT that controls the timing at which data is held in the latch circuit 270. The second AND circuit 219 outputs “1” as the latch signal LT when the inverted signal of the OR circuit 217 and the output of the OR circuit 217 output from the flip-flop 218 are both “1”. To do. The second AND circuit 219 outputs “1” as the latch signal LT for one cycle of the clock CK from the changing point where the enable signal SEN changes from “1” to “0”.
[0062]
FIG. 4 is a schematic block diagram showing an example of the 1-shift circuit 220 (see FIG. 1). FIG. 4 shows the configuration of the 1-shift circuit 220 when the number of stages m of the m-stage flip-flop 260 (see FIG. 1) is 64.
[0063]
The internal configuration of the arithmetic circuit 221 is the same as that of the arithmetic circuit 221 shown in FIG. Each of multipliers 222-1 to 222-64 receives shift data SD-1 to SD-64 as outputs of m-stage flip-flop 260 as multiplication values, and feedback coefficients FB-1 to FB- as multiplication values. 64 is entered. The outputs of the multipliers 222-1 to 222-64 are input to 63 adders 223-1 to 223- (m-1), and the exclusive OR of the entire multipliers 222-1 to 222-64 is calculated. The The output of the arithmetic circuit 221 is output as 1-shift result data DS1R-1. The values of the shift data SD-1 to SD-63 are output from the 1 shift result data DS1R (2) to DS1R-64. The flip-flops 261-1 to 261 in the m-stage flip-flop 260 after the 1-shift result data DS1R-1 to DS1R-64 execute the feedback shift operation once for the shift data SD-1 to SD-64. -m Internal state.
[0064]
The n shift circuit 230 (see FIG. 1) is configured by connecting n arithmetic circuits 221 shown in FIG. 4 (arithmetic circuits 221-1 to 221 (n)). FIG. 6 is a block diagram showing a configuration of the n shift circuit 230 when the number of stages m of the m stage flip-flop 260 is m = 64 and the shift amount n = 4 in the n shift circuit 230 is set. Therefore, a signal corresponding to the n-shift result data DSnR in FIG. 1 will be described as a 4-shift result DS4R.
[0065]
In the arithmetic circuit 221-1, shift data SD-1 to SD-64, which are outputs of the m-stage flip-flop 260 (see FIG. 1), are input as multiplication values to the multipliers, and feedback coefficients FB are used as multiplication values. -1 to FB-64 are input. The output of the arithmetic circuit 221-1 is output to the arithmetic circuits 221-2 to 221-4 and the 4-shift result DS4R-4.
[0066]
In the arithmetic circuit 221-2, the output of the arithmetic circuit 221-1 is input as a multiplied value to the multiplier 222-1 (see FIG. 9), and shifted as the multiplied value to the multipliers 222-2 to 222-64. Data SD-1 to SD-63 are input. Feedback coefficient bits FB-1 to FB-64 are input as multiplication values to the multipliers 222-1 to 222-64. The output of the arithmetic circuit 221-2 is output to the arithmetic circuits 221-3 to 221-4 and is output as the 4-shift result DS4R-3.
[0067]
In the arithmetic circuit 221-3, the output of the arithmetic circuit 221-2 is input as the multiplied value to the multiplier 222-1 and the output of the arithmetic circuit 221-1 is input as the multiplied value to the multiplier 222-2. Shift data SD-1 to SD-62 are input as multiplied values to the multipliers 222-3 to 222-64. Feedback coefficients FB-1 to FB-64 are input as multiplication values to the multipliers 222-1 to 222-64. The output of the arithmetic circuit 221-3 is output to the arithmetic circuit 221-4 and the 4-shift result DS4R-2.
[0068]
In the arithmetic circuit 221-4, the output of the arithmetic circuit 221-3 is input as the multiplied value to the multiplier 222-1 and the output of the arithmetic circuit 221-2 is input as the multiplied value to the multiplier 222-2. The output of the arithmetic circuit 221-1 is input as the multiplied value to the multiplier 222-3, and the shift data SD-1 to SD-61 are input as the multiplied values to the multipliers 222-4 to 222-64. The Feedback coefficients FB-1 to FB-64 are input as multiplication values to the multipliers 222-1 to 222-64. The output of the arithmetic circuit 221-4 is output as the 4-shift result DS4R-1.
[0069]
The values of the shift data SD-1 to D-60 are output from the 4-shift results DS4R-5 to DS4R-64.
[0070]
Each of the flip-flops 261-1 to 261- in the m-stage flip-flop 260 after the 4-shift results DS4R-1 to DS4R-64 have executed the feedback shift operation four times for the shift data SD-1 to SD-64. It becomes the internal state of m.
[0071]
In the above description, the case where n = 4 has been described as an example. However, when n is other than 4, if n arithmetic circuits 221 are used and signal lines are connected in the same manner as described above, the shift is performed. It is possible to calculate the internal state of the flip-flop 261 after the feedback shift operation is executed n times for the data SD-1 to SD-m.
[0072]
The operation of the feedback shift register circuit will be described below.
[0073]
6 to 8 show the case where the number m of stages of the m-stage flip-flop 260 shown in FIG. 1 is 64, the shift amount n = 4 in the n shift circuit 230, and the shift number SFN is a binary value signal having an 8-bit width. It is a timing chart which shows the circuit operation of.
[0074]
First, the basic operation of the entire circuit will be described with reference to the timing chart of FIG.
[0075]
FIG. 6 is a timing chart when the shift number SFN = 5 is input.
[0076]
When the clock CK is supplied when the initial value setting signal SSET is “1”, the m-stage flip-flop 260 holds the value of the initial value data DINIT as an internal state, and the initial value is output from the shift data SD.
[0077]
When the clock CK is supplied when the shift number setting signal SNSET is “1”, the control circuit 210 takes in the shift number SFN and generates the shift number control signal SFC and the enable signal SEN.
[0078]
The 1 shift circuit 220 calculates a value (= value after 1 shift) after the feedback shift operation is performed once for the shift data SD (= initial value).
[0079]
The n (= 4) shift circuit 230 calculates a value after the feedback shift operation is performed n = 4 times (= value after 4 shifts) with respect to the shift data SD (= initial value).
[0080]
At this time, since the shift number control signal SFC is 1, the output of the n (= 4) shift circuit 230 (= the value after 4 shifts) is selected by the first selector 240 and output to the m-stage flip-flop 260. The
[0081]
When the clock CK is supplied when the enable signal SEN is “1”, the m-stage flip-flop 260 sets the output of the first selector 240 (the value after 4 shifts) via the second selector 250 as an internal state. While being input and held, it is output as shift data SD.
[0082]
The 1-shift circuit 220 calculates a value (= value after 5 shifts) after further executing a feedback shift operation once for the shift data SD (= value after 4 shifts).
[0083]
The n (= 4) shift circuit 230 calculates a value (= 8 shifted value) after the feedback shift operation is executed four times for the shift data SD (= 4 shifted value).
[0084]
At this time, since the shift number control signal SFC = “0”, that is, the 1 shift circuit 220 side is selected, the output of the 1 shift circuit 220 (= value after 5 shifts) is selected by the first selector 240, and m stages It is output to the flip-flop 260.
[0085]
When the clock CK is supplied when the enable signal SEN = “1”, the m-stage flip-flop 260 holds the output of the first selector 240 (= the value after 5 shifts) as an internal state, and as the shift data SD. Output. When the internal state of the m-stage flip-flop 260 becomes a value after five shifts set to the shift number SFN, the latch signal LT is output from the control circuit 210.
[0086]
  When the clock CK is supplied when the latch signal LT = “1”, the value of the shift data SD (= the value after 5 shifts) is held in the latch circuit 270 and is output as the shift result output data DR. The shift result output data DR is one cycle (2 ^m -1) It corresponds to 1 to m bits of the M series having a phase shift amount of 5 in bits.
[0087]
That is, according to the present embodiment, as shown in FIG. 6, an M sequence after 5 shifts with respect to the initial value is output 3 clocks after the initial value is set in the m-stage flip-flop 260. In order to obtain a similar value in the prior art, it is necessary to supply a clock of 5 clocks, and it can be seen that the processing delay is shortened by this embodiment. Therefore, in the present embodiment, it can be seen that as the number of shifts increases, the amount of processing delay reduction with respect to the prior art increases.
[0088]
The above is the basic operation example of the embodiment. According to the present embodiment, in order to generate an M sequence for an arbitrary phase shift amount by m bits, the shift number setting signal SNSET and the shift number SFN are reset after the series of operations in FIG. The feedback shift operation is performed using the internal state of the m-stage flip-flop 260 at the end of the operation as a new initial value.
[0089]
FIG. 7 shows a timing chart when the shift number SFN is set to 8 after the operation of FIG.
[0090]
  In this embodiment, one cycle (2 ^m -1) Since the M sequence of bits is output by m bits, it is necessary to reset m to the shift number SFN after the output of the m-bit M sequence after any phase shift first. Since the purpose is to explain the circuit operation, the operation when the shift number SFN is set to 8 is shown as an example. In FIG. 7, since the operation up to time A is the same as that in FIG. 6, detailed description thereof is omitted.
[0091]
In the m-stage flip-flop 260, the internal state is updated only when the clock CK is supplied when the enable signal SEN = “1”. Therefore, in the present embodiment configured so that the enable signal SEN = “0” when the operation for the shift set to the shift number SFN is completed, the value at the end of the shift is the internal value of the m-stage flip-flop 260. It is held as a state. More specifically, in FIG. 7, the value after 5 shifts is held as the internal state of the m-stage flip-flop 260 after the shift is completed.
[0092]
After the time A has elapsed, the shift number SFN = 8 is set at a predetermined timing, and when the shift number setting signal SNSET = “1”, the value after 5 shifts held in the m-stage flip-flop 260 is changed to a new initial value. A feedback shift operation is performed.
[0093]
When the clock CK is supplied when the shift number setting signal SNSET = “1”, the control circuit 210 takes in the shift number SFN and generates the shift number control signal SFC and the enable signal SEN.
[0094]
The 1-shift circuit 220 calculates a value (= value after 6 shifts) after performing the feedback shift operation once for the shift data SD (= value after 5 shifts).
[0095]
The n (= 4) shift circuit 230 calculates a value (= 9 shifted value) after the feedback shift operation is performed n (= 4) times for the shift data SD (= 5 shifted value). .
[0096]
Here, since the shift number control signal SFC = “1”, the output of the 4 shift circuit 230 (= the value after 9 shifts) is selected by the first selector 240 and output to the m-stage flip-flop 260. .
[0097]
When the clock CK is supplied when the enable signal SEN = “1”, the m-stage flip-flop 260 holds the output of the first selector 240 (= the value after 9 shifts) as an internal state, and as the shift data SD. Output.
[0098]
The 1-shift circuit 220 calculates a value (= value after 10 shifts) after performing the feedback shift operation once for the shift data SD (= value after 9 shift).
[0099]
The n (= 4) shift circuit 230 calculates a value (= value after 13 shifts) after the feedback shift operation is performed four times for the shift data SD (= value after 9 shifts).
[0100]
Here, since the shift number control signal SFC = “1”, the output of the n (= 4) shift circuit 230 (= the value after 13 shifts) is selected by the first selector 240 and output to the m-stage flip-flop 260. Is done.
[0101]
When the clock CK is supplied when the enable signal SEN = “1”, the m-stage flip-flop 260 holds the output of the first selector 240 (= the value after 13 shifts) as an internal state, and as the shift data SD. Output.
[0102]
When the internal state of the m-stage flip-flop 260 becomes a value after 8 shifts set to the shift number SFN, the control circuit 210 outputs a latch signal LT. When the clock CK is supplied when the latch signal LT is “1”, the value of the shift data SD (= the value after 13 shifts) is held in the latch circuit 270 and is output as the shift result output data DR.
[0103]
As described above, when the shift number setting signal SNSET and the shift number SFN are reset after the shift is completed, m after the shift operation is completed for (shift number set for the first time + shift number set for the second time). An M sequence of bits is obtained. Therefore, after operating with an arbitrary phase shift amount set to the shift number SFN and then operating the circuit with the shift number SFN set to m, the M sequence has an arbitrary phase shift in the first operation. 1 to m bits are output, and an M sequence of (m + 1) to (m + m) bits is output in the second operation. This is an M sequence equivalent to the M sequence generated by the conventional circuit.
[0104]
Next, the operation of the control circuit 210 of this embodiment will be described.
[0105]
FIG. 8 is a timing chart showing the operation of the control circuit 210. FIG. 8 shows an operation of the control circuit 210 when 15 is set as the shift number SFN as an example.
[0106]
When the clock CK is supplied when the shift number setting signal SNSET = “1”, the binary value of the shift number SFN (= 000011111) to the first down counter 211 is a value from MSB to 2 bits “000011”. ”Is set, and“ 11 ”that is a value from 1 bit to LSB of the binary value of the shift number SFN is set in the second down counter 215.
[0107]
The first comparator 212 outputs “1” because the internal state of the first down counter 211 becomes “000001” or more. Further, the third comparator 216 outputs “1” because the internal state of the second down counter 215 becomes “01” or more.
[0108]
The first down counter 211 performs a decrement count every time the clock CK is supplied while the internal state of the first down counter 211 is “000001” or more and the output of the first comparator 212 is “1”. When the internal state of the first down counter 211 becomes “000000”, the operation is stopped.
[0109]
When the internal state of the first down counter 211 becomes “000000”, the first comparator 212 outputs “0”, and the first AND circuit 214 outputs “1”.
[0110]
The second down counter 215 executes a decrement count each time the clock CK is supplied while the internal state of the second down counter 215 is “01” or more and the output of the first AND circuit 214 is “1”. When the internal state of the second down counter 215 becomes “00”, the operation is stopped. When the internal state of the second down counter 215 becomes “00”, the third comparator 216 and the first AND circuit 214 output “0”.
[0111]
The shift number control signal SFC outputs “1” while the output of the first comparator 212 is “1”. The enable signal SEN outputs “1” while either the first comparator 212 or the third comparator 216 is “1”. The flip-flop 218 outputs a signal obtained by delaying the enable signal SEN by one cycle of the clock CK.
[0112]
Accordingly, the latch signal LT output from the control circuit 210 is “1” for a period of one cycle of the clock CK from the point that the internal state of the second down counter 215 becomes “00”.
[0113]
As described above, according to the present embodiment, when the value set in the shift number SFN is larger than the shift amount n in the n shift circuit 230, one shift is performed in one clock using the circuit shown in FIG. By calculating the shift result by combining the operation to be performed and the operation to shift n by 1 clock, it is possible to generate an M sequence for a desired phase shift amount in a shorter time than conventional.
[0114]
  Further, by outputting the internal state of the m-stage flip-flop as shift result output data DR which is an m-bit bus signal, one cycle (2 ^m -1) Since the M series of bits is output in m bits in parallel, a high-speed operation in accordance with the transmission speed of the transmission data of the encryption source is unnecessary.
[0115]
【The invention's effect】
  As described above, according to the present invention, it is possible to generate an M sequence for a desired phase shift amount in a shorter time than in the past. One cycle (2 ^m -1) Since the M series of bits is output in m bits in parallel, a high-speed operation in accordance with the transmission speed of the transmission data of the encryption source is unnecessary.
[Brief description of the drawings]
1 is a schematic configuration diagram showing an embodiment of a feedback shift register circuit of FIG. 1;
2 is a schematic configuration block diagram of an m-stage flip-flop of the feedback shift register circuit of FIG. 1;
3 is a block diagram showing a schematic configuration of a control circuit of the feedback shift register circuit of FIG. 1. FIG.
4 is a schematic configuration block diagram of one shift circuit of the feedback shift register circuit of FIG. 1; FIG.
5 is a schematic configuration block diagram of an n shift circuit of the feedback shift register circuit of FIG. 1. FIG.
6 is an operation timing chart of the embodiment of the feedback shift register circuit of FIG. 1; FIG.
FIG. 7 is an operation timing chart when the shift number SFN is reset after the shift is completed in the feedback shift register circuit according to the present invention.
8 is a circuit operation diagram of a control circuit 210 of the feedback shift register circuit of FIG. 1. FIG.
FIG. 9 is a block diagram showing an example of a conventional feedback shift register circuit.
[Explanation of symbols]
100 Feedback shift register
101 selector
102 flip-flop
200 Feedback shift register
210 Control circuit
211 First down counter
212 First comparator
213 Second comparator
214 First AND circuit
215 Second down counter
216 Third comparator
217 OR circuit
218 flip-flop
219 Second AND circuit
220 1 shift circuit
221 arithmetic circuit
222 multiplier
223 Adder
230 n shift circuit
240 First selector
250 Second selector
260 m-stage flip-flop
261 flip-flop
270 Latch circuit
SSET initial value setting signal
DINIT initial value data
FB feedback coefficient
CK clock
CKT clock terminal
SNSET Shift number setting signal
SFN shift number
DR shift result output data
SFC shift number control signal
SEN enable signal
LT Latch signal
DS1R 1 shift result
DSnR n shift result
SD shift data

Claims (3)

In a feedback shift register circuit for generating an M-sequence pseudo-random sequence,
A 1-shift circuit that shifts input data in 1-bit units ;
An n shift circuit that shifts input data by n (n is a power of 2 and a natural number of 2 or more) bits;
A selection circuit that selects and outputs either the output of the 1 shift circuit or the output of the n shift circuit;
A shift data generation circuit that internally holds data output from the selection circuit and outputs the data as shift data, and feeds back the shift data to inputs of the 1 shift circuit and the n shift circuit ;
The number of selections of the output of the n shift circuit in the selection circuit is set to the number of integer solutions obtained by dividing the desired number of shifts by n, and the number of selections of the output of the one shift circuit is a remainder generated by the division A selection control circuit to set to a number;
A feedback shift register circuit comprising: a latch circuit that latches shift data output from the shift data generation circuit at a predetermined timing and outputs the latched data as output data to the outside . 2. The feedback shift register circuit according to claim 1 , wherein the latch circuit outputs the output data as m-bit data of an M-sequence pseudo-random number sequence of 1 cycle ( 2 ^m −1 ) bits. The shift data generating circuit has m parallel-connected flip-flops in response to the degree of the characteristic polynomial for generating a pseudo-random number sequence of the M-sequence, and holds the output of the selection circuit as the internal state 2. An m-stage flip-flop circuit that outputs the internal state as an m-bit signal and feeds back the m- bit signal to inputs of the 1-shift circuit and the n-shift circuit. Or the feedback shift register circuit of 2.

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