JP4194430B2 - Synchronizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronization device used in an image forming apparatus such as a printer or a copying machine.
[0002]
[Prior art]
In an image forming apparatus such as a laser printer or a copying machine, it is necessary to generate video data (image data) synchronized with a synchronization reference signal BD (for example, a signal indicating that a polygon mirror has reached a specific position). In this case, since the synchronization accuracy affects the print quality, it needs to be equal to or higher than a specific value. Therefore, in order to perform synchronization with an accuracy of 1/8 of the video pixel frequency, the synchronization reference signal BD is sampled using a sampling clock having a frequency eight times the video pixel frequency, and the synchronized synchronization reference signal BD is synchronized. As a trigger, video data is synchronized (for example, see Patent Documents 1 to 3 below). However, when the pixel frequency is increased, the sampling clock becomes a very high frequency, which is a problem.
[0003]
In order to solve this problem, an image signal synchronization circuit as disclosed in Patent Document 4 below has been proposed. This is to generate delayed video data having a plurality of types of delay using a delay element for the video data, and for a plurality of types of delay using a delay element for the horizontal sync signal. A delayed horizontal sync signal is generated, and a plurality of delayed horizontal sync signals are used to detect a phase difference between the horizontal sync signal and the basic clock signal, and select delayed video data corresponding to the phase difference. The same effect as using a high-speed clock is obtained.
[0004]
However, since the image signal synchronization circuit disclosed in Patent Document 4 uses a delay element to generate a clock having a phase difference with respect to the basic clock, it is easily affected by temperature, power supply voltage, process variations, and the like. There is a problem that accuracy deteriorates.
[0005]
This problem can be solved by the technique disclosed in Patent Document 5 below. However, in this technique, since a phase difference detection and output delay adjustment are performed using a clock n times the reference clock instead of the delay element, a high-speed clock must be used. May become unstable.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-250048 [Patent Document 2]
Japanese Patent Laid-Open No. 11-150638 [Patent Document 3]
JP-A-11-216906 [Patent Document 4]
JP 11-245447 A [Patent Document 5]
Japanese Patent Laid-Open No. 11-245446
[Problems to be solved by the invention]
The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to always maintain stable operation even when a high-speed pixel frequency is supplied. It is to provide a possible synchronization device.
[0008]
[Means for Solving the Problems]
To achieve the above object, a synchronization device according to claim 1 of the present invention is a synchronization device that synchronizes with a reference trigger signal that is generated asynchronously and starts data output. By sampling at, the timing of the reference trigger signal is detected with an accuracy finer than one cycle of the sampling clock, and when the detection result is passed to an operation unit that operates with a clock having a phase different from that of the sampling clock, Reference trigger timing detection means that allows a timing delay longer than one period of the sampling clock is provided, and the reference trigger timing detection means latches the sampling results in order for one of the sampling results with clocks having different phases. A plurality of latch means for A temporary retaining means, the work by a different operating clock and temporary storage means, characterized by comprising a selector means for receiving selects the output of the temporary holding means.
[0009]
According to the first aspect of the present invention, it is possible to always maintain a stable operation even when a high-speed pixel frequency is supplied.
[0012]
According to a second aspect of the present invention, there is provided the synchronization device according to the first aspect, further comprising polarity control means for inverting the polarity of the reference trigger signal.
[0013]
According to the second aspect of the present invention, since the polarity of the reference trigger signal can be inverted, it is possible to cope with both the rising edge / falling edge of the reference trigger signal.
[0014]
According to a third aspect of the present invention, there is provided the synchronization device according to the first or second aspect, wherein a timing delay longer than one cycle of the operation clock is set, and the data output timing is set to be longer than one cycle of the operation clock. Data output timing control means is provided for controlling the data at fine timing and outputting the data to an operation unit using a clock different from the operation clock.
[0015]
According to the third aspect of the present invention, it is possible to always maintain a stable operation even when a high-speed pixel frequency is supplied.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a synchronization apparatus of the present invention, and shows an example incorporated in a video DMA controller (controller used in a laser printer). The synchronization apparatus 100 includes a phase difference clock generation unit 101, a reference trigger timing detection unit 102, and a video / data output timing control unit 103, and is incorporated in the video DMA controller 110. The video DMA controller 110 also includes a video DMA control register 111.
[0017]
The frame gate (FGATE_N) signal is a synchronization signal indicating whether or not it is time to transfer data in the area of one page to a plotter (not shown). The reference trigger (BD_N) signal is a signal that defines a reference operation timing. Regarding the reference timing, a change from a low level to a high level is a reference timing, or a change from a high level to a low level is a reference timing. For this reason, the polarity can be switched by the setting of the polarity control register 112 provided in the video DMA control register 111 described later. The video data (VD) signal is a signal that becomes image data output by the plotter. This VD signal is a 1-bit asynchronous interface signal, and must be output in accordance with the timing of the BD_N signal with high accuracy. If this synchronization accuracy is poor, the output image will be an image with a shift for each line.
[0018]
The phase difference clock generation unit 101 corresponds to a clock (CLK [3: 0]) whose phase is shifted by 90 degrees and each other clock, and is started delayed (START [3: 0]) signal is output. This signal is supplied to the reference trigger timing detection unit 102 and the video / data output timing control unit 103, and is used for the initialization timing of the clock and the internal selector, respectively. Upon receiving the reference trigger (BD_N) signal, the reference trigger timing detection unit 102 indicates in the video DMA control register 111 SYNC_OUT [3] which phase of the clocks whose phases are shifted by 90 degrees is detected first. : 0] signal to notify. The video / data output timing control unit 103 receives the video data (VD_S) and the timing information (OUTTIM [3: 0]) on which phase the video data (VD_S) is output from the video DMA control register 111, and the video data corresponding to the content. Is output as a VD signal. The video DMA control register 111 includes a plurality of video DMA control registers, and performs sequence control of the entire video DMA controller 110. Also, the internal polarity control register 112 sends an INV signal to the reference trigger timing detection unit 102 to control the polarity of the reference trigger.
[0019]
FIG. 2 is a block diagram illustrating a detailed configuration of the reference trigger timing detection unit 102. A reference trigger (BD_N) signal is supplied to the register 201 (REG [0]), the register 202 (REG [1]), the register 203 (REG [2]), and the register 204 (REG [3]). Further, these registers are supplied with clocks (CLK [0], CLK [1], CLK [2], CLK [3]) delayed in phase by 90 degrees from the phase difference clock generator 101, respectively. For this reason, the state of BD_N is sampled sequentially from the register 201 (REG [0]) supplied with CLK [0] that is advanced in the first phase.
[0020]
First, a configuration of the subsequent stage of the register 202 (REG [1]), the register 203 (REG [2]), and the register 204 (REG [3]) will be described. Since the subsequent stage of the register 202 (REG [1]), the register 203 (REG [2]), and the register 204 (REG [3]) has the same configuration, the configuration of the subsequent stage of the register 202 (REG [1]) is described here. Only explained.
[0021]
The output of the register 202 (REG [1]) is supplied to the selector 205 and the selector 206. These selectors select whether to supply their own output or the output of the register 202 (REG [1]) to the registers 207 and 208. Both the selector 205 and the selector 206 are controlled by a SEL [1] B signal. When the selector 205 selects the output of the register 202 (REG [1]), the selector 206 is configured to be opposite to each other so that the output of the register 208 is selected. Therefore, the timings at which the registers 207 and 208 are updated are different from each other. Since the signal of SEL [1] B toggles every 1CLK [1], the registers 207 and 208 are updated at different timings every 2CLK [1]. Outputs of the registers 207 and 208 are supplied to the selector 209. In the selector 209, one of the outputs of the registers 207 and 208 is selected by the SEL [0] B signal that changes in synchronization with CLK [0] and is supplied to the register 210 (SREG [1]). The output of the register 210 (SREG [1]) is supplied as SYNC_OUT [1] to the CLK [0] operation region as a synchronization signal of CLK [0].
[0022]
The configuration of the subsequent stage of the register 201 (REG [0]) is different from the configuration of the subsequent stage of the register 202 (REG [1]), and is configured as a three-stage shift register including registers 211, 212, and 213. Since the register 201 (REG [0]) operates in synchronization with CLK [0], a circuit for synchronizing with CLK [0] is not necessary. However, in order to synchronize timing with other circuit configurations, 3 A stage shift register is configured. By these circuits, SYNC_OUT [3: 0] signals of SYNC_OUT [0], SYNC_OUT [1], and SYNC_OUT [2] synchronized with SCLK [0] are generated.
[0023]
The registers 214, 215, 216, and 217 are registers for generating a toggle signal, and the contents are the same except that the bit numbers of the input / output signals are different. These operate with clocks having different phases, and after the START signal becomes high level, the state is inverted for each clock and the SELB signal is output.
[0024]
FIG. 3 is a timing chart for explaining the operation of the reference trigger timing detection unit 102 shown in FIG. CLK [0] is a clock without phase delay output from the phase difference clock generation unit 101. CLK [1], CLK [2], and CLK [3] are clocks with a phase delay of 90 degrees with respect to CLK [0], CLK [1], and CLK [2], respectively. START [0] is a start signal corresponding to CLK [0] and is asserted after the reset signal is released to the entire circuit. START [1], START [2], and START [3] correspond to CLK [1], CLK [2], and CLK [3], respectively, and are asserted after their phases are delayed by 90 degrees.
[0025]
SEL [0] B, SEL [1] B, SEL [2] B, and SEL [3] B are outputs of the registers 214, 215, 216, and 217 shown in FIG. The initial value is at a low level, and when the corresponding START signal is at a high level thereafter, the state is inverted when the rising edge of the corresponding clock (the number-matching clock) is detected.
[0026]
REG [0], REG [1], REG [2], and REG [3] are a register 201 (REG [0]), a register 202 (REG [1]), a register 203 (REG [ 2]), an output signal of the register 204 (REG [3]). For example, in the case of the phase delay zero register of the second data, it is indicated as D2_0. REG_D1 [0] and REG_D2 [0] indicate the outputs of the registers 211 and 212 that are configured in the subsequent stage of the register 201 (REG [0]). SYNC_OUT [0] is an output of the register 213.
[0027]
Since REG [1] operates at CLK [1], which is a clock delayed by 90 degrees, output data changes in synchronization with this clock. REG [1] _AOUT indicates the output of the register 207, and is updated at the rising edge of CLK [1] when SEL [1] B is low. On the other hand, REG [1] _BOUT indicates the output of the register 208, and is updated at the rising edge of CLK [1] when SEL [1] B is high.
[0028]
REG [1] _SELOUT is the output of the selector 209. When SEL [0] B is high level, the output of the register 208 (REG [1] _BOUT) is selected, and when it is low level, the output of the register 207 (REG [1] ] _AOUT). Note that since this selection is performed by the signal SEL [0] B that is synchronized with CLK [0], REG [1] _SELOUT is synchronized with CLK [0]. SYNC_OUT [1] is a result of re-synchronizing REG [1] _SELOUT with the register 210 (SREG [1]) that synchronizes with CLK [0]. It should be noted that by providing a “temporary holding unit” composed of the registers 207 and 208, the contents of the registers 207 and 208 of the “temporary holding unit” are held, and then SYNC_OUT [1 ] Is longer than one clock period until the data is received. As a result, the timing constraint when transferring data between clocks having different phases is relaxed, and stable operation is maintained even when a high-speed clock is supplied. The same applies to the CLK [2] and CLK [3] systems.
[0029]
Also, SYNC_OUT [0] to SYNC_OUT [3] indicate data having different phases only at the same timing, and a reference trigger is generated at any phase timing by a signal synchronized with CLK [0]. You can recognize if it occurred.
[0030]
Here, considering a case where a rising edge of BD_N is detected, BD_N changes from a low level to a high level in a broken line portion shown in FIG. After this, the high level can be detected first when REG [0] is D5_0. Further, REG [1] is D5_90. In REG [2], the time is D4_180. In REG [3], the time is D4_270. Therefore, SYNC_OUT [3: 0] for D4 gives a result of 1100 (bin), and it is recognized that the detection was first performed with a phase delay of 180 degrees with respect to D4.
[0031]
FIG. 4 is a block diagram showing a detailed configuration of the video / data output timing control unit 103. In FIG. 4, VD_S is the base data of the video output, and is a signal synchronized with the clock having the same phase as CLK [0]. OUTTIM [3: 0] is timing control information of video output data, and only 1 bit out of 4 bits of OUTTIM [3: 0] is “1” and “1”. Output in synchronization with the clock of the phase corresponding to. Note that OUTTIM [0] has a phase delay of 0, OUTTIM [1] has a phase delay of 90 degrees, OUTTIM [2] has a phase delay of 180 degrees, and OUTTIOM [3] has a phase delay of 270 degrees. .
[0032]
The selectors 401 and 402 are selectors that select the outputs of the registers 403 and 404, which are configured in the subsequent stages, or the VD_S signal, respectively. This is controlled by the contents of the output SEL [0] B of the register 414. The selectors 401 and 402 are configured so as not to select the VD_S signal at the same time, one selects the VD_S signal and the other selects the output of the register 403 or the register 404. The registers 403 and 404 are registers for holding the contents of the VD_S signal and are updated at a rate of once every two clocks, but the registers 403 and 404 are updated at different timings.
[0033]
Outputs of the registers 403 and 404 are supplied to selectors 408, 409, and 410. These selectors are controlled by SEL [1] B, SEL [2] B, and SEL [3] B which are outputs of the registers 415, 416, and 417. Note that these signals are synchronized with the respective clocks supplied to the registers 411, 412, and 413 that are configured in the subsequent stage of the selectors 408, 409, and 410. Unlike the other systems, the register 405 operates for the clock having the same phase as that of the VD_S signal. Therefore, the processing for transferring between phases is not required, and the register 405 is provided for timing adjustment with the other system. Is a registered register. The selector 407 selects an input in accordance with the contents of OUTTIM [3: 0], and sends it to a plotter (not shown) as a video output signal (VD). At this time, the output of the register 406 is output when OUTTIM [0] is “1”, the output of the register 411 is output when OUTTIM [1] is “1”, and the register 412 is output when OUTTIM [2] is “1”. When OUTTIM [3] is “1”, the output of the register 413 is selected and output as VD.
[0034]
The phase difference clock generation unit 101 supplies clocks (CLK [0], CLK [1], CLK [2], CLK [3]) whose phases are delayed by 90 degrees. Registers 414, 415, 416, and 417 are registers for generating a toggle signal. These operate with clocks having different phases, and after the START signal becomes high level, the state is inverted for each clock and the SELB signal is output.
[0035]
FIG. 5 is a timing chart for explaining the operation of the video / data output timing control unit 103 shown in FIG. CLK [0] is a clock without phase delay output from the phase difference clock generation unit 101. CLK [1], CLK [2], and CLK [3] are clocks with a phase delay of 90 degrees with respect to CLK [0], CLK [1], and CLK [2], respectively. START [0] is a start signal corresponding to CLK [0] and is asserted after the reset signal is released to the entire circuit. START [1], START [2], and START [3] correspond to CLK [1], CLK [2], and CLK [3], respectively, and are asserted after their phases are delayed by 90 degrees.
[0036]
SEL [0] B, SEL [1] B, SEL [2] B, and SEL [3] B are outputs of the registers 414, 415, 416, and 417 shown in FIG. The initial value is at a low level, and when the corresponding START signal is at a high level thereafter, the state is inverted when the rising edge of the corresponding clock (the number-matching clock) is detected. VD_S is basic data of video output and is a signal synchronized with a clock having the same phase as CLK [0]. VREG_AOUT captures the contents of VD_S at the rising edge of CLK [0] when SEL [0] B is low. VREG_BOUT captures the contents of VD_S at the rising edge of CLK [0] when SEL [0] B is high.
[0037]
REG [1] _SELOUT selects VREG_AOUT when SEL [1] B is high, and selects VREG_BOUT when SEL [1] B is low. REG [1] _OUT is obtained by capturing REG [1] _SELOUT at the rising edge of CLK [1]. Similarly, REG [2] _SELOUT selects VREG_AOUT when SEL [2] B is high, and selects VREG_BOUT when SEL [2] B is low. REG [2] _OUT is obtained by capturing REG [2] _SELOUT at the rising edge of CLK [2]. The same applies to REG [3] _SELOUT and REG [3] _OUT. VD_S_D1 is a signal delayed by 1 CLK [0] of VD_S, and REG [0] _OUT is a signal delayed by 1CLK [0] of VD_S_D1.
[0038]
Since the video data output timing control unit 103 can arrange the video data having different phases by 90 degrees in this way, one output is selected according to the state of OUTTIM [3: 0] and is output as VD. Thus, the data output timing can be controlled at a timing finer than one cycle of the operation clock. In addition, there is a time longer than one clock period from the output of VREG_AOUT and VREG_BOUT to the reception of a register operating with a clock of a different phase. Even when a timing restriction at the time of data transfer is relaxed and a high-speed clock is supplied, the operation does not become unstable, and video data can be output at a stable timing.
[0039]
The embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to the matters shown in this embodiment, and can be changed or improved based on the description of the scope of claims.
[0040]
【The invention's effect】
The synchronization device of the present invention allows a timing delay longer than one period of the sampling clock to be present when the sampling result of the reference trigger signal is transferred to the operation part using a clock different from the sampling clock. Even if the pixel frequency is increased, the operation does not become unstable, and the stable operation can be always maintained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a synchronization device of the present invention, and shows an example incorporated in a video DMA controller.
FIG. 2 is a block diagram showing a detailed configuration of a reference trigger timing detection unit.
FIG. 3 is a timing chart for explaining the operation of a reference trigger timing detection unit.
FIG. 4 is a block diagram showing a detailed configuration of a video data output timing control unit.
FIG. 5 is a timing chart for explaining the operation of a video / data output timing control unit;
[Explanation of symbols]
100 Synchronizer 101 Phase Difference Clock Generation Unit 102 Reference Trigger Timing Detection Unit 103 Video Data Output Timing Control Unit 110 Video DMA Controller 111 Video DMA Control Register 112 Polarity Control Registers 201-204, 207, 208, 210-217, 403 ˜406, 411˜417 Register 205, 206, 209, 401, 402, 407˜410 Selector

Claims (3)

In the synchronization device that synchronizes with the reference trigger signal generated asynchronously and starts data output,
By sampling the reference trigger signal with a clock having a different phase, the timing of the reference trigger signal is detected with an accuracy finer than one cycle of the sampling clock, and the detection result is operated with a clock having a phase different from that of the sampling clock. A reference trigger timing detection means that allows a timing delay longer than one period of the sampling clock when passing to the operating unit to perform ,
The reference trigger timing detection means is
Temporary holding means composed of a plurality of latch means for sequentially latching the sampling results for one of the sampling results with clocks having different phases;
Selector means that operates with an operation clock different from that of the temporary holding means, and that selectively receives an output of the temporary holding means;
Synchronization apparatus characterized by comprising a. The synchronization device according to claim 1, further comprising polarity control means for inverting the polarity of the reference trigger signal. A timing delay longer than one cycle of the operation clock is set, the data output timing is controlled at a timing finer than one cycle of the operation clock, and the data is output to the operation unit using a clock different from the operation clock. The synchronization apparatus according to claim 1, further comprising a data output timing control unit.

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