JP4196001B2 - Semiconductor power module - Google Patents

Description

  The present invention relates to a semiconductor power module, and more particularly to a module that drives a large current at a high frequency.

  A semiconductor power module includes a main circuit including a power semiconductor that is a semiconductor element for power control and a control circuit including a driver IC that is a semiconductor element that controls the operation of the circuit by exchanging signals with the circuit. Are incorporated into one device.

  Examples of conventional semiconductor power modules are shown in FIGS. FIG. 10 is a plan view of a circuit board of the semiconductor power module disclosed in Patent Document 1. FIG. FIG. 11 is a cross-sectional view of the circuit board shown in FIG.

  In FIG. 10, IGBT1 to IGBT6 are insulated gate bipolar transistors (hereinafter referred to as power semiconductors), and D1 to D6 are flywheel diodes (hereinafter referred to as diode elements) connected in reverse parallel to the power elements IGBT1 to IGBT6, respectively. IC1 to IC3 are high-side control ICs 4 and low-side control ICs (hereinafter referred to as driver ICs), which are connected to the gates of the corresponding power elements IGBT1 to IGBT6, respectively.

  10 and 11, the insulating metal substrate 101 is composed of a metal plate 102, an insulating layer 103, and a copper foil pattern 104. The copper foil pattern 104 is a main circuit pattern on which the power semiconductor element 120 is mounted. Part 104 a and control circuit pattern part 104 b on which the control semiconductor element 121 is mounted, and are electrically connected by connection lines 122 to 124. One end of each of the power lead terminal 105 and the control lead terminal 106 is soldered to the main circuit pattern portion 104a and the control circuit pattern portion 104b. Reference numeral 107 denotes a case for housing the insulating metal substrate 101, the power semiconductor element 120, the control semiconductor element 121, and the like. The other end of the power lead terminal 105 and the control lead terminal 106 penetrates the case 107 and is exposed to the outside. External lead terminals are formed.

  In the cross-sectional view of the circuit board shown in FIG. 11, the six power semiconductors IGBT1 to IGBT6 and the diode elements D1 to D6 shown in FIG. 10 are collectively shown as a power semiconductor element 120, which is a control IC 3 The high-side control elements IC1 to IC3 and the single low-side control element IC4 are collectively shown as a control semiconductor element 121. Further, the main current input terminals P and N of the power semiconductors IGBT1 to IGBT6 and the main current output terminals U, V, and W are used as power lead terminals 105, and the control signal input terminals UP, VP, WP, and UN of the control elements IC1 to IC3 are used. , VN, WN, grounding terminal GND, etc. are shown as control lead terminals 106.

  With the above configuration, the driver ICs IC1 to IC4 receive signals from the outside and output drive signals to the corresponding power semiconductors IGBT1 to IGBT6, and the power semiconductors IGBT1 to IGBT6 receive the terminals P, The DC input from N is turned ON and OFF, and an AC output of an arbitrary frequency is supplied from a terminal U, V, W to a three-phase motor (not shown) as a load. That is, the driver IC, IC1, IC4 outputs a drive signal to the corresponding power semiconductor IGBT1, IGBT4 by inputting an external control signal, respectively, and the power semiconductor IGBT1 is turned on and the power semiconductor IGBT4 is turned off by inputting these drive signals. Thus, the main current input from the terminal P is output to the three-phase motor (not shown) via the terminal U.

  As is apparent from FIG. 10, in the conventional semiconductor power module, the control lead terminal for outputting the output current of each power semiconductor to the outside includes the circuit pattern portion to which each power semiconductor is fixed and the upper electrode of the power semiconductor. And only one each from the circuit pattern part connected by the metal fine wire. In addition, each power semiconductor is soldered on a circuit pattern having a certain distance from the power lead terminal, and the circuit pattern for electrically connecting the power lead terminal and the power semiconductor is inevitably narrow and wraps around. Formed in shape. Furthermore, the thin metal wire that electrically connects the upper electrode of the power semiconductor and the circuit pattern is inevitably longer for the same reason as described above.

  FIG. 12 is a cross-sectional view of the power lead terminal of the semiconductor power module disclosed in Patent Document 2 and the peripheral portion of the circuit board.

In FIG. 12, two power supply terminals PS (P) and PS (N) constituted by plate-like conductors are arranged with each other with a plate-like insulating sheet INS1 made of synthetic resin or the like sandwiched therebetween. Proximity is provided. The power supply terminals PS (P) and PS (N) are electrically connected to the wiring patterns P (P) and P (N), respectively. The thickness of the insulating sheet INS1 is, for example, 0.5 mm to 1.5 mm. For this reason, the currents flowing through these power supply terminals PS (P) and PS (N) flow almost in close contact with each other across the insulating sheet INS1, and the flowing directions thereof are antiparallel to each other. As a result, parasitic generation occurs in a path formed by the power supply terminal PS (P), the wiring pattern P (P), the IGBT element (not shown), the wiring pattern P (N), and the power supply terminal PS (N). Inductance is reduced.
JP 2000-133768 A Japanese Patent Laid-Open No. 6-21323

  In a semiconductor power module that handles a large current at a high frequency of a driving frequency of 10 kHz or more, the time change rate di / dt of the current from ON to OFF and from OFF to ON increases by increasing the switching time.

  However, in the conventional configuration shown in Patent Document 1, the circuit pattern and terminal distance of the power source current path that flows from the main current input terminal P to the main current input terminal N through the main current output terminals U, V, and W are long. Inevitably, the routing of the current path becomes longer, and the inductance L parasitically generated in the power source current path becomes larger. As a result, a surge voltage or radiation noise having a magnitude of Ldi / dt is generated by the inductance L at the time of switching, causing electrical noise, causing malfunction of the circuit of the device, and further causing circuit elements to be destroyed.

  In another conventional configuration shown in Patent Document 2, the wiring patterns P (P) and P (N) connected to the main power supply terminals PS (P) and PS (N) have their main parts adjacent to each other. The main power supply terminals PS (P) and PS (N) have substantially different directions of power supply currents flowing through the wiring patterns P (P) and P (N), respectively. So as to be antiparallel to each other. For this reason, the inductance generated parasitically in the path of the main power supply current is reduced, but the main power supply terminals PS (P) and PS (N) and the wiring patterns P (P) and P (N) are provided close to each other. For this reason, the terminal length and circuit pattern routing are inevitably increased, and the wiring resistance generated in the current path is increased. Further, since the terminals and the circuit pattern are formed by three-dimensional wiring, there is a problem that the degree of freedom of wiring is small, the structure is complicated, and the manufacturing cost is expensive.

  Furthermore, since no attempt has been made to reduce the inductance generated in the current path from the main power supply terminal to the output terminal, a surge voltage is applied to the output signal, which may cause malfunction of the device.

  In view of the above, an object of the present invention is to provide a semiconductor power module that reduces parasitic inductance and wiring resistance of a large current path of a power semiconductor and realizes high frequency and large current driving.

In order to solve the above problems, a semiconductor power module according to the present invention includes a metal base printed board in which a conductive circuit pattern is formed on an electrically insulating layer disposed on one main surface of a metal board, and the circuit. At least one power semiconductor fixed on the pattern and a driver IC for driving the power semiconductor, and the upper electrode of the power semiconductor element and the circuit pattern are electrically connected by a thin metal wire A semiconductor power module, wherein at least one of a group of metal lead terminals having the same potential for electrically connecting the semiconductor power module and the outside is connected to the metal base printed circuit board via a lead terminal support. an internal lead terminal is a structure having an external lead terminal connected to the external terminal pitch of the inner lead terminal The external lead smaller than inter-terminal pitch of the terminals, the terminal number of said inner lead terminals larger than the number of terminals of the external lead terminals, the pitch between terminals of the parts to be connected to an external of the metal lead terminal group are the same It is characterized by that.

A circuit pattern having power lead terminals for electrically connecting the power semiconductor and the outside is provided, the circuit pattern to which the power semiconductor is fixed, an upper electrode of the power semiconductor and a metal wiring In the connected circuit pattern and the circuit pattern in which the power lead terminal is installed, it is preferable that a slit or groove for subdividing the current path is formed in each circuit pattern.

  The group of metal lead terminals having the same potential is composed of at least three metal lead terminals connected to the metal base substrate side and at least two metal lead terminals connected to the outside. It is preferable to have one or more lead terminal support parts for changing the lead terminal pitch in the part.

  The metal lead terminal group is preferably attached to a plurality of locations on the metal base printed board.

Another semiconductor power module according to the present invention is fixed to a metal base printed board having a conductive circuit pattern formed on an electrically insulating layer disposed on one main surface of the metal board, and the circuit pattern. The semiconductor power module has at least one power semiconductor and a driver IC for driving the power semiconductor, and electrically connects the upper electrode of the power semiconductor element and the circuit pattern by a thin metal wire. Te, the power lead terminal for a main electrode connected to the outside of the power semiconductor has a narrow pitch between terminals than the control lead terminal for connecting the electrodes of the driver IC with an external, and subdivide the current path A plurality of metal lead terminals having the same potential are connected in parallel .

  The power lead terminals are preferably arranged in a staggered pattern when viewed from the direction in which the lead terminals extend, with each lead terminal being spaced apart and arranged in two or more stages.

Preferably, the power lead terminal is formed in a plate shape and is provided with slits or grooves for subdividing the current path.

  Of the internal lead terminals in the power lead terminal, at least one internal lead terminal preferably has a longer lead length than the others.

  An inner case integrally formed with the metal lead terminal for housing the metal base printed board, the power semiconductor, and the driver IC therein, and the inner case is filled, and the power semiconductor and the driver IC are sealed. More preferably, a sealing resin that stops is provided.

  More preferably, a half bridge circuit is formed by the plurality of power semiconductors, and an output terminal for outputting a large current pulse is further provided.

  According to the semiconductor power module of the present invention, a plurality of metal lead terminals arranged in the main power supply current path and the external output current path are connected in parallel, so that the current path is subdivided, and the parasitic inductance of the terminals is reduced. There is a reduction effect.

  As a result, the surge voltage and radiation noise during switching are reduced, which has the effect of preventing malfunction of the circuit of the device and destruction of the circuit element, and a motor drive device that requires high frequency and high current drive. It is suitable as a driving device for a plasma display panel.

  Further, since the lead terminal support portion is provided between the plurality of terminals, there is an effect of increasing the connection strength of the terminals. Further, by making the pitch between terminals uniform, there is an effect that the product substrate layout can be easily made. Furthermore, since there is a terminal having a long lead length among the plurality of terminals, there is an effect that positioning when the module is mounted on the external substrate can be facilitated.

In addition to the configuration of the semiconductor power module described above, the circuit pattern in which the power semiconductor is fixed, the circuit pattern connected to the upper electrode of the power semiconductor with metal wiring, and the circuit pattern in which the power lead terminal is installed Since the slit or groove for subdividing the current path is formed, there is an effect of reducing the inductance and resistance components parasitic on the circuit pattern and the metal thin wire.

  As a result, the surge voltage and radiation noise during switching are reduced, which has the effect of preventing malfunction of the circuit of the device and destruction of the circuit element, and a motor drive device that requires high frequency and high current drive. It is suitable as a driving device for a plasma display panel.

  Further, since the power lead terminals are arranged in a so-called zigzag pattern, that is, in a zigzag array, a plurality of terminals can be arranged at high density.

Further, according to another configuration of the semiconductor power module, the power lead terminal is formed in a plate shape and is provided with slits or grooves for subdividing the current path. With this configuration, the current path of the power lead terminal is characterized by Can be subdivided, and there is an effect of reducing inductance parasitic on the terminal. Further, since the terminals are formed in a plate shape, the terminal strength is strong, and there is an effect that positioning when the module is mounted on the external substrate can be easily performed.

  Further, according to the semiconductor power module of another configuration, the metal base printed circuit board, the power semiconductor, the inner case integrally formed with the metal lead terminal for housing the driver IC, the power semiconductor filled in the inner case, Since the sealing resin for sealing the driver IC is provided and the control lead terminal and the inner case are integrated, there is an effect that the terminal arrangement position can be controlled with high accuracy.

  Hereinafter, embodiments of the present invention will be described using examples.

(First embodiment)
FIG. 1 is a plan view of a semiconductor power module 1 according to an embodiment of the present invention. As shown in FIG. 1, a circuit pattern made of a copper material is arranged on one main surface of a metal base printed board 2, and circuit components are mounted thereon. In the figure, only main components and circuit patterns are shown, and the circuit patterns are not shown in the middle of the portions where detailed explanation is unnecessary.

  The power semiconductor elements 4a, 4b, 5a, and 5b for power control use MOSFETs in this embodiment. The type of power semiconductor element is not limited to this, and may be a power transistor, IGBT (insulated gate bipolar transistor), or the like. These MOSFETs are fixed and electrically connected to predetermined positions of the circuit patterns 14 and 16 with solder or the like.

  Although omitted in the figure, a heat spreader (heat dissipating metal base) may be inserted between the MOSFETs 4a, 4b, 5a, 5b and the circuit patterns 14, 16 for the purpose of improving heat dissipation. The upper electrodes of the MOSFETs 4a and 4b are electrically connected to the circuit pattern 15 by a plurality of fine metal wires 18a and 18b, respectively, and the MOSFETs 5a and 5b are electrically connected to the circuit pattern 17 by a plurality of fine metal wires 18c and 18d, respectively. The

  Of the power lead terminal units 10 to 13, 10 is fixed to the circuit pattern 14 and becomes the drain terminal (D1) of the MOSFETs 4a and 4b, and 11 is fixed to the circuit pattern 15 and becomes the source terminal (S1) of the MOSFETs 4a and 4b. , 12 are fixed to the circuit pattern 16 and become the drain terminals (D2) of the MOSFETs 5a and 5b, and 13 is fixed to the circuit pattern 17 and become the source terminals (S2) of the MOSFETs 5a and 5b.

  A semiconductor element (driver IC) 3 controls the operation of the power semiconductors 4a, 4b, 5a, and 5b for power control. 6 to 9 are control lead terminals, 6 is a ground terminal (GND) of the driver IC 3, 7 is a control input terminal (LIN) of the low-side power semiconductor Q2, and 8 is a control input terminal of the high-side power semiconductor Q1. (HIN) and 9 are power supply terminals (VCC) of the driver IC 3. Each control lead terminal is electrically connected to a predetermined electrode terminal of the driver IC 3 by a circuit pattern (not shown).

  Next, FIG. 2 is a cross-sectional transmission diagram along the alternate long and short dash line A-A ′ in FIG. 1. In the figure, the same parts corresponding to those in FIG. As shown in FIG. 2, the circuit patterns 14 to 17 on the metal base printed board 2 are electrically insulated by an insulating layer 19. Circuit components and external terminals on the metal base printed board 2 are sealed with a sealing resin 20.

  FIG. 3 is a schematic circuit diagram showing the main part of the semiconductor power module shown in FIG. In the figure, the same parts corresponding to those in FIG. Q1 shows an equivalent circuit of a plurality of MOSFETs 4a and 4b connected in parallel. The drain terminal of Q1 is 10 (D1) and the source terminal is 11 (S1). Q2 shows an equivalent circuit of a plurality of MOSFETs 5a and 5b connected in parallel. The drain terminal of Q2 is 12 (D2), and the source terminal is 13 (S2). Ho21 and Lo22 are control output terminals for outputting signals based on the input control signals input from the HIN terminal 8 and LIN terminal 7 of the driver IC 3, respectively. In the module, Ho21 is the gate electrode of Q1, and Lo22 is Q2. Are respectively electrically connected to the gate electrodes. The source terminal 11 of Q1 and the drain terminal 12 of Q2 are connected on an external substrate outside the module, and Q1 and Q2 constitute a half bridge circuit. In this embodiment, the main power supply terminals are 10 (D1) and 13 (S2), and the main output terminals are 11 (S1) and 12 (D2).

  Next, the operation of the semiconductor power module in one embodiment of the present invention will be described with reference to FIGS. The driver IC 3 receives a signal from the outside, and outputs a drive signal to the gate electrodes of the corresponding power semiconductors Q1 and Q2, and the power semiconductors Q1 and Q2 receive a main power from the power lead terminal 10 by the input of the drive signal. The current is turned ON and OFF, and an AC output with an arbitrary frequency is supplied from the power lead terminals 11 and 12 to the load. That is, the driver IC 3 outputs an ON signal to the corresponding gate electrode Ho21 of the power semiconductor Q1 and an OFF signal to the gate electrode Lo22 of Q2 by the input of the external control signal, and the power semiconductor Q1 is turned ON by the input of these drive signals. When the semiconductor Q2 is turned OFF, the main current i1 input from the power lead terminal 10 is output to the load via the power lead terminal 11. Next, the driver IC 3 outputs an OFF signal to the corresponding gate electrode Ho21 of the power semiconductor Q1 and an ON signal to the gate electrode Lo22 of Q2 by the input of the external control signal, and the power semiconductor Q1 is turned OFF by the input of these drive signals. When the power semiconductor Q2 is turned on, the main current i2 from the load is output to the power lead terminal 13 via the power lead terminal 12.

  As is clear from the above, the path of the main current i1 in FIG. 1 enters the circuit pattern 14 from the power lead terminal 10 and flows to the circuit pattern 15 through the power semiconductor elements 4a and 4b and the fine metal wires 18a and 18b. Output from the lead terminal 11. As shown in FIG. 4, the current path includes an inductance L1 parasitic on the power lead terminal 10, an inductance L2 parasitic on the circuit pattern 14, the metal thin wires 18a and 18b, an inductance L3 parasitic on the circuit pattern 15, and a power lead terminal. 11 includes a parasitic inductance L4. 1, the path of the main current i2 enters the circuit pattern 16 from the power lead terminal 12 and flows to the circuit pattern 17 through the power semiconductor elements 5a and 5b and the fine metal wires 18c and 18d, and is output from the power lead terminal 13. Is done. As shown in FIG. 4, the current path includes an inductance L5 parasitic to the power lead terminal 12, an inductance L6 parasitic to the circuit pattern 16, the metal thin wires 18c and 18d and the inductance L7 parasitic to the circuit pattern 17, and the power lead terminal. 13 includes a parasitic inductance L8.

  Since the main currents i1 and i2 are driven by a high current of several tens of A or more and a high frequency of 10 kHz or more, the time change rate of the current may reach several kA / μs during switching. When such a current flows, a surge voltage having a magnitude of (L1 + L2 + L3 + L4) di1 / dt and (L5 + L6 + L7 + L8) di2 / dt is generated by the parasitic inductances (L1 to L8) included in the current path. Damage, increase in loss, or malfunction due to noise.

  In order to reduce these parasitic inductances, in FIG. 1, circuit patterns 14 to 17 are arranged in proximity to control lead terminals 10 to 13 that are electrically connected to each other, and power semiconductors 4a and 4b are fixed. The insulation distance between the circuit pattern 14 and the circuit pattern 15 is 1 mm, and the insulation distance between the circuit pattern 16 and the circuit pattern 17 to which the power semiconductors 5a and 5b are fixed is 1 mm. Is done.

  Further, the power semiconductors 4a and 4b are installed on the circuit pattern 14 at positions where the wiring lengths of the fine metal wires 18a and 18b for electrically connecting the upper electrodes and the circuit pattern 15 are 6 to 10 mm. 5a and 5b are placed on the circuit pattern 16 at positions where the wiring lengths of the fine metal wires 18c and 18d for electrically connecting the upper electrodes and the circuit pattern 17 are 6 to 10 mm. The number of fine metal wires 18a to 18d is wired more than the number calculated from the rated current of each power semiconductor. For example, if the rated current of the power semiconductor is 50 A and the fusing current per thin metal wire is 25 A, three wires are sufficient, but by hitting 5 to 10 wires, the parasitic inductance in the metal wire is reduced. In addition, the circuit patterns 14 to 17 in FIG. 1 have a thickness of other circuit pattern portions of 0.05 to 0.1 mm, whereas a thick copper material is used in advance or a solder material or the like is used. The parasitic inductance of the circuit patterns 14 to 17 can be further reduced by fixing to 0.15 to 0.5 mm. Although not shown here, the parasitic inductance can be further reduced by inserting slits or grooves for subdividing the current path in the circuit patterns 14a, 15a, 16a, and 17a. With the above configuration, the parasitic inductances L2, L3, L6, and L7 in the circuit shown in FIG. 4 can be reduced.

Next, a terminal structure for reducing the inductances L1, L4, L5, and L8 parasitic on the power lead terminals 10, 11, 12, and 13 will be described with reference to FIG. FIG. 5 is a structural diagram showing a first structure of the power lead terminal. A lead terminal support portion 24 is provided between a plurality of metal lead terminals to form a lead terminal unit 23. In the lead terminal unit 23, the pitch P1 between the internal terminals on the 23a side connected to the metal base printed circuit board side of the module is 1.27 mm, and seven terminals are connected in parallel at the same potential. On the other hand the external terminal pitch P2 of 23b side to be connected to the main printed circuit board side is 2.54 mm, 4 pieces of terminals are connected in parallel to the same potential. The terminal width of the lead terminal unit 23 is 0.8 mm for both 23a and 23b, and the terminal thickness T2 is 0.5 to 0.8 mm. It is also possible to make the terminal thickness on the 23a side 0.8 to 1.5 mm thicker than the 23b side. The lead terminal support 24 is installed at a position flush with the main printed circuit board so that the length on the 23a side is maximized.

  With the above terminal structure, it is possible to connect a plurality of terminals in parallel than usual, and it is possible to reduce inductance parasitic on the lead terminals. Further, since the lead terminal support 24 is provided between the plurality of lead terminals, the connection strength between the plurality of terminals can be increased. In addition, since the pitch between the terminals connected to the main printed circuit board is the same, the external board layout can be facilitated.

  With the above terminal structure, it is possible to connect a plurality of terminals in parallel, and it is possible to reduce inductance parasitic on the lead terminals.

  The self-inductance L parasitic on the circuit pattern and the terminal can be obtained by the following calculation formula as a thin plate (width w, thickness t, length l) in the cross-sectional direction in design.

L = 0.2 × l × (Ln (2 × l / (w + t)) + 0.5
+ 0.224 × (w + t) / l) (nH) (Formula 1)
In addition, the self-inductance L ′ parasitic on the thin metal wire (length l, diameter φ) can be calculated by the following equation in design.

L ′ = 0.2 × l × (Ln (4 × l / φ) −0.75) (nH) (Formula 2)
The effect of inductance reduction by the above configuration needs to be verified by experiment. In the case of using an aluminum wire having a length of 12 mm and a diameter of 350 μm in the thin metal wire, the parasitic inductance is 2.6 nH in the parallel connection of 6 wires, whereas it is reduced to 1.4 nH by making the parallel connection of 10 wires. I was able to. Further, in the conventional configuration, a parasitic inductance of several tens of nH or more exists, but the total value of the parasitic inductance between the power lead terminals 10 to 11 can be reduced to 4.0 nH by the configurations of FIGS.

  With the above configuration, the paths of the main currents 1 and 2 are configured with the shortest distance, and the current paths are subdivided, so that the parasitic inductances L1 to L8 can be reduced. In addition, parasitic resistance can be reduced. As a result, the surge voltage and radiation noise during switching are reduced, which has the effect of preventing malfunction of the circuit of the device and destruction of the circuit element, and a motor drive device that requires high frequency and high current drive. It is suitable as a driving device for a plasma display panel.

(Second Embodiment)
The semiconductor power module according to the second embodiment of the present invention is obtained by changing the power lead terminal structure in the semiconductor power module according to the first embodiment.

  FIG. 6A is a view showing a second structure of the power lead terminal of the semiconductor power module in one embodiment of the present invention. In FIG. 6A, reference numeral 25 denotes a power lead terminal unit. In the example shown in the figure, seven terminals 25a to 25g are connected in parallel to the same potential, and 10, 11, 12, 13 shown in FIG. This corresponds to the terminal. On the other hand, reference numeral 26 in FIG. 6B is an example of a control lead terminal, one of which is a different potential, which corresponds to the terminals 6, 7, 8, and 9 shown in FIG. For example, the terminal pitch P2 of the control lead terminals 26 is constant at 2.54 mm, whereas the terminal pitch P1 of the power lead terminal unit 25 is narrowed to 1.27 mm. The terminal width of both the control lead terminal 26 and the power lead terminal 25 is 0.8 mm. Further, the terminal thickness T2 of the control lead terminal 26 is 0.5 to 0.8 mm, whereas the terminal thickness T1 of the power lead terminal 25 is 0.8 to 1.5 mm.

  With the above configuration, the inductances L1, L4, L5, and L8 parasitic on the power lead terminal portion through which the main power supply current flows can be reduced.

(Third embodiment)
The semiconductor power module according to the third embodiment of the present invention is obtained by changing the power lead terminal structure in the semiconductor power module according to the first embodiment. FIG. 7A is a plan view showing a third structure of the power lead terminals, and the power lead terminal units 27 are staggered, that is, zigzag arranged as compared with the second embodiment of FIG. It has become. FIG.7 (b) is a side view along the dashed-dotted line BB 'in Fig.7 (a). The vertical distance d between the terminals is 5 mm, and the horizontal terminal pitch, terminal thickness, and terminal width are the same as those of the power lead terminal unit 25 in FIG. With the above terminal structure, it is possible to connect in parallel approximately twice as many terminals as the power lead terminal unit 25 shown in FIG. 6A, and it is possible to further reduce the parasitic inductance of the power lead terminal.

  In the first to third embodiments, the structure of the power lead terminal unit is not shown in FIGS. 5, 6, and 7, but other than the plurality of internal terminals constituting the power lead terminal unit, If a terminal having a longer lead length is disposed, positioning when the module is mounted on the external substrate is facilitated.

(Fourth embodiment)
The semiconductor power module according to the fourth embodiment of the present invention is obtained by changing the power lead terminal structure in the semiconductor power module according to the first embodiment. FIG. 8 is a structural view showing a fourth structure of the power lead terminal, and a plurality of leads shown in FIGS. 5, 6, and 7 showing the structure of the power lead terminal unit in the first to third embodiments. The structure is different from that of a power lead terminal unit configured by connecting terminals in parallel, and is formed in a wide plate shape. By providing a plurality of slits or grooves in the direction of subdividing the current path in the plate-shaped power lead terminal 28, the current path of the power lead terminal can be subdivided, and the parasitic inductance of the terminal is reduced. . Moreover, since the terminal is formed in a plate shape, the terminal strength is strong, and positioning when mounting the module on the external substrate can be facilitated.

(Fifth embodiment)
FIG. 9A is a plan view showing the structure of the semiconductor power module 30 in the fifth embodiment of the present invention, and FIG. 9B is a cross-sectional transmission diagram along the alternate long and short dash line CC ′. In the figure, the same parts corresponding to those in FIG. 9A and 9B, the circuit pattern and the semiconductor element arrangement arranged on the metal base printed board 2 are the same as those in the first embodiment. In the first embodiment, the circuit components and the external terminals on the metal base printed circuit board 2 are sealed with the sealing resin 20, but in the fifth embodiment, the circuit parts are mounted on the metal base printed circuit board 2 on which the circuit components are mounted. In this configuration, an insert case 31 that forms a sealing space is attached to the metal base printed board 2.

  As shown in FIGS. 9A and 9B, the insert case 31 is formed of, for example, a rectangular frame having a peripheral wall 32 from an insulating resin. In the peripheral wall 32, at least the control lead terminals 6 to 9 and the power lead terminals 10 to 13 are integrally formed. The structure of the power lead terminals 10 to 13 in FIG. 9 is the same as that of the first embodiment shown in FIG. 5, but which of the power lead terminals in the second to fourth embodiments is different from that of FIG. May be used. The lower surface of the insert case 31 is open and formed so that the metal base printed board 2 is fitted. Circuit components on the metal base printed board 2 are sealed with a sealing resin 20.

  With the above configuration, since the control lead terminal and the inner case are integrally molded, the arrangement position of the control lead terminal can be controlled with high accuracy. The other operations and effects are the same as those of the first embodiment, and the main current path is configured with the shortest distance and the current path is subdivided, so that parasitic inductance can be reduced. In addition, parasitic resistance can be reduced. As a result, the surge voltage and radiation noise during switching are reduced, which has the effect of preventing malfunction of the circuit of the device and destruction of the circuit element, and a motor drive device that requires high frequency and high current drive. It is suitable as a driving device for a plasma display panel.

  In each of the above-described embodiments, an example in which two parallel-connected MOSFETs 4a, 4b and 5a, 5b are used has been described. However, the same can be applied to a case where two or more MOSFETs are connected in parallel. It is obvious. In each of the above-described embodiments, the semiconductor power module in which the power semiconductors Q1 and Q2 are connected in series as shown in FIG. 3 to form a half-bridge circuit has been described. It is apparent that the present invention can be similarly applied to a semiconductor power module configured by using a single-phase full bridge and a three-phase half-bridge circuit incorporated in the same module.

  As described above, the present invention is useful as a motor driving device or a plasma display panel driving device that requires high frequency and large current driving.

The top view which shows the structure of the semiconductor power module which concerns on the 1st Embodiment of this invention. Sectional transparent drawing along the dashed-dotted line AA 'of the semiconductor power module which concerns on the 1st Embodiment of this invention 1 is a schematic circuit diagram showing main parts of a semiconductor power module according to a first embodiment of the present invention. Schematic circuit diagram showing the configuration of parasitic inductance of the semiconductor power module according to the first embodiment of the present invention The figure which shows the structure of the semiconductor power module which concerns on the 1st Embodiment of this invention It is a figure which shows the structure of the metal lead terminal of the semiconductor power module which concerns on the 2nd Embodiment of this invention, (a) is a figure which shows the structure of the lead terminal for power, (b) is the structure of the lead terminal for control. Illustration It is a figure which shows the structure of the lead terminal for power of the semiconductor power module which concerns on the 3rd Embodiment of this invention, (a) is a top view, (b) is a side view along dashed-dotted line B-B '. The figure which shows the structure of the lead terminal for power of the semiconductor power module which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the semiconductor power module which concerns on the 5th Embodiment of this invention, (a) is a top view, (b) is a cross-sectional transparent drawing along dashed-dotted line C-C '. Plan view showing a conventional semiconductor power module Sectional view showing a conventional semiconductor power module Sectional view of the periphery of the power lead terminal and circuit board showing another conventional semiconductor power module

Explanation of symbols

1 Semiconductor Power Module 2 Metal Base Printed Circuit Board 3 Driver IC
4a, 4b Power semiconductor 5a, 5b Power semiconductor 6 Control lead terminal (driver IC grounding terminal (GND))
7 Control lead terminal (Low-side control input terminal (LIN))
8 Control lead terminal (High-side control input terminal (HIN))
9 Control lead terminal (Driver IC power supply terminal (VCC))
10 Lead terminal for power (drain terminal (D1))
11 Lead terminal for power (source terminal (S1))
12 Lead terminal for power (drain terminal (D2))
13 Lead terminal for power (source terminal (S2))
14, 15, 16, 17 Circuit pattern (copper material)
18a, 18b, 18c, 18d Metal fine wire 19 Insulating layer 20 Sealing resin 21 Control signal terminal 22 Control signal terminal 23, 25, 26, 27, 28 Lead terminal unit for power 24 Lead terminal support 30 Semiconductor power module 31 Insert case 32 Peripheral wall 101 Insulated metal substrate 102 Metal plate 103 Insulating layer 104 Copper foil pattern (circuit pattern)
105 Power Lead Terminal 106 Control Lead Terminal 107 Storage Case 120 Power Semiconductor Element 121 Control Semiconductor Element 122, 123, 124 Connection Line

Claims (10)

A metal base printed circuit board having a conductive circuit pattern formed on an electrically insulating layer disposed on one main surface of the metal board;
At least one power semiconductor fixed on the circuit pattern;
A driver IC for driving the power semiconductor;
A semiconductor power module for electrically connecting the upper electrode of the power semiconductor element and the circuit pattern by a thin metal wire,
At least one of the same-potential metal lead terminal group for electrically connecting the semiconductor power module and the outside includes an internal lead terminal connected to the metal base printed circuit board side through a lead terminal support portion, It has a structure having external lead terminals connected to the outside,
The inter-terminal pitch of the internal lead terminals is smaller than the inter-terminal pitch of the external lead terminals, the number of terminals of the internal lead terminals is greater than the number of terminals of the external lead terminals,
A semiconductor power module characterized in that a pitch between terminals of a portion connected to the outside in the metal lead terminal group is the same . A circuit pattern in which a power lead terminal for electrically connecting the power semiconductor and the outside is installed,
In the circuit pattern to which the power semiconductor is fixed, the circuit pattern connected to the upper electrode of the power semiconductor through a metal wiring, and the circuit pattern in which the power lead terminal is installed, a current path is provided to each circuit pattern. 2. The semiconductor power module according to claim 1, wherein slits or grooves to be subdivided are formed. The metal lead terminal group having the same potential is composed of at least three metal lead terminals connected to the metal base substrate side and at least two metal lead terminals connected to the outside.
3. The semiconductor power module according to claim 1, further comprising one or more lead terminal support portions for changing a lead terminal pitch at a central portion of the metal terminal. 4. The semiconductor power module according to claim 1, wherein the metal lead terminal group is attached to a plurality of locations on the metal base printed board. A metal base printed circuit board having a conductive circuit pattern formed on an electrically insulating layer disposed on one main surface of the metal board;
At least one power semiconductor fixed on the circuit pattern;
A driver IC for driving the power semiconductor;
A semiconductor power module for electrically connecting the upper electrode of the power semiconductor element and the circuit pattern by a thin metal wire,
A plurality of power lead terminals for connecting the main electrode of the power semiconductor to the outside are narrower in pitch than the control lead terminals for connecting the electrodes of the driver IC to the outside, and subdivide the current path. semiconductors power module metal lead terminal of the same potential is it characterized by comprising a parallel connection of. 6. The power lead terminals are arranged in two or more stages with the lead terminals spaced apart from each other, and arranged in a staggered pattern when viewed from the direction in which the lead terminals extend. The semiconductor power module as described. 6. The semiconductor power module according to claim 5, wherein the power lead terminal is formed in a plate shape and is provided with slits or grooves for subdividing the current path. 6. The semiconductor power module according to claim 5, wherein at least one of the internal lead terminals in the power lead terminal has a longer lead length than the other lead terminals. An inner case integrally formed with the metal lead terminal to house the metal base printed circuit board, the power semiconductor, and the driver IC;
9. The semiconductor power module according to claim 1, further comprising a sealing resin that fills the inner case and seals the power semiconductor and the driver IC. The semiconductor power module according to claim 1, further comprising an output terminal that forms a half-bridge circuit with the plurality of power semiconductors and further outputs a large current pulse.

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