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JP4200450B2 - Manufacturing method of chip-type fuse - Google Patents
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JP4200450B2 - Manufacturing method of chip-type fuse - Google Patents

Manufacturing method of chip-type fuse Download PDF

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JP4200450B2
JP4200450B2 JP2005062104A JP2005062104A JP4200450B2 JP 4200450 B2 JP4200450 B2 JP 4200450B2 JP 2005062104 A JP2005062104 A JP 2005062104A JP 2005062104 A JP2005062104 A JP 2005062104A JP 4200450 B2 JP4200450 B2 JP 4200450B2
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substrate
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fuse
chip
holes
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章 上月
小百合 前林
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Matsuo Electric Co Ltd
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本発明は、例えばプリント基板上に装着されるチップ型ヒューズの製造方法に関し、特に、その電極の形成に関するものである。   The present invention relates to a method of manufacturing a chip-type fuse that is mounted on, for example, a printed circuit board, and more particularly to formation of an electrode thereof.

ヒューズ線を使用したチップ型ヒューズとしては、例えば特許文献1、2に開示されているようなものがある。   As a chip-type fuse using a fuse wire, for example, there are those disclosed in Patent Documents 1 and 2.

特許文献1のチップ型ヒューズは、絶縁体製のほぼ直方体状のベースを有している。このベースの上面の中央には、上面側で開口した凹部が形成されている。ベースの上面に、絶縁体製のほぼ直方体状の蓋の下面が接している。この蓋には、ベースの凹部に対応する位置に、蓋の下面で開口した凹部が形成されている。これら凹部によって中空部が形成されている。金属端子が、ベースの凹部の両側の上面から、ベースの両端まで伸び、そこからベースの端面に沿って下方に伸びている。中空部の両端を跨いで、ヒューズ線が配置され、その両端が端子部材にそれぞれはんだ付けされている。   The chip-type fuse of Patent Document 1 has a substantially rectangular parallelepiped base made of an insulator. In the center of the upper surface of the base, a recess opened on the upper surface side is formed. The lower surface of a substantially rectangular parallelepiped lid made of an insulator is in contact with the upper surface of the base. The lid is formed with a recess opened at the lower surface of the lid at a position corresponding to the recess of the base. A hollow portion is formed by these concave portions. A metal terminal extends from the upper surface on both sides of the recess of the base to both ends of the base and extends downward along the end surface of the base. A fuse wire is disposed across both ends of the hollow portion, and both ends thereof are soldered to the terminal member.

特許文献2のチップ型ヒューズでは、絶縁体の直方体状のベースの上面中央に内部空間形成用の凹部が形成されている。その両側に金属端子収容用の凹部がそれぞれ形成されている。金属端子収容用の凹部には、金属端子の内方端部が配置され、この金属端子は、内方端部から外方に伸び、ベースの端面で下方に折り曲げられ、さらにベースの底面に沿ってベースの内側に折り曲げられている。金属端子の内方端部間に、内部空間形成用の凹部を跨いでヒューズ線が配置され、その両端が、金属端子の内方端部にはんだ付けされている。ベースの上面は蓋によって被われるが、その蓋の下面にも、ベースの内部空間形成用の凹部に対応するように内部空間形成用の凹部が形成されている。   In the chip-type fuse of Patent Document 2, a recess for forming an internal space is formed at the center of the upper surface of a rectangular parallelepiped base of an insulator. Recesses for receiving metal terminals are respectively formed on both sides thereof. An inner end portion of the metal terminal is disposed in the recess for housing the metal terminal. The metal terminal extends outward from the inner end portion, is bent downward at the end surface of the base, and is further along the bottom surface of the base. And bent inside the base. Between the inner end portions of the metal terminals, a fuse wire is disposed across the recess for forming the internal space, and both ends thereof are soldered to the inner end portions of the metal terminals. The upper surface of the base is covered with a lid, and a concave portion for forming an internal space is formed on the lower surface of the lid so as to correspond to the concave portion for forming the internal space of the base.

米国特許明細書第4608548号U.S. Pat. No. 4,608,548 実開昭59−119545号公報Japanese Utility Model Publication No.59-119545

特許文献1、2に示したチップ型ヒューズでは、ベース、蓋、金属端子、ヒューズ線を個別に形成した上で、ベース上にヒューズ線、金属端子を配置し、ヒューズ線と金属端子とをはんだ付けしなければならず、その生産に手間がかかり、量産には不向きであった。   In the chip type fuses shown in Patent Documents 1 and 2, the base, lid, metal terminal, and fuse wire are individually formed, the fuse wire and the metal terminal are arranged on the base, and the fuse wire and the metal terminal are soldered. It had to be attached, and it took time to produce it, and it was not suitable for mass production.

本発明は、量産が可能なチップ型ヒューズの製造方法を提供することを目的とする。   An object of this invention is to provide the manufacturing method of the chip-type fuse which can be mass-produced.

本発明によるチップ型ヒューズの製造方法では、まずヒューズ半製品を製造する。このヒューズ半製品では、少なくとも1つの列状体を有している。列状体では、絶縁基板の上下面間を貫通する複数の貫通孔が所定の間隔をおいて一列に形成されている。列状体では、さらに、隣接する前記貫通孔間の前記絶縁基板内それぞれに中空部が形成されている。この列状体において、前記各貫通孔及び前記各中空部を直線状に通ってヒューズ線が挿通されている。ヒューズ線は、中空部内において何者とも非接触となるように配置することが望ましい。前記各貫通孔の上下面周囲、前記各貫通孔内及び前記各貫通孔内に突出している前記ヒューズ線が一体にめっきされる。前記各貫通孔を通る切断線に沿って前記基板が切断される。   In the chip-type fuse manufacturing method according to the present invention, first, a semi-finished product of a fuse is manufactured. This fuse semi-finished product has at least one column. In the columnar body, a plurality of through holes penetrating between the upper and lower surfaces of the insulating substrate are formed in a row at a predetermined interval. In the row body, a hollow portion is further formed in each of the insulating substrates between the adjacent through holes. In this array, fuse wires are inserted through the through holes and the hollow portions in a straight line. It is desirable to arrange the fuse wire so that no one is in contact with the hollow portion. The fuse wires protruding around the upper and lower surfaces of each through hole, in each through hole and in each through hole are plated together. The substrate is cut along a cutting line passing through each through hole.

この製造方法によれば、各貫通孔の上下面周囲、前記各貫通孔内及び前記各貫通孔内に突出している前記ヒューズ線が一体にめっきされるので、このめっきという1工程によって、後に基板を切断することによってチップ型ヒューズの端子となる部分が形成されると共に、この端子となる部分にヒューズ線が電気的に接続される。従って、特許文献1、2のように、金属端子を予め形成した上で、これをベースに配置し、ヒューズ線と半田付けするというような複数の工程が不要となり、チップ型ヒューズの量産に適している。   According to this manufacturing method, since the fuse wire protruding around the upper and lower surfaces of each through hole, in each of the through holes and in each of the through holes is integrally plated, the substrate is later formed by one step of this plating. Is cut to form a portion serving as a terminal of the chip-type fuse, and a fuse wire is electrically connected to the portion serving as the terminal. Therefore, as in Patent Documents 1 and 2, it is not necessary to perform a plurality of processes such as forming a metal terminal in advance, placing it on the base, and soldering it to the fuse wire, which is suitable for mass production of chip-type fuses. ing.

前記基板には、複数の前記列状体を互いに平行に設けることができる。この場合、前記切断は、前記各列状体の対応する貫通孔を通る切断線と、前記各列状体間を通る切断線とに沿って、行われる。このように複数の列状体を設けることによって更にチップ型ヒューズを量産することができる。   The substrate may be provided with a plurality of the columnar bodies in parallel with each other. In this case, the cutting is performed along a cutting line that passes through the corresponding through hole of each columnar body and a cutting line that passes between the columnar bodies. By providing a plurality of columnar bodies in this way, chip-type fuses can be further mass-produced.

或いは、前記基板を、上部基板及び下部基板とに分割形成することができる。この場合、前記上部及び下部基板には、複数の上部貫通孔と複数の下部貫通孔とが形成されている。これら上部基板と下部基板とは接着されているが、この接着は、上部貫通孔と下部貫通孔とのうち互いに対応するものが、一致するように行われる。少なくとも前記下部基板の前記下部貫通孔間に前記中空部形成用の凹部が形成されている。前記下部基板の中空部形成用の凹部と対応する上部基板の位置にも、中空部形成用の凹部を設けることもできる。前記接着の前に前記ヒューズ線が前記列状体中の前記下部基板の下部貫通孔及び下部基板の前記中空部形成用凹部に位置するように配置される。   Alternatively, the substrate can be divided into an upper substrate and a lower substrate. In this case, a plurality of upper through holes and a plurality of lower through holes are formed in the upper and lower substrates. The upper substrate and the lower substrate are bonded to each other, and this bonding is performed so that the corresponding ones of the upper through hole and the lower through hole match each other. A recess for forming the hollow portion is formed at least between the lower through holes of the lower substrate. A recess for forming a hollow portion can also be provided at the position of the upper substrate corresponding to the recess for forming the hollow portion of the lower substrate. Before the bonding, the fuse wire is disposed so as to be positioned in the lower through hole of the lower substrate in the columnar body and the hollow forming recess of the lower substrate.

このように構成すると、1つの列状体の下部基板上に1本のヒューズ線を配置するだけでよく、製造が容易になる。   With this configuration, it is only necessary to arrange one fuse line on the lower substrate of one columnar body, which facilitates manufacture.

以上のように、本発明によれば、チップ型ヒューズを容易に量産することができる。   As described above, according to the present invention, chip-type fuses can be easily mass-produced.

本発明の1実施形態のチップ型ヒューズの製造方法によって製造されたチップ型ヒューズを図1(a)乃至(c)に示す。このチップ型ヒューズ1は、絶縁体製、例えばガラスエポキシ基板製の本体2を有している。この本体2は、例えば概略直方体状に形成され、その内部に中空部4を有している。この中空部4内に、中空部4の内周面と非接触にヒューズ線6が配置されている。ヒューズ線6の両端は、本体2の両端から外方に突出している。その突出端は、本体2の下面及び上面にめっきで形成された端子8a、8bと電気的に接続されている。   1A to 1C show a chip-type fuse manufactured by a chip-type fuse manufacturing method according to an embodiment of the present invention. The chip-type fuse 1 has a main body 2 made of an insulator, for example, a glass epoxy substrate. The main body 2 is formed in a substantially rectangular parallelepiped shape, for example, and has a hollow portion 4 therein. A fuse wire 6 is disposed in the hollow portion 4 in a non-contact manner with the inner peripheral surface of the hollow portion 4. Both ends of the fuse wire 6 protrude outward from both ends of the main body 2. The protruding ends are electrically connected to terminals 8a and 8b formed on the lower surface and upper surface of the main body 2 by plating.

詳細には、本体2は、下部本体2aと、上部本体2bとからなり、両者はそれぞれ同じ、長さ、幅及び高さを持っている。下部本体2aの上面の中央には、下部本体2aの長さ方向に沿って下部凹所4aの概略矩形状の開口が形成されている。この開口から下部凹所4aは、下部本体2aの下面側にほぼ垂直に窪んでいる。同様に上部本体2bの下面中央にも、上部本体2bの長さ方向に沿って上部凹所4bの概略矩形状の開口が形成され、この開口から上部凹所4bは、上部本体2bの上部側にほぼ垂直に窪んでいる。これら上部本体2a、2bが重ね合わせた状態で、下部凹所4aと上部凹所4bとが一致し、これらが中空部4を形成している。なお、下部本体2aと上部本体2bとの両端部の中央には、それぞれ円弧状の切欠10a、10bが互いに一致するように形成されている。   Specifically, the main body 2 includes a lower main body 2a and an upper main body 2b, and both have the same length, width, and height. A substantially rectangular opening of the lower recess 4a is formed in the center of the upper surface of the lower main body 2a along the length direction of the lower main body 2a. From this opening, the lower recess 4a is recessed substantially perpendicularly to the lower surface side of the lower body 2a. Similarly, a substantially rectangular opening of the upper recess 4b is formed in the center of the lower surface of the upper body 2b along the length direction of the upper body 2b, and the upper recess 4b extends from the opening to the upper side of the upper body 2b. It is recessed almost vertically. In a state in which the upper main bodies 2a and 2b are overlapped, the lower recess 4a and the upper recess 4b coincide with each other to form a hollow portion 4. In addition, arc-shaped notches 10a and 10b are formed at the centers of both ends of the lower main body 2a and the upper main body 2b so as to coincide with each other.

ヒューズ線6は、直線状で、下部本体2aと上部本体2bとの接合面に、中空部4のいずれの部分とも非接触の状態で配置され、その両端部が切欠10a、10b内に突出している。   The fuse wire 6 is linear, and is disposed on the joint surface between the lower main body 2a and the upper main body 2b in a non-contact state with any portion of the hollow portion 4, and both end portions thereof protrude into the notches 10a and 10b. Yes.

下部端子8a、上部端子8bは、下部切欠10a、10bを包囲するようにめっきによって形成されている。このめっきは、図1(b)に示すように下部切欠10a、上部切欠10bの内周面にもおよび、さらに下部切欠10a、上部切欠10bの接合部から突出しているヒューズ線6の全周にも及んでいる。この切欠内周面面のめっき層を符号12a、12bで示し、ヒューズ線6の突出端のめっき層を符号14で示す。   The lower terminal 8a and the upper terminal 8b are formed by plating so as to surround the lower notches 10a and 10b. As shown in FIG. 1B, the plating extends to the inner peripheral surfaces of the lower notch 10a and the upper notch 10b, and further to the entire circumference of the fuse wire 6 protruding from the joint portion of the lower notch 10a and the upper notch 10b. It also extends. The plating layer on the inner peripheral surface of the notch is indicated by reference numerals 12a and 12b, and the plating layer at the protruding end of the fuse wire 6 is indicated by reference numeral 14.

この下部端子8a、上部端子8b、めっき層12a、12b、14は、同図(c)に拡大して示すように、いずれもが複数のめっき層からなる。下部端子8a、8bは、無電解銅めっき層16a、16bとその外面に形成された電解銅めっき層18a、18bと、その外面側に形成された電解ニッケルめっき層20a、20bと、その外面側に形成された電解錫めっき層22a、22bとからなる。   Each of the lower terminal 8a, the upper terminal 8b, and the plating layers 12a, 12b, and 14 includes a plurality of plating layers as shown in an enlarged view in FIG. The lower terminals 8a and 8b are composed of electroless copper plating layers 16a and 16b, electrolytic copper plating layers 18a and 18b formed on the outer surfaces thereof, electrolytic nickel plating layers 20a and 20b formed on the outer surfaces thereof, and outer surfaces thereof. The electroplated tin plating layers 22a and 22b are formed.

めっき層12a、12bは、上部および下部切欠10a、10bの内周面に、無電解銅めっき層16a、16bと一体に形成された無電解銅めっき層24a、24bと、この無電解銅めっき層24a、24bの外面側に、電解銅めっき層18a、18bと一体に形成された電解銅めっき層26a、26bと、この電解銅めっき層26a、26bの外面側に、電解ニッケルめっき層20a、20bと一体に形成された電解ニッケルめっき層28a、28bと、この電解ニッケルめっき層28a、28bの外面側に電解錫めっき層22a、22bと一体に形成された電解錫めっき層30a、30bとからなる。   The plating layers 12a and 12b are formed by electroless copper plating layers 24a and 24b formed integrally with the electroless copper plating layers 16a and 16b on the inner peripheral surfaces of the upper and lower notches 10a and 10b, and the electroless copper plating layer. Electrolytic copper plating layers 26a and 26b formed integrally with the electrolytic copper plating layers 18a and 18b on the outer surface side of 24a and 24b, and electrolytic nickel plating layers 20a and 20b on the outer surface side of the electrolytic copper plating layers 26a and 26b. And electrolytic tin plating layers 30a and 30b integrally formed with the electrolytic tin plating layers 22a and 22b on the outer surface side of the electrolytic nickel plating layers 28a and 28b. .

めっき層14は、ヒューズ線6の突出端の全周囲に形成され、無電解銅めっき層24a、24bと一体に形成された無電解銅めっき層32と、この無電解銅めっき層32の外面側に、電解銅めっき層26a、26bと一体に形成された電解銅めっき層34と、この電解銅めっき層34の外面側に電解ニッケルめっき層28a、28bと一体に形成された電解ニッケルめっき層36と、この電解ニッケルめっき層36の外面側に電解錫めっき層30a、30bと一体に形成された電解錫めっき層38とからなる。   The plating layer 14 is formed all around the protruding end of the fuse wire 6, and is formed integrally with the electroless copper plating layers 24 a and 24 b, and the outer surface side of the electroless copper plating layer 32. Furthermore, the electrolytic copper plating layer 34 formed integrally with the electrolytic copper plating layers 26a, 26b, and the electrolytic nickel plating layer 36 formed integrally with the electrolytic nickel plating layers 28a, 28b on the outer surface side of the electrolytic copper plating layer 34. And an electrolytic tin plating layer 38 formed integrally with the electrolytic tin plating layers 30a and 30b on the outer surface side of the electrolytic nickel plating layer 36.

無電解銅めっき層16a、16b、24a、24b、32は同時に形成されている。同様に、電解銅めっき層18a、18b、26a、26b、34は同時形成されている。電解ニッケルめっき層20a、20b、28a、28b、36も、同時に形成され、電解錫めっき層22a、22b、30a、30b、38も同時に形成されている。なお、同図(c)では、各めっき層の厚さをかなり誇張して描いてある。   The electroless copper plating layers 16a, 16b, 24a, 24b, and 32 are formed simultaneously. Similarly, the electrolytic copper plating layers 18a, 18b, 26a, 26b, and 34 are formed simultaneously. Electrolytic nickel plating layers 20a, 20b, 28a, 28b, 36 are also formed at the same time, and electrolytic tin plating layers 22a, 22b, 30a, 30b, 38 are also formed at the same time. In addition, in the figure (c), the thickness of each plating layer is drawn exaggerated considerably.

このチップ型ヒューズは、例えば次のようにして製造される。まず、図4(c)に示すような半製品40を製造する。この半製品40は、基板42と長尺ヒューズ線44とからなる。   This chip-type fuse is manufactured as follows, for example. First, a semi-finished product 40 as shown in FIG. The semi-finished product 40 includes a substrate 42 and a long fuse wire 44.

基板42は、絶縁体、例えばガラスエポキシ樹脂製の下部基板42aと上部基板42bとからなる。図2(a)、(b)に示すように、下部基板42aは平面形状が概略長方形または正方形状のもので、その一辺に沿って予め定めた間隔ごとに下部貫通孔46aが一列に、それぞれの中心が同一直線上に位置するように形成されている。これら下部貫通孔46aは、いずれも下部基板42aの上下面を貫通する円形孔である。隣接する下部貫通孔46aの間に、中空部形成用の下部凹部48aが形成されている。下部凹部48aは、隣接する下部貫通孔46aとそれぞれ等距離に位置し、下部基板42aの上面において長孔状に開口し、所定の深さだけ下部基板42aの下面側に向かってほぼ垂直に窪んでいる。下部凹部48aは、その長手方向が上記一辺に沿うように、かつ、その長手方向の中心線が各下部貫通孔46aの中心を繋ぐ直線上に位置するように形成されている。このように下部貫通孔46aと下部凹部48aとが一列に形成されている。この列が、上記一辺と直交する他の一辺の方向に所定の間隔をおいて、複数列形成されている。   The substrate 42 is made of an insulator, for example, a lower substrate 42a and an upper substrate 42b made of glass epoxy resin. As shown in FIGS. 2A and 2B, the lower substrate 42a has a substantially rectangular or square planar shape, and the lower through holes 46a are arranged in a row at predetermined intervals along one side thereof. Are centered on the same straight line. These lower through holes 46a are circular holes that penetrate the upper and lower surfaces of the lower substrate 42a. A lower concave portion 48a for forming a hollow portion is formed between adjacent lower through holes 46a. The lower concave portion 48a is located at an equal distance from each of the adjacent lower through holes 46a, opens in a long hole shape on the upper surface of the lower substrate 42a, and is recessed substantially vertically toward the lower surface side of the lower substrate 42a by a predetermined depth. It is. The lower recess 48a is formed so that its longitudinal direction is along the one side, and its center line is located on a straight line connecting the centers of the respective lower through holes 46a. In this way, the lower through hole 46a and the lower recess 48a are formed in a line. A plurality of rows are formed at predetermined intervals in the direction of the other side perpendicular to the one side.

上部基板42bは、下部基板42aと同じ大きさ、同じ材質で、各下部貫通孔46aと対応する位置に、これと同じ大きさで上部貫通孔46bが形成され、下部凹部48aに対応する位置にこれと同じ大きさで上部凹部48bが形成されている。但し、上部凹部48bは、その下面側に開口し、上面側に窪んでいる(図4(b)参照)。   The upper substrate 42b has the same size and the same material as the lower substrate 42a, and the upper through hole 46b is formed in the same size as the lower through hole 46a. The upper substrate 42b is in the position corresponding to the lower recess 48a. An upper recess 48b is formed in the same size. However, the upper concave portion 48b is open on the lower surface side and is recessed on the upper surface side (see FIG. 4B).

図3(a)、(b)に示すように、下部基板42aの上面側には、各列における下部貫通孔46a、下部凹所48aの中心を繋ぐ直線状に、上面側に開口した溝50aが上記他方の辺から、これと対向する辺まで形成される。これら溝50aは、図3(c)に示すように所定間隔ごとに複数形成されている、上部基板42bにも、同様に各列における上部貫通孔46b、下部凹所48bの中心を繋ぐ直線状に、上面側に開口した溝50bが上記他方の辺から、これと対向する辺まで形成される。   As shown in FIGS. 3A and 3B, on the upper surface side of the lower substrate 42a, a groove 50a opened on the upper surface side in a straight line connecting the centers of the lower through holes 46a and the lower recesses 48a in each row. Is formed from the other side to the side opposite to the other side. A plurality of these grooves 50a are formed at predetermined intervals as shown in FIG. 3C. Similarly, the upper substrate 42b is linearly connected to the centers of the upper through holes 46b and the lower recesses 48b in each row. In addition, the groove 50b opened on the upper surface side is formed from the other side to the side opposite thereto.

次に、図4(a)に示すように下部基板42aの各溝50a上に長尺のヒューズ線44を上記他方の辺から、これに対向する辺まで配置する。次に、同図(b)に示すように、上部基板42bの下面における上部貫通孔46b、上部凹所48a以外の部分に接着剤52を塗布し、各下部貫通孔46a、上部貫通孔46bの対応するものが一致し、かつ各下部凹所48aと各上部凹所48bとの対応するものが一致するように、同図(c)に示すように貼り合わせる。   Next, as shown in FIG. 4A, a long fuse wire 44 is disposed on each groove 50a of the lower substrate 42a from the other side to the side opposite thereto. Next, as shown in FIG. 4B, an adhesive 52 is applied to portions other than the upper through hole 46b and the upper recess 48a on the lower surface of the upper substrate 42b, and the lower through holes 46a and the upper through holes 46b are formed. Bonding is performed as shown in FIG. 5C so that the corresponding ones match and the corresponding ones of the lower recesses 48a and the upper recesses 48b match.

これによって、対応する下部貫通孔46aと上部貫通孔46bとのよって縦横に配列された貫通孔46が形成され、対応する下部凹所48aと上部凹所48bとによって縦横に配列された複数の中空部48が形成され、同一列にある貫通孔46と中空部48の内部に長尺のヒューズ線44とが挿通されている。この挿通位置は、下部基板42aと上部基板42との接合面上にある。この状態では、長尺のヒューズ線44は、各中空部48内において中空部48とは全く接触していない。また、長尺のヒューズ線44のうち中空部48から伸びた部分は、各貫通孔46における下部貫通孔46aと上部貫通孔46bとの接合部を通過して、隣接する中空部48内に侵入している。この同一列の貫通孔46と中空部48と長尺のヒューズ線44とによって一列の列状体が形成されている。この列状体が、他方の辺に沿って所定間隔をおいて複数形成されている。このようにして半製品40が製造される。   As a result, through holes 46 arranged vertically and horizontally are formed by corresponding lower through holes 46a and upper through holes 46b, and a plurality of hollows arranged vertically and horizontally by corresponding lower recesses 48a and upper recesses 48b. A portion 48 is formed, and a long fuse wire 44 is inserted into the through hole 46 and the hollow portion 48 in the same row. This insertion position is on the joint surface between the lower substrate 42 a and the upper substrate 42. In this state, the long fuse wire 44 is not in contact with the hollow portion 48 in each hollow portion 48. Further, a portion of the long fuse wire 44 extending from the hollow portion 48 passes through a joint portion between the lower through hole 46 a and the upper through hole 46 b in each through hole 46 and enters the adjacent hollow portion 48. is doing. The through-holes 46, the hollow portions 48, and the long fuse wires 44 in the same row form a row-like body. A plurality of the row-like bodies are formed at a predetermined interval along the other side. In this way, the semi-finished product 40 is manufactured.

次に、同図(e)に示すように、下部基板42aの下面における各下部貫通孔46aの周囲、上部基板42aの上面における各上部貫通孔46bの周囲、各下部貫通孔46aの内周面、各上部貫通孔46bの内周面および長尺のヒューズ線46のうち各貫通孔46内にある部分に、一体にめっき層54が形成されている。このめっき層54は、上述したように無電解銅めっき層、電解銅めっき層、電解ニッケルめっき層、電解錫めっき層を、下部基板42a、上部基板42bから外方に向かって上記の順に重ねることによって形成されている。なお、めっき層54は、図5に示すように、隣接する列状体の対応する貫通孔46の周囲のめっき層54と繋がるように形成されている。   Next, as shown in FIG. 4E, the periphery of each lower through hole 46a on the lower surface of the lower substrate 42a, the periphery of each upper through hole 46b on the upper surface of the upper substrate 42a, and the inner peripheral surface of each lower through hole 46a. A plating layer 54 is integrally formed on the inner peripheral surface of each upper through-hole 46b and a portion of each long fuse wire 46 in each through-hole 46. As described above, the plating layer 54 is formed by stacking the electroless copper plating layer, the electrolytic copper plating layer, the electrolytic nickel plating layer, and the electrolytic tin plating layer in the order described above from the lower substrate 42a and the upper substrate 42b. Is formed by. As shown in FIG. 5, the plating layer 54 is formed so as to be connected to the plating layer 54 around the corresponding through hole 46 of the adjacent columnar body.

そして、図5および図4(e)に点線で示す切断線に沿って、基板42を切断することによって、チップ型ヒューズ1が、多量に同時に形成される。なお、切断線は、各列状体における対応する貫通孔46の中心を通るものと、隣接する列状体の間の間隔の中央をそれぞれ通るものとがあり、さらに、基板42の各辺に沿って切断するものもある。   Then, by cutting the substrate 42 along the cutting lines indicated by the dotted lines in FIGS. 5 and 4 (e), a large number of chip-type fuses 1 are simultaneously formed. In addition, there are cutting lines that pass through the center of the corresponding through-hole 46 in each columnar body, and those that pass through the center of the interval between adjacent columnar bodies, and further, on each side of the substrate 42 Some cut along.

このようなチップ型ヒューズ1の製造方法によれば、切断することによってチップ型ヒューズ1の端子8a、8bとなる部分と、これら端子8a、8bとヒューズ線6との接続部分との形成を、めっき層54を形成することによって行っているので、チップ型ヒューズ1の本体2と別個に端子を形成したり、この端子とヒューズ線とを接続したりする作業が不要であるので、量産を容易に行うことができる。   According to such a manufacturing method of the chip-type fuse 1, the portions that become the terminals 8 a and 8 b of the chip-type fuse 1 by cutting and the connection portions between the terminals 8 a and 8 b and the fuse line 6 are formed. Since the plating layer 54 is formed, it is not necessary to form a terminal separately from the main body 2 of the chip-type fuse 1 or to connect the terminal and the fuse wire, so that mass production is easy. Can be done.

上記の実施の形態では、図1に示すように下部基板42a、上部基板42bそれぞれに凹部48a、48bを形成したが、例えば下部基板42aのみに凹部を形成することもできる。但し、この場合には、下部基板42aの高さを、上記の実施の形態に示した下部基板42aよりも高くし、下部凹部48aの深さも深くし、長尺のヒューズ線44は、下部凹部48aの高さのほぼ中央に位置させることが望ましい。そのため、下部基板48aに形成する溝50aは、上記の実施の形態の場合よりも深く形成することが望ましい。但し、上部基板48bの溝50bは不要になる。このように構成すると、上部基板42bには、上部貫通孔46bのみを形成すればよいので、その製造が容易になる。   In the above embodiment, as shown in FIG. 1, the recesses 48a and 48b are formed in the lower substrate 42a and the upper substrate 42b, respectively. However, the recesses can be formed only in the lower substrate 42a, for example. However, in this case, the height of the lower substrate 42a is made higher than that of the lower substrate 42a shown in the above embodiment, the depth of the lower recess 48a is also increased, and the long fuse wire 44 is connected to the lower recess 42a. It is desirable to be positioned approximately at the center of the height of 48a. Therefore, it is desirable that the groove 50a formed in the lower substrate 48a is formed deeper than in the case of the above embodiment. However, the groove 50b of the upper substrate 48b is unnecessary. If comprised in this way, since only the upper through-hole 46b should be formed in the upper board | substrate 42b, the manufacture becomes easy.

上記の実施の形態では、絶縁基板42に複数の列状体を形成したが、最低限度1つの列状体を形成するだけでもよい。   In the above-described embodiment, a plurality of columnar bodies are formed on the insulating substrate 42. However, at least one columnar body may be formed at a minimum.

本発明の1実施形態の製造方法によって製造されたチップ型ヒューズの斜視図、中央縦断面図、中央縦断面図の拡大図である。It is a perspective view of a chip type fuse manufactured by a manufacturing method of one embodiment of the present invention, a central longitudinal section, and an enlarged view of a central longitudinal section. 本発明の1実施形態の製造方法の初期の過程を示す図である。It is a figure which shows the initial stage process of the manufacturing method of one Embodiment of this invention. 本発明の1実施形態の製造方法の中間の過程を示す図である。It is a figure which shows the intermediate process of the manufacturing method of one Embodiment of this invention. 本発明の1実施形態の製造方法の残りの過程を示す図である。It is a figure which shows the remaining processes of the manufacturing method of one Embodiment of this invention. 発明の1実施形態の製造方法の最終過程を示す図である。It is a figure which shows the last process of the manufacturing method of one Embodiment of invention.

符号の説明Explanation of symbols

42 絶縁基板
44 長尺のヒューズ線
46 貫通孔
48 中空部
42 Insulating substrate 44 Long fuse wire 46 Through hole 48 Hollow part

Claims (3)

絶縁基板の上下面間を貫通する複数の貫通孔が所定の間隔をおいて一列に形成され、隣接する前記貫通孔間の前記絶縁基板内にそれぞれ中空部が形成された列状体において、前記各貫通孔及び前記各中空部を直線状に通って長尺のヒューズ線が挿通されたヒューズ半製品を形成する過程と、
前記各貫通孔の上下面周囲、前記各貫通孔内及び前記各貫通孔内に突出している前記ヒューズ線を一体にめっきする過程と、
前記各貫通孔を通る切断線に沿って前記基板を切断する過程とを、
具備するチップ型ヒューズの製造方法。
A plurality of through holes penetrating between the upper and lower surfaces of the insulating substrate are formed in a row at a predetermined interval, and the hollow body is formed in each of the insulating substrates between the adjacent through holes. Forming a semi-finished fuse product in which a long fuse wire is inserted through each through hole and each hollow portion in a straight line; and
The process of integrally plating the fuse wires protruding around the upper and lower surfaces of each through hole, in each through hole and in each through hole;
Cutting the substrate along a cutting line passing through each through hole,
A method for manufacturing a chip-type fuse.
請求項1記載のチップ型ヒューズの製造方法において、前記基板には、複数の前記列状体が互いに平行に設けられ、前記切断は、前記各列状体の対応する貫通孔を通る切断線と、前記各列状体間を通る切断線とに沿って、行われるチップ型ヒューズの製造方法。   2. The chip-type fuse manufacturing method according to claim 1, wherein a plurality of the columnar bodies are provided in parallel to each other on the substrate, and the cutting is performed by a cutting line passing through a corresponding through hole of each of the columnar bodies. A method for manufacturing a chip-type fuse, which is performed along a cutting line passing between the respective columns. 請求項1記載のチップ型ヒューズの製造方法において、前記基板は、上部基板及び下部基板とに分割形成され、前記上部及び下部基板には、複数の上部貫通孔と複数の下部貫通孔とが形成され、これら上部貫通孔と下部貫通孔とのうち互いに対応するものを、一致させて上部基板及び下部基板が接着されており、少なくとも前記下部基板には、前記下部貫通孔間に前記中空部形成用の凹部が形成され、前記接着の前に前記ヒューズ線が前記列状体中の下部貫通孔及び前記中空部形成用の凹部に位置するように配置されるチップ型ヒューズの製造方法。
2. The method of manufacturing a chip-type fuse according to claim 1, wherein the substrate is divided into an upper substrate and a lower substrate, and a plurality of upper through holes and a plurality of lower through holes are formed in the upper and lower substrates. The upper substrate and the lower substrate are bonded by matching the corresponding ones of the upper through hole and the lower through hole, and at least the lower substrate has the hollow portion formed between the lower through holes. A chip-type fuse manufacturing method in which a recess is formed and the fuse wire is positioned before the bonding so that the fuse wire is positioned in a lower through hole in the columnar body and in the recess for forming the hollow portion.
JP2005062104A 2005-03-07 2005-03-07 Manufacturing method of chip-type fuse Expired - Lifetime JP4200450B2 (en)

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