JP4200560B2 - Server apparatus and server apparatus control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a server apparatus and a server apparatus control method capable of realizing a reduction in power by using a semiconductor memory as a recording medium.
[0002]
[Prior art]
When storing moving images in an AV server using a semiconductor memory as a recording medium, the amount of moving image data is generally very large, so a huge semiconductor memory is required to record them.
[0003]
[Problems to be solved by the invention]
Therefore, conventionally, there has been a problem that the power consumption of the entire AV server becomes very large.
[0004]
Accordingly, an object of the present invention is to provide a server apparatus and a server apparatus control method capable of suppressing power consumption even when a semiconductor memory is used as a recording medium for storing moving images.
[0005]
[Means for Solving the Problems]
The invention according to claim 1, in controllable server device from a computer connected to the network, when recording or reproducing data on a recording medium comprising a semiconductor memory divided into a plurality of memory cells, the while securing the one or more memory cells having a memory capacity corresponding to one time, after the elapse of a short second time than the first time, one or a memory capacity corresponding to the second time and securing means for securing a plurality of memory cells, among the semiconductor memory, a power supply of one or more memory cells having a memory capacity corresponding to the first time, among the semiconductor memory, corresponding to a second time together to turn on the power of one or more memory cells having a memory capacity, a memory capacity corresponding to a second time that is previously recorded or reproduced Or the power of the plurality of memory cells to clear, when the recording or reproduction is stopped, and a control means for controlling to turn off the one or more memory cells having a memory capacity corresponding to the first time It is a server device provided.
And a control method of the server device.
[0006]
Audio signals or video signals recorded on the AV server from the PC are controlled in real time via the Ethernet. The AV server uses a recording medium composed of a flash memory. When an image signal is input, it is compressed by an encoder and then distributed to 41 streams by a distributor. The distributed 41 streams are supplied to the memory module. The 41 streams read from the memory module are combined into one stream by the combiner. In the decoder, the stream is expanded and an image signal is output. At this time, power consumption during standby can be suppressed by supplying operation power only to the memory to be accessed in the memory module.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. An example of recording and reproducing an image on an AV server using a memory as a recording medium will be described. The AV server used in this embodiment has one input and one output, and a flash memory is used as the memory.
[0008]
FIG. 1 shows an overall view of the system. The AV server 5 is controlled as follows. The PC 1 issues a command to the AV server 5. The PC 1 is equipped with a GUI for recording and reproducing images, and the user can control the AV server 5 by using the GUI. A command issued from the PC 1 is input to the IDC 3 via the Ethernet 2. IDC is an abbreviation for Intelligent Device Controller, which converts an asynchronous command sent from the PC 1 into a command synchronized with the reference of the broadcast station. The IDC 3 also controls the switcher 4 in addition to the AV server 5. The switcher 4 selects an input signal desired to be recorded from the AIR 6, VTR 7, VTR 8, and editor 9 and also selects and outputs a desired output destination during reproduction.
[0009]
Next, a block diagram inside the AV server 5 shown in FIG. 2 will be described. The input image signal 17 is input to the encoder 18 and compressed to 30 Mbps. The compressed signal is input to the disperser 19. The disperser 19 disperses the input stream into 41 streams. The reason for the dispersion is to create a plurality of slow streams because the writing speed of the flash memory used for the memory module 11 is slower than the image input speed. The number of distributed streams depends on the writing speed of the flash memory.
[0010]
The flash memory used in this embodiment is premised on the use of a memory that requires 8 μs in writing time, and in order to write image data at 30 Mbps in this memory, it is necessary to distribute the data to 41 streams. There is. The memory module 11 is a part where flash memories are gathered, and details will be described later.
[0011]
The synthesizer 20 returns the 41 streams to one stream and outputs the stream to the decoder 21. The decoder 21 decompresses the image and returns it to the original image. The image signal 22 returned to the original image is output.
[0012]
The recording counter 14 outputs an address and a control signal at the time of writing to each memory in the memory module 11. Similarly, the reproduction counter 15 outputs an address and a control signal at the time of reading. The recording counter 14 and the reproduction counter 15 operate in synchronization with a reference signal synchronized with a clock in the broadcasting station from the reference 12. The selector 16 also operates in synchronization with the reference 12, and switches either the recording counter 14 or the reproduction counter 15 at a constant timing and outputs it to the memory module 11.
[0013]
The latch 24 outputs a power selection signal 23, a power on signal, and a power off signal 25 to the memory module 11 in accordance with a command from the CPU 27. These signals control the power supply of memory cells to be written and read out of the memory cells in the memory module 11.
[0014]
The ROM 28 stores programs for recording and reproducing images, and the RAM 29 is used as an area for storing variables and the like when these programs are executed. The IDC I / F 13 interfaces with the IDC 3, receives a command from the PC 1, and transmits it to the CPU 27. The CPU 27, ROM 28, RAM 29, IDC I / F 13, recording counter 14, and reproduction counter 15 are connected by a bus 26.
[0015]
Next, a block diagram of the memory module 11 is shown in FIG. The inside of the memory module 11 is composed of 8 memory modules (41 to 45) in smaller units. The signal input from the disperser 19 is distributed to all of these memory modules 41 to 45. All outputs from the memory modules 41 to 45 are connected and output to the synthesizer 20. Of the eight memory modules 41 to 45, a memory to be recorded or reproduced is selected by a signal from the selector 16. The signal from the selector 16 and the signal from the latch 24 are input to all the memory modules 41 to 45.
[0016]
Next, the inside of the small unit memory modules 41 to 45 in FIG. 3 will be described. FIG. 4 shows an internal block diagram of the memory modules 41 to 45 in small units. The small unit memory modules 41 to 45 are configured by horizontal 8 × vertical 41 memory cells, and the 41 streams input from the disperser 19 are connected in the horizontal direction and output to the combiner 20. . The address 51 input from the selector 16 is composed of 29 bits, the upper 3 bits select a small unit of memory modules 41 to 45, and the subsequent 3 bits select a memory cell column and the rest The 23 bits become a write address or a read address of each memory.
[0017]
The control signal 52 switches between writing and reading to all memory cells. The decoder 54 generates a CS selection signal 53 for selecting a column. The power supply selection signal 23 also selects the memory modules 41 to 45 whose upper 3 bits are small, and selects the column by the subsequent 3 bits. The power supply selection signal 23 is input to the decoder 55. The decoder 55 outputs a power selection signal 56 and selects a column of memory cells to be subjected to power control. The power-on signal and the power-off signal 25 are used for switching the power state of the selected column of memory cells.
[0018]
Further, the inside of the memory cell will be described. FIG. 5 shows an internal block diagram of the memory cell. The memory cell includes a flash memory 81 and a power switch 82. The flash memory 81 has a capacity of 8 Mbytes. The signal input from the disperser 19 is connected to the data bus of the flash memory 81, and performs stream input / output. The CS selection signal 53 is connected to the CS terminal of the flash memory, and brings the flash memory 81 into an operating state. The address 51 has the lower 23 bits connected to the address terminal of the flash memory 81. The control signal 52 is connected to the WE terminal of the flash memory 81, switches the mode of the flash memory 81, and selects writing or reading.
[0019]
The power switch 82 is connected to the power ON signal, the power OFF signal 25, and the power selection signal 56. When the power selection signal 56 is asserted, the power ON signal and the power OFF signal 25 are valid. For example, when the power on signal is asserted in the state where the power selection signal 56 is asserted, the power switch 82 is turned on and the power 83 is supplied to the flash memory 81. The above is the internal configuration of the AV server using the flash memory as a recording medium. Thus, in this embodiment, as an example, 8 × 8 × 41 = 2624 8 Mbyte flash memories are used.
[0020]
Next, the operation of the AV server will be described. First, the recording system will be described. The data flow of the recording system is shown in FIG. FIG. 6A is a stream in which input data is output from the encoder 18. This stream is synchronized with the clock reference in the broadcast station, and one data is output in units of 6 clocks with a 27 MHz clock. The numbers assigned from 1-1 to 3-40 in the input data are for explaining the flow of data. The stream shown in FIGS. 6B and 6C is an output from the disperser 19 and is distributed into 41 slow streams.
[0021]
The command to the memory module shown in FIG. 6D is for instructing the operation of each memory cell, and the first write command composed of CMD1, CMD2, and CMD3 instructs the flash memory to perform the write operation. Is. Unlike a general RAM, a flash memory usually needs to send a write command in advance as shown in FIG. 6D because of its structure. The subsequent address (for example, 0-AD, 0 address) is the write address itself, and the subsequent WAIT is for waiting for the end of the writing of the data given to the flash memory. This is also the time required for the structure, and in this embodiment is 8 μs. The subsequent read address (R-AD) is used during a read operation to be described later. By performing the writing operation and the reading operation at different times, apparently recording and reproduction can be performed simultaneously.
[0022]
Next, the playback system will be described. The flow of data in the reproduction system is shown in FIG. The command to the memory module shown in FIG. 7A is a command for reading data from each memory cell. When an address (for example, an address of 1-1) is output, the data is output immediately after that. Inactive is a portion used at the time of writing described above. In FIG. 7A, in order to facilitate understanding, a state in which only reading is performed is written, and thus “Inactive” is indicated. The read data is output to the combiner 20 as shown in FIGS. 7B and 7C. As shown in FIG. 7D, output data is output from the synthesizer 20.
[0023]
Next, recording and reproduction processing will be described. FIG. 8 shows a flowchart of an example of the recording / reproducing process. When a command for instructing recording and reproduction is received from the IDC 3, in step 121, it is determined whether or not the received command is a recording command. If it is determined that the command is a recording command, control is transferred to step 123, and the recording command If not, control is passed to step 122. In step 122, it is determined whether or not the command is a playback command. If it is determined that the command is a playback command, control is transferred to step 124. If it is determined that the command is not a playback command, control is returned to step 121. In step 123, control of a recording process to be described later is performed, and when the recording process ends, the control returns to step 121. Then, in step 124, the reproduction process described later is controlled. When the reproduction process is completed, the control returns to step 121. In this way, the process jumps to the process corresponding to each command.
[0024]
First, FIG. 9 shows a flowchart of an example of the recording process. In the recording process, first, the file system is accessed to obtain a free area for the first 2 seconds (step 126). The file system is a part that manages files, and holds information such as a position on a memory map where each file is recorded and information on free space. When the area for 2 seconds is secured, the power supply selection circuit 23 is accessed to turn on the memory for 2 seconds (step 127).
[0025]
Thereafter, the write start address is output to the recording counter 14 to start recording (step 128). In this state, it waits for 1 second (step 129), and when 1 second has passed, the file system is accessed to obtain a free space for the next 1 second (step 130). When the free space for the next 1 second is obtained, the power supply selection circuit 23 is accessed, the newly obtained memory for 1 second is turned on, and the already written 1 second memory is turned off. (Step 132).
[0026]
These processes (steps 128 to 131) are repeated until a stop command for stopping recording is received from the IDC 3 (step 132). When the stop command is received, the recording counter 14 is stopped, the power of the memory for 2 seconds that is currently turned on is turned off, and the recording process is finished (step 133).
[0027]
The flash memory does not function immediately even when the power is turned on, and it takes a certain time until the operation is started. For this reason, in this embodiment, the power is turned on at least one second before being accessed by performing the processing as described above.
[0028]
Subsequently, a flowchart of an example of the reproduction process is shown in FIG. 10, and the reproduction process step will be described. First, the file system is accessed to obtain an area for the first 2 seconds of the file to be reproduced (step 135). Next, the power supply selection circuit 23 is accessed, and the power supply of the memory for 2 seconds is turned on (step 136). Thereafter, the read start address is output to the reproduction counter 15 and reproduction is started (step 137). In this state, it waits for 1 second (step 138), and after 1 second, the file system is accessed to obtain a region for the next 1 second (step 139).
[0029]
When the next area for 1 second is obtained, the power supply selection circuit 23 is accessed to turn on the memory for 1 second, and to turn off the memory for the already read area for 1 second (step 140). . These processes (steps 137 to 140) are repeated until a stop command for stopping reproduction is received from the IDC 3 (step 141). When the stop command is received, the playback counter 15 is stopped, the power of the memory for 2 seconds where the power of the memory is currently turned on is turned off, and the playback process is terminated (step 142).
[0030]
Here, the file system described above will be briefly described. The file system is software that manages information about each file. In this embodiment, the information held by the file system is a file name and an area on the memory where the file is written. Thereby, the conversion between the file name and the memory area where the file exists is performed. For example, when a playback command is received, the file system first converts the given file name to the actual memory area where the file is written, accesses the memory area based on the converted information, and Image data written in the area is read out.
[0031]
In this embodiment, since the recording medium is configured by a flash memory as the recording medium, data is not lost even if the power is turned off. Therefore, power is supplied only to the part to be accessed. Power supply control is possible, and as a result, more efficient power supply control is possible.
[0032]
In this embodiment, data to be recorded and reproduced on a recording medium is an image signal, but an audio signal may be used. That is, this method is particularly effective when data with real-time properties such as image signals and audio signals is handled. Since the data has real-time characteristics, it is possible to completely predict the memory to be accessed in advance, and it is possible to control the power supply in units of IC chips.
[0033]
In this embodiment, both the PC and the AV server are connected to the Ethernet, and the data recorded on the AV server is controlled by the PC. However, the present invention is not limited to this, and the data is recorded on the AV server via the so-called Internet. The data may be controlled.
[0034]
【The invention's effect】
In a conventional AV server using a semiconductor memory as a recording medium, power control is not particularly performed on the semiconductor memory, so that a current always flows through the semiconductor memory. When the AV server is used for broadcasting business, the semiconductor memory becomes quite large. In the above-described embodiment, the AV server is capable of recording a 30 Mbps image for about 1.5 hours, and uses 2624 8 Mbyte flash memories. Since the flash memory has a current of about 1 mA even during standby, a current of about 2.6 A (about 8.7 W) flows even when the AV server is not operating, considering an AV server of the same scale as this embodiment. When considering an actual broadcast business device, the scale of 1.5 hours at 30 Mbps is smaller, and the actual AV server is considered to be 10 times or more of this. Considering this, in reality, only about 26 A (about 87 W) is consumed in the memory portion alone.
[0035]
According to the present invention, as described above, the standby current can be made substantially zero, so that almost no power is consumed while not being accessed. Therefore, the power consumption of an AV server using a memory as a recording medium can be reduced. It becomes possible. In particular, this is particularly effective when there is a system that is not operating, such as at midnight, or when an AV server is mounted on the vehicle.
[0036]
In addition, according to the present invention, it is possible to reduce the heat generated from the recording medium, so that a heat dissipating facility such as a fan, which is necessary for an AV server using a hard disk as a recording medium, is not required. Density mounting becomes possible.
[Brief description of the drawings]
FIG. 1 is a schematic view of an embodiment applied to the present invention.
FIG. 2 is a block diagram of an embodiment of an AV server applied to the present invention.
FIG. 3 is a block diagram of an embodiment of a memory module applied to the present invention.
FIG. 4 is a block diagram of an embodiment of a memory module applied to the present invention.
FIG. 5 is a block diagram of an embodiment of a memory cell applied to the present invention.
FIG. 6 is a timing chart at the time of writing applied to the present invention.
FIG. 7 is a timing chart at the time of reading applied to the present invention.
FIG. 8 is a flowchart of an example of recording and reproduction processing applied to the present invention.
FIG. 9 is a flowchart of an example of a recording process applied to the present invention.
FIG. 10 is a flowchart of an example of a reproduction process applied to the present invention.
[Explanation of symbols]
5 ... AV server, 11 ... memory module, 12 ... reference, 13 ... IDC I / F, 14 ... recording counter, 15 ... playback counter, 16 ... selector , 17, 22 ... Image signal, 18 ... Encoder, 19 ... Disperser, 20 ... Synthesizer, 21 ... Decoder, 23 ... Power supply selection signal, 24 ... Latch, 25 ... Power on signal, Power off signal, 26 ... Bus, 27 ... CPU, 28 ... ROM, 29 ... RAM

Claims (8)

In a server device that can be controlled from a computer connected to a network,
When recording or reproducing data on a recording medium comprising a semiconductor memory divided into a plurality of memory cells, while securing the one or more memory cells having a memory capacity corresponding to the first time, the first Securing means for securing one or a plurality of memory cells having a memory capacity corresponding to the second time after a second time shorter than one time has elapsed;
Among the above semiconductor memory, a power supply of one or more memory cells having a memory capacity corresponding to the first time, among the above semiconductor memory, 1 has a memory capacity corresponding to the second time or together to turn on the power of a plurality of memory cells, already off the power of one or more memory cells having a memory capacity corresponding to recorded or reproduced the second time, when the recording or reproducing is stopped And a control unit that controls the power of one or more memory cells having a memory capacity corresponding to the first time to be turned off. The control means controls to supply power only to a memory cell in which a file being recorded or reproduced in the semiconductor memory exists, and not to supply power to memory cells other than the memory cell. The server device according to 1. 2. The server device according to claim 1, wherein the control unit is configured to supply power only to a memory cell that is recording or reproducing data to and from the semiconductor memory and not to supply power to memory cells other than the memory cell. . The server device according to claim 1, wherein when the power is not supplied, the control unit uses an electronic switch to stop power supply to the memory cell .   The server device according to claim 1, wherein the second time is half of the first time.   The server device according to claim 1, wherein the network is Ethernet or the Internet. The server device according to claim 1, wherein each of the memory cells is a flash memory. In a method for controlling a server device that can be controlled from a computer connected to a network,
When recording or reproducing data on a recording medium comprising a semiconductor memory divided into a plurality of memory cells, while securing the one or more memory cells having a memory capacity corresponding to the first time, the first after a lapse of a short second time than the first time, and ensuring step of securing one or more memory cells having a memory capacity corresponding to the second time,
Among the above semiconductor memory, a power supply of one or more memory cells having a memory capacity corresponding to the first time, among the above semiconductor memory, 1 has a memory capacity corresponding to the second time or together to turn on the power of a plurality of memory cells, already off the power of one or more memory cells having a memory capacity corresponding to recorded or reproduced the second time, when the recording or reproducing is stopped And a control step of controlling the power of one or more memory cells having a memory capacity corresponding to the first time to be turned off.

Images