JP3673091B2 - Clock control circuit and digital signal processing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock control circuit and a digital signal processing apparatus including the same.
[0002]
[Prior art]
As an application example of the digital signal processing apparatus, an MD (mini disk) system will be described as an example. However, the conventional digital signal processing apparatus (including the MD system) is provided with a circuit for generating a clock, but the one corresponding to the clock control circuit of the present invention for generating and controlling the clock is provided. It is not done. As a conventional MD system, one described in JP-A-6-103699 is known.
[0003]
FIG. 4 is a schematic block diagram of a conventional mini disk system. In FIG. 4, 1 is a disk which is a recording / reproducing medium, 2 is a reproduction signal processing circuit, 3 is a memory for temporarily storing reproduced data, 4 is a compression / decompression circuit for restoring compressed data, and 5 is a restored data. Digital / analog converter for converting into an audio signal, 10 is an analog / digital converter for digitizing an analog audio signal, 9 is a compression circuit for compressing the digitized data to reduce the amount of data, and 8 is temporarily recording data Memory for storing, 7 is a recording signal processing circuit, 6 is a servo circuit for moving the recording medium at a predetermined speed, 11 is a memory control circuit for managing the storage state of the memory, and 12 is a system including the memory control circuit 11 It is a clock generation circuit that supplies a clock to a member that requires a clock. FIG. 5 is a conceptual diagram showing the operation of the memory control circuit.
[0004]
The operation of the conventional mini disc system configured as described above will be described. A signal reproduced from the disk 1 is reproduced as data by the reproduction signal processing circuit 2 and temporarily written in the memory 3. Although details will be described later, the memory 3 is used to perform signal transfer rate conversion, and the memory control circuit 11 instructs the compression / decompression circuit 4 to output a reproduction signal. In the case of MD, since the data is recorded by the compression method called ATRAC, the compression / decompression circuit 4 performs the decompression process to restore the audio signal. The data thus restored is converted into an analog audio signal by the D / A converter 5 and output.
[0005]
During recording, an analog audio signal is converted into digital data by the A / D converter 10, and the signal is converted into a data string based on the ATRAC standard by the compression circuit 9. This compression process is a process that has been introduced in order to prolong the recording time that can be recorded on one disc, the transfer rate of data that is recorded and reproduced by the compression process is A / D · D / A Therefore, when transferring at the same rate, it is necessary to create a waiting time to convert the transfer rate. This rate conversion process is controlled by the memory control circuit 11 as will be described later. The output of the compression circuit 9 is once written in the memory 8 and is output to the recording signal processing circuit 7 in accordance with an instruction from the memory control circuit 11. The memory control circuit 11 issues a command to the servo circuit 6 in accordance with the reading from the memory, and controls the data to be written at a correct position based on the address information written in advance on the disk. In the operation of the servo circuit 6, the same address control process is performed during reproduction.
[0006]
In both reproduction and recording, the clock generation circuit 12 supplies a clock to members that require a clock in the system such as the memory control circuit 11. However, the clock generation circuit 12 is accessed only when necessary for each member in order to correct the operation timing shift in each member rather than continuously supplying to each member.
[0007]
The operation of the memory control circuit 11 will be described with reference to FIG. The horizontal axis direction in FIG. 5 indicates the flow of time.
[0008]
When writing to the memory 3 is started at point (a), the amount of memory used increases rapidly.
[0009]
Next, reading from the memory is started at point (b). In the case of the MD system, since the transfer rate of data reproduced from the disk is set faster than the rate of the signal reproduced as an audio signal, the memory usage increases although the rate of increase decreases even when reading is started. Go.
[0010]
Before the memory capacity overflows, the writing to the memory is temporarily stopped at the point (c). In this way, only reading is performed, so the amount of memory used decreases gradually.
[0011]
After a while, the writing to the memory is resumed at point (d). In this way, by repeating the operations (c) and (d), transfer rate conversion processing is executed while reading is continued.
[0012]
The point (g) represents a case where the reproduction signal from the disc is interrupted for some reason, and a state in which writing cannot be performed for a while continues, and before all the contents of the memory are read, If writing can be started at point (h), the reproducing operation can be continued without interrupting the reading side.
[0013]
(I) After the data is stored in the memory up to the point, the same operation as (d) and (e) is performed.
[0014]
Since the memory is used in this way, the reading side operates continuously, but the writing side only needs to operate when necessary. Accordingly, power consumption can be reduced by stopping the clock of the circuit on the writing side when no operation is required. Further, when only the processing on the reading side needs to be executed, the processing amount is smaller than in the case of performing both normal writing and reading, and therefore it is conceivable to operate the signal processing processor by lowering the operation clock.
[0015]
[Problems to be solved by the invention]
When switching the clock system, it is usually done by issuing a reset to initialize the internal circuit state and then operating with a new clock, but while continuously reading data as described above If you try to switch clocks, you cannot reset. In addition, in devices that do not need to consider the instability of operation when switching such that there is no part that is continuously operating, switching can be performed without resetting, but In a device having a certain portion, there is a possibility that the operation becomes abnormal when such processing is performed.
[0016]
In consideration of the above-described problems, the present invention is efficient by including a clock control circuit capable of switching clocks without substantially affecting the clock supply destination and the clock control circuit of the present invention. An object of the present invention is to provide a digital signal processing apparatus capable of performing signal processing.
[0017]
[Means for Solving the Problems]
In order to solve the above-described problem, a first aspect of the present invention (corresponding to the aspect of the present invention described in claim 1) includes a clock generator that switches clocks of at least two frequencies and outputs them as a master clock, and the master clock And a temporary storage unit for temporarily storing data during data processing. When the timing control unit receives a clock switching request, the temporary storage unit outputs the output clock to the output clock. monitors whether or not the access, with no the access timing, a clock control circuit, characterized by instructing the switching of the master clock to the clock generator.
[0018]
According to a second aspect of the present invention (corresponding to the aspect of the present invention described in claim 2), after the timing controller instructs to switch the master clock, the new output clock based on the switched master clock is generated. In the clock control circuit according to the first aspect of the present invention, the output clock is not output until the output is started.
[0019]
According to a third aspect of the present invention (corresponding to the present invention described in claim 3), the clock control circuit of the present invention and mode switching means for switching at least two processing modes are provided, and the mode switching means The digital signal processing apparatus outputs the clock switching request corresponding to each processing mode to the timing control unit when switching the processing mode.
[0020]
The fourth of the present invention (corresponding to the invention of claim 4), the two processing modes, the reading of data from the temporary memory means, and concurrent Mr writing of data of the to the temporary storage means The digital signal processing apparatus according to the third aspect of the present invention is characterized in that the first processing mode is a second processing mode in which only reading of data from the temporary storage means is performed.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
FIG. 1 is a schematic block diagram of a digital signal processing apparatus according to an embodiment of the present invention. The digital signal processing apparatus according to the present embodiment is obtained by mounting the clock control circuit of the present invention on the conventional minidisk system described with reference to FIG.
[0024]
In FIG. 1, 1 is a disk which is a recording / reproducing medium, 2 is a reproduction signal processing circuit, 3 is a memory for temporarily storing reproduced data, 4 is a compression / decompression circuit for restoring compressed data, and 5 is a restored data. Digital / analog converter for converting into an audio signal, 10 is an analog / digital converter for digitizing an analog audio signal, 9 is a compression circuit for compressing the digitized data to reduce the amount of data, and 8 is temporarily recording data Memory for storing, 7 is a recording signal processing circuit, 6 is a servo circuit for moving the recording medium at a predetermined speed, 11 is a memory control circuit for managing the storage state of the memory, and 101 is a master by switching clocks of two frequencies Clock generator for outputting as a clock, 102 is an output clock based on the master clock An output timing controller. The clock generator 101 and the timing controller 102 constitute the clock control circuit of the present invention.
[0025]
In addition, in each of the above members, those having the same functions as those of the conventional mini disk system shown in FIG. 4 are given the same reference numerals, and details of those functions and operations are shown in FIG. This is equivalent to that of the conventional mini disk system. That is, for the operation of the memory control circuit 11, writing and reading are controlled with respect to the memories 3 and 8 according to FIG. However, the difference between the mini-disc system of FIG. 4 and the mini-disc system as the digital signal processing apparatus in the present embodiment is that the clock used for the operation of each member is not from the clock generator 12 of FIG. This is a point related to being supplied from the clock generation unit 101 and the timing control unit 102 which are clock control circuits of the present invention.
[0026]
FIG. 2 is a block diagram of the clock control circuit according to the embodiment of the present invention, and shows details of the clock generation unit 101 and the timing control unit 102 of FIG. In FIG. 2, 101 is a clock generator, and 102 is a timing controller. FIG. 3 is a timing diagram for explaining the operation of the timing control unit 102, and the horizontal axis direction in FIG. 3 indicates the flow of time. In FIG. 3, 201 is a clock switching request signal from the memory control circuit 11, 202 is an access information signal indicating whether or not the memories 3 and 8, etc. are accessing the output clocks 207 and 208, and 203 is to the clock generator 101. switching signal, an initialization signal from the clock generator 101 is 204, 205 access permission signal indicating whether the access to the output clock 207 and 208 from the outside, 206 a phase of the master clock 209 by the timing control unit 102 , 207 is an output clock to the memory read system, 208 is an output clock to the memory write system, and 209 is the clock generator 101 to the timing controller 102. This is an output master clock (not shown in FIG. 3). The clock switching request signal 2 01, when the signal ON is a switch to the processing mode only data read processing, when the signal OFF is to process mode for performing a reading process and the writing process of data of the data by concurrent This shows the switching. The access permission signal 205 indicates that access to the external output clocks 207 and 208 is permitted when the signal is ON, and prohibition of access to the external output clocks 207 and 208 when the signal is OFF. . The output clocks 207 and 208 are used in the memories 3 and 8 and may be output directly from the timing control unit 102 to the supply destination, but here are supplied via the memory control circuit 11. The following explanation will be given. Similarly, for the access information signal 202, the timing control unit 102 may directly detect and issue an access from the memories 3, 8, etc., but here the following explanation is given assuming that it is issued by the memory control circuit 11. Do.
[0027]
Hereinafter, an example of processing mode switching will be described with reference to FIG.
[0028]
The memory control circuit 11, the memory 3 and / or memory 8, the data read processing, it is assumed that the control to perform the write processing of data concurrency (for example, in FIG. 5 ( d) to (e)). The memory control circuit 11 refers to the amount of memory used and changes the processing mode so that only the data reading process is performed on the memory 3 and / or the memory 8. At the same time or immediately after that, the memory control circuit 11 outputs a clock switching request signal 201 to the timing control unit 102. When the timing control unit 102 receives the clock switching request signal 201, the timing control unit 102 starts monitoring the access information signal 202 from the memory control circuit 11. During normal operation, the access information signal 202 is generated for both writing to and reading from the memory. However, when processing mode switching is performed, writing to the memory does not occur. The access information signal 202 becomes 0. At this timing (dotted line timing in FIG. 3), the timing control unit 102 outputs the switching signal 203 to the clock generation unit 101 and turns off the output of the access permission signal 205 to the memory control circuit 11. . At the same time, the output clock 208, which is a clock for the memory writing system, is stopped.
[0029]
The clock generator 101 receives the changeover signal 203, executes the switching of the master clock 209 is required latency order not to generate excess noise on the clock. When this waiting time is over and the switching of the master clock 209 is completed, the clock generator 101 issues an initialization signal 204. In the initialization signal 2 04 of the timing controller 102 has received, the phase of the master clock 209 and the reference clock 206 for the access timing of the memory is initialized, to ensure consistency between the clock switching previously. When the initial phase adjustment is completed, an access permission signal 205 is output to the memory control circuit 11 . At the same time, the output clock 207 of the readout system starts to output.
[0030]
In such a switched state, the frequency of the master clock 209 is lowered, the clock for the memory write system is stopped, and the clock for the memory read system is also lowered, so that extra power consumption can be reduced. Therefore, for example, when a battery is used as a power supply source, a system having a long battery life can be realized.
[0031]
From the processing mode only data read process, for switching to the processing mode in which the writing processing of the reading process and the data of the data by parallel lines also conforms to the above.
[0032]
In the present embodiment, the digital signal processing apparatus of the present invention has been described as a mini-disc system. However, the present invention is not limited to this, and other digital signal processing apparatuses may be used. The clock control circuit according to the invention and mode switching means for switching between at least two processing modes are provided, and the clock switching request corresponding to each processing mode when the mode switching means switches between the processing modes. As long as it is a digital signal processing device that outputs the signal to the timing control unit.
[0033]
In the present embodiment, the clock control circuit according to the present invention is described as being provided in the minidisk system and using the RAM access signal as an access to the output clock. However, the present invention is not limited to this. In short, the clock control circuit includes a clock generation unit that switches clocks of at least two frequencies and outputs them as a master clock, and a timing control unit that outputs an output clock based on the master clock, When the timing control unit receives a clock switching request, it may be a clock control circuit that monitors access to the output clock and instructs the clock generation unit to switch the master clock at a timing when there is no access.
[0034]
【The invention's effect】
As is apparent from the above description, the present invention according to claims 1 and 2 can provide a clock control circuit capable of switching clocks without substantially interfering with the clock supply destination.
[0035]
Further, the present invention of claims 3 and 4 can provide a digital signal processing apparatus capable of performing efficient signal processing by including the clock control circuit of the present invention.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a digital signal processing apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram of a clock control circuit according to an embodiment of the present invention.
FIG. 3 is a timing chart for explaining the operation of the clock control circuit according to the embodiment of the present invention.
FIG. 4 is a block diagram of a conventional MD system.
FIG. 5 is a timing diagram showing fluctuations in the amount of buffer memory used in a conventional MD system.
[Explanation of symbols]
1 disc 2 reproduction signal processing circuit 3 and 8 memory 5 D / A converter 6 servo circuit 7 records the signal processing circuit 4,9 compression / decompression circuit 10 A / D converter 11 memory control circuit 101 clock generation unit 102 a timing control unit 201 clock switching request signal 202 access information signal 203 switching signal 204 initialization signal 205 access permission signal 206 access timing reference clock 207 reads system output clock 208 writing system output clock

Claims (4)

A clock generator that switches clocks of at least two frequencies and outputs them as a master clock; a timing controller that outputs an output clock based on the master clock; and temporary storage means for temporarily storing data during data processing the timing controller receives a clock switching request, and monitors whether the the temporary storage means is accessing said output clock, with no the access timing, the master clock to the clock generator A clock control circuit for instructing switching of the clock.   The timing control unit does not output the output clock after instructing the switching of the master clock until starting to output a new output clock based on the switched master clock. Item 2. The clock control circuit according to Item 1.   3. A clock control circuit according to claim 1 and mode switching means for switching between at least two processing modes, wherein the mode switching means switches to each processing mode when switching between the processing modes. A digital signal processing apparatus that outputs the corresponding clock switching request to the timing control unit. The two processing modes are:
A first processing mode for reading data from the temporary storage means and writing data to the temporary storage means in parallel;
4. The digital signal processing apparatus according to claim 3, wherein the digital signal processing apparatus is in a second processing mode in which only reading of data from the temporary storage means is performed.

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