JP4253752B2 - Programmable controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a programmable controller including a CPU board and an expansion board.
[0002]
[Prior art]
A conventional programmable controller includes, for example, a CPU module, an I / O module prepared according to the number of control points of various devices to be controlled, a motherboard as a base for these modules, and a motherboard for electrical connection. It consists of In this motherboard, means for reading the ID code of each I / O module in accordance with a command from the CPU module when the power is turned on and transmitting it to the CPU module, and sending and receiving between the CPU module and each I / O module Means and the like for controlling the signals to be taken into each other are provided.
[0003]
[Problems to be solved by the invention]
The conventional programmable controller described above is indispensable because the motherboard has the above functions, but since the outer shape is formed in a box shape so that each module can be attached to the motherboard, the outer shape of each module The dimensions were large, and the overall size was large due to the presence of the motherboard. In addition, the number of parts is increased due to the presence of the mother board, which increases the cost.
[0004]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a programmable controller that is miniaturized and inexpensive in terms of cost.
[0005]
[Means for Solving the Problems]
The programmable controller according to claim 1 of the present invention is a programmable controller formed by laminating one or a plurality of expansion boards to which various devices to be controlled are connected to a control board and connecting them in series. The expansion board has a plurality of mode pins to which a potential corresponding to a connection position is applied, and a stack position recognition unit that recognizes a stack position based on the potential applied to the plurality of mode pins, and an ID code An ID code generation unit for generating, and the control board stores the ID code of the expansion board in a memory based on the stacking position, and then recognizes and recognizes the type of the expansion board from the ID code The expansion board determination unit executes a memory allocation operation based on the number of control points of the expansion board of the type described above.
[0006]
In the programmable controller according to claim 2 of the present invention, the potential of each mode pin of the stacking position recognition unit is given by the control board or the upper or lower expansion board based on the stacking position of the expansion board. In the lowermost expansion board where no expansion board exists, a potential generated in the expansion board is applied.
[0007]
The programmable controller according to claim 3 of the present invention is such that the expansion board is connected to an address bus, a data bus, and a data bus, and is provided for a plurality of I / Os provided according to the number of control points of various devices to be controlled. A gate array and a signal transfer direction setting unit for setting the transfer direction of the address signal on the address bus from the stack position and setting the transfer direction of the data signal on the data bus from the stack position according to read time and write time And an address decoding unit that has a preset address corresponding to the extension board to be stacked, and selects an address based on the stacking position, and an address signal transferred from the control board via an address bus When the address is input, it is determined whether the address is selected by the address decoding unit. In which a gate array selector for selecting I / O gate arrays based on address.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is an external view of a programmable controller according to an embodiment of the present invention, FIG. 2 is a plan view of an input / output expansion board, and FIG. 3 is a plan view of the input expansion board.
In the figure, reference numeral 1 denotes a control board (hereinafter referred to as “CPU board”), which has an expansion connector 2 erected on one side, and stores a CPU, a system program, a sequence program, etc. (not shown). An input / output connector and the like are provided for connection to the memory and various devices to be controlled.
[0009]
The CPU stores an ID code in the memory based on a stack position recognized by an expansion board to be described later. At the start of operation, the ID code is read to determine whether the ID code is normal. Recognizes the type of expansion board from the ID code, and starts the operation by allocating memory based on the number of control points of the recognized type of expansion board, and starts operation when the ID code is abnormal It has a function to prohibit. During operation, the sequence program is executed and decoded, and various devices connected to the CPU board 1 and the expansion board are controlled based on the result.
[0010]
Reference numeral 11 denotes an input / output expansion board. For example, as shown in FIG. 2, a first extension connector 12 erected on one surface of the board body (substrate) and a dedicated cable connection provided laterally on the same surface. And a second extension connector 13 and input and output connectors 14 and 15 for connecting to various devices to be controlled. The first expansion connector 12 described above is disposed so as to be connectable to the expansion connector 2 of the CPU board 1 and the first expansion connector of the input expansion board described later.
[0011]
Reference numeral 31 denotes an input expansion board. For example, as shown in FIG. 3, a first expansion connector 32 is provided upright on one side of the board, and a second for connecting a dedicated cable provided sideways on the other side. The expansion connector 33 and input connectors 34 and 35 for connecting to various devices to be controlled are provided.
[0012]
The input / output expansion board 11 and the input expansion board 31 have their stack positions determined from the arrangement of the first expansion connectors 12 and 32 provided on each of them. For example, when three CPU boards 1 are stacked, as shown in FIG. 1, the input / output expansion board 11 is arranged in the first and second stages, and the input expansion board 31 is arranged in the third stage. Each expansion board 11, 31 is fixed via a spacer 51.
[0013]
The input / output expansion board 11 is used in the first stage because, as described above, the first expansion connector 12 of the input / output expansion board 11 is disposed at a position facing the expansion connector 2 of the CPU board 1. This is because the input / output expansion board 11 is used in the second stage, and the input expansion board 31 is used in the third stage. When the expansion boards 11 and 31 are inverted, the first expansion boards are used. This is because the connectors 12 and 32 face each other.
[0014]
When three sheets are stacked in this way, the second expansion connectors 13 of the first and second input / output expansion boards 11 are connected to each other by a dedicated cable 52 and coupled to the CPU board 1. Let When this dedicated cable 52 is connected, it is bent at two places as shown in the figure, and this is for aligning the pins of the respective second expansion connectors 13.
[0015]
Also, when stacking one board on the CPU board 1, the input / output expansion board 11 is used for the above reasons, and when stacking two boards, the input / output expansion board 11 is arranged at the first stage, and the second stage. One of the input / output expansion board 11 and the input expansion board 31 is arranged in FIG. Also in this case, the first stage and the second stage are connected by the dedicated cable 52 as described above.
[0016]
Next, circuit configurations of the input / output expansion board 11 and the input expansion board 31 will be described with reference to FIGS. FIG. 4 is a block diagram showing the circuit configuration of the input / output expansion board, and FIG. 5 is a block diagram showing the circuit configuration of the input expansion board.
In the figure, reference numeral 16 denotes a programmable logic device formed by hardware configuration of each function of the stack position recognition unit, ID code generation unit, signal transfer direction setting unit, address decoding unit and gate array selection unit according to the present invention ( (Hereinafter referred to as “PLD”), a large number of pins (not shown) connected to the address buses 20a and 20b and the data bus 21 laid on the substrate, buffers 17 and 18 and each gate array 19 are connected to A plurality of pins (not shown) connected via conductors, two mode pins 23 connected to the first extension connector 12 via conductors, and one ID pin 24 etc. ing.
[0017]
The address bus 20a is connected to the first extension connector 12, the address bus 20b is connected to the buffer 17 connected to the second extension connector 13, and the data bus 21 branches to the first extension connector 12. And a buffer 18 connected to the second expansion connector 13 and to each gate array 19.
[0018]
When the first expansion connector 12 is not connected to any of the two mode pins 23, the potential (high level) generated by the expansion board 11 is applied to the first expansion connector 12. When 12 is connected to the expansion connector 2 of the CPU board 1, the potential becomes low level. This is because the pins on the expansion connector 2 side of the CPU board 1 connected to the mode pins 23 are connected to the ground.
[0019]
When the first expansion connector 12 is connected to the first expansion connector 32 of the input expansion board 31, a high level potential is still applied to each mode pin 23. This is because one of the two mode pins 23 is not connected to the first expansion connector 32 side and the other pin is a mode pin on the input expansion board 31 side that is at a high level. Because it is connected.
[0020]
The ID pin 24 described above is for causing the PLD 16 to generate an ID code. In the input / output expansion board 11, a preset high level potential is applied to the ID pin 24.
[0021]
The PLD 16 of the input / output expansion board 11 recognizes that the two mode pins 23 are stacked at the first level when the potentials of the two mode pins 23 are at a low level, and when the potentials of the mode pins 23 are at a high level. Is recognized as being stacked in the second stage, and when a high level potential is applied to the ID pin 24, a preset ID code (for example, D5h) is generated.
[0022]
Then, a signal for fixing the transfer direction of the address signal on the address buses 20a and 20b is output from the recognized stack position to the buffer 17, and the transfer direction of the data signal on the data bus 21 from the stack position is read and written. Set accordingly. This controls the buffer 18 according to reading or writing when a data signal is transferred to the expansion board 11. Also, the address assigned to the expansion board 11 is selected from the stacking position, and when the address signal transferred from the CPU board 1 is input, it is determined whether it is its own address. The gate array 19 is selected based on the above.
[0023]
36 is a PLD formed by hardware constituting the functions of the stack position recognition unit, ID code generation unit, signal transfer direction setting unit, address decoding unit and gate array selection unit according to the present invention, as described above. A plurality of pins (not shown) connected to the address buses 40a and 40b and the data bus 41 laid on the buffer, a plurality of pins connected to the buffers 37 and 38 and the gate arrays 39 via respective conductors on the substrate. (Not shown), two mode pins 43 connected to the first extension connector 32 through conductors, and one ID pin 44 and the like.
[0024]
The address bus 40a is connected to the first extension connector 32, the address bus 40b is connected to the buffer 37 connected to the second extension connector 33, and the data bus 41 branches off to the first extension connector 32. Are connected to the buffer 38 connected to the second expansion connector 33 and to each gate array 39.
[0025]
When the first expansion connector 32 is not connected to any of the two mode pins 43, the potential (high level) generated by the expansion board 31 is applied to the two mode pins 43. When 32 is connected to the first expansion connector 12 of the input / output expansion board 11, the potential becomes high level and low level. This is because one of the two mode pins 43 is connected to the mode pin 23 on the input / output expansion board 11 side that is at the high level, and the other pin is the input / output expansion. This is because the pin on the first extension connector 12 side of the board 11 is connected to the ground.
[0026]
The ID pin 44 described above is for causing the PLD 36 to generate an ID code in the same manner as described above. In the input expansion board 31, a preset low level potential is applied to the ID pin 44. ing.
[0027]
The PLD 36 of the input expansion board 31 recognizes that the two mode pins 43 are stacked when the potential of the two mode pins 43 is high, and one of the two mode pins 23 is When the high level and the other pin are at the low level, it is recognized that the third layer is stacked, and when a low level potential is applied to the ID pin 44, a preset ID code (for example, 2Ah) is generated. .
[0028]
Then, a signal for fixing the transfer direction of the address signal on the address buses 40a and 40b is output from the recognized stack position to the buffer 37, and the transfer direction of the data signal on the data bus 41 from the stack position is set at the time of reading and writing. Set accordingly. In this case as well, when a data signal is transferred to the expansion board 31, the buffer 38 is controlled according to read or write. Also, the address assigned to the expansion board 31 is selected from the stacking position, and when the address signal transferred from the CPU board 1 is input, it is determined whether it is its own address. The gate array 39 is selected based on the above.
[0029]
Here, the operation of the PLD and the processing on the CPU board side when each expansion board is stacked on the CPU board and the power is turned on as shown in FIG. 1 will be described.
As shown in FIG. 1, when the expansion boards 11 and 31 are stacked on the CPU board 1 and are connected continuously and applied with power, each mode pin 23 of the PLD 16 of the first-stage input / output expansion board 11 is provided. Becomes a low level, a high level potential is applied to the ID pin 24, the potential of each mode pin 23 of the PLD 16 of the second stage I / O expansion board 11 becomes a high level, and the ID pin 24 is high. The potential of the level is applied, the potential of each mode pin 43 of the PLD 36 of the input expansion board 31 at the third stage becomes the high level and the low level, and the low level potential is applied to the ID pin 44.
[0030]
At this time, the first-stage PLD 16 recognizes that it is stacked in the first stage based on the potential (low level) of the two mode pins 23 and generates an ID code (D5h). Then, a signal for fixing the transfer direction of the address signal on the address buses 20a and 20b is output from the recognized stack position to the buffer 17, and the transfer direction of the data signal on the data bus 21 from the stack position is read and written. The address assigned to the expansion board 11 is selected from the stacking position.
[0031]
The second-stage PLD 16 recognizes that the second-stage PLD 16 is stacked on the second-stage based on the potential (high level) of the two mode pins 23 and generates the same ID code (D5h) as described above. Then, a signal for fixing the transfer direction of the address signal on the address buses 20a and 20b is output from the recognized stack position to the buffer 17, and the transfer direction of the data signal on the data bus 21 from the stack position is read and written. The address assigned to the expansion board 11 is selected from the stacking position.
[0032]
Further, the third-stage PLD 36 recognizes that the third-stage PLD 36 is stacked on the basis of the potentials (high level and low level) of the two mode pins 43 and generates an ID code (2Ah). Then, a signal for fixing the transfer direction of the address signals on the address buses 40a and 40b is output from the recognized stack position to the buffer 37, and the transfer direction of the data signal on the data bus 41 from the stack position is read and written. The address assigned to the expansion board 31 is selected from the stacking position.
[0033]
On the other hand, the CPU of the CPU board 1 sequentially writes the ID codes (D5h, 2Ah) of the expansion boards 11 and 31 in the memory based on the stacking positions recognized by the PLDs 16 and 36.
[0034]
Regarding the transfer direction of the address signal and the transfer direction at the time of reading and writing the data signal, in the first-stage input / output expansion board 11, the transfer direction of the address signal is the first expansion connector 12 → PLD 16 → The buffer 17 is changed to the second extension connector 13, and the transfer direction of the data signal at the time of reading is changed from the second extension connector 13 to the buffer 18 to the first extension connector 12, and the transfer direction of the data signal at the time of writing is changed. This is the reverse of the transfer direction when reading.
[0035]
In the second input / output expansion board 11, the transfer direction of the address signal is second expansion connector 13 → buffer 17 → PLD 16 → first expansion connector 12, and the transfer direction of the data signal at the time of reading is the first. 1 extension connector 12 → buffer 18 → second extension connector 13, and the transfer direction of the data signal at the time of writing is opposite to the transfer direction at the time of reading.
[0036]
In the third-stage input expansion board 31, the transfer direction of the address signal is first expansion connector 32 → PLD 36 → buffer 37 → second expansion connector 33, and the transfer direction of the data signal at the time of reading is the second. The extension connector 33 → the buffer 38 → the first extension connector 32, and the transfer direction of the data signal at the time of writing is opposite to the transfer direction at the time of reading.
[0037]
In the above description, an example in which up to three are stacked on the CPU board 1 is shown, but the number is not limited to this, and any number may be used. In this case, the number of mode pins 23 and 43 of each PLD 16 and 36 is three or more, and the number of ID pins 24 and 44 is two or more.
[0038]
Next, the operation of the CPU board at the time of initial setting before entering operation will be described based on FIG. 6, FIG. 7 and FIG. 6, 7 and 8 are flowcharts showing the operation of the CPU board at the time of initial setting before the operation is started. As shown in FIG. 1, three expansion boards 11 and 31 are stacked on the CPU board 1, and the ID codes of the expansion boards are stored in the memory in the stacking order.
[0039]
First, the CPU of the CPU board 1 determines whether or not power is normally applied to the CPU board main body and the stacked expansion boards 11 and 31 by means of power supply voltage detection means (not shown) provided in the expansion boards 11 and 31. (S1). When the power supply is abnormal, this is displayed and the operation is prohibited (S2, S3). When the power supply is normal, the memory is accessed and the ID code of the expansion board stacked in the first stage is read (S4). Then, it is determined whether the parity is an odd number (S5).
[0040]
When the parity is an even number, it is determined that the code is not used when it is abnormal (S6). When the code is not used, it is determined that the expansion board is not stacked (S7). It is determined whether it has been repeated three times (S8). When it has not been repeated three times, reading of the ID code is started (S4), but when it has been repeated three times, operation is started with only the CPU board 1 (S9). If it is determined in S6 that the code is not unused, it is determined whether or not the parity check has been repeated three times (S10). If not repeated three times, the process returns to S4 in the same manner as described above, but repeated three times. If the ID code is abnormal, the operation is prohibited (S11, S12).
[0041]
When the parity of the ID code read first is an odd number, it is determined as normal and it is determined whether the ID code is D5h (S13). If the ID code is not D5h, it is determined whether or not this determination has been repeated three times (S15). If it has not been repeated three times, the process returns to S4 as described above. Is prohibited (S16). When the ID code is D5h, it is recognized as the input / output expansion board 11 (S14), and the memory allocation operation is executed according to the number of input points and output points of that type.
[0042]
Next, the second ID code is read (S17), and it is determined whether the parity is an odd number (S18). When the parity is an even number, it is determined that the code is not used and the code is not used (S19), as described above. If the code is not used, the expansion board is not stacked on the second level. It is determined (S20), and it is determined whether this determination is repeated three times (S21). If it has not been repeated three times, the second ID code is read again (S17), but if it has been repeated three times, it is determined that only the input / output expansion board 11 is laminated (S22, S23). If it is determined in S19 that the code is not an unused code, it is determined whether or not the parity check has been repeated three times (S24). If it has not been repeated three times, the process returns to S17 as described above, but repeated three times. If the ID code is abnormal, the operation is prohibited by displaying that the ID code is abnormal (S25, S26).
[0043]
When the parity of the second ID code read is odd, it is determined that the ID code is D5h (S27). When the ID code is D5h, it is recognized as the input / output expansion board 11 (S28), and the memory allocation operation is executed in accordance with the number of input points and the number of output points in the same manner as described above. If the ID code is not D5h, it is determined whether it is 2Ah (S29). If the ID code is 2Ah, it is recognized as the input expansion board 31 (S30), and the memory allocation operation is executed according to the number of input points. . If the ID code is none, it is determined whether the confirmation has been repeated three times (S31). If the ID code has not been repeated three times, the process returns to S17 in the same manner as described above. Driving is prohibited as a thing (S32).
[0044]
When the confirmation of the type of the expansion board at the second stage is completed, the third ID code is read to determine whether the parity is an odd number as described above (S33, S34). When the parity is an even number, it is determined that the code is abnormal and it is determined whether the code is not used (S35). If the code is not used, it is determined that the expansion board is not stacked in the third stage (S36). It is determined whether this determination has been repeated three times (S37). If it is not repeated three times, the third ID code is read again (S33). If it is repeated three times, it is determined that the input / output and input expansion boards 11 and 31 are stacked, and the operation is started. Enter (S38, S39). If it is determined in S35 that the code is not an unused code, it is determined whether or not the parity check has been repeated three times (S40). If not repeated three times, the process returns to S33 in the same manner as described above but repeated three times. If the ID code is abnormal, the operation is prohibited (S41, S42).
[0045]
When the parity of the third ID code read is odd, it is determined as normal and it is determined whether or not the ID code is 2Ah (S43). When the ID code is 2Ah, it is recognized as the input expansion board 31 (S44), and in the same manner as described above, the memory allocation operation is executed according to the number of input points of that type and the operation is started (S45). If the ID code is not 2Ah, it is determined whether the confirmation has been repeated three times (S46). If the ID code has not been repeated three times, the process returns to S33 in the same manner as described above. Driving is prohibited (S47).
[0046]
As described above, in the present embodiment, each PLD recognizes the stack position based on the potential of each mode pin, generates an ID code, and generates an address signal on the address bus from the recognized stack position. A signal that fixes the transfer direction is output to each buffer, and the transfer direction of the data signal on the data bus from the stack position is set according to read and write, and assigned to each expansion board from the stack position The CPU board side sequentially writes the ID code of each expansion board into the memory based on the stack position recognized by each PLD, and then recognizes the type of each expansion board from the ID code. In addition, based on the number of control points of the recognized type of expansion board, the memory allocation work is executed and the operation is started. This eliminates the need for the motherboard that was required in the past, which reduces the number of parts and reduces the cost, and also eliminates the need for the motherboard as described above. There is no need to form a box in the form of a box, and a programmable controller having a small size can be provided.
[0047]
【The invention's effect】
As described above, according to the present invention, the expansion board recognizes the stacking position based on the potentials applied to the plurality of mode pins, generates a preset ID code, and starts addressing from the stacking position. Sets the transfer direction of the address signal on the bus, sets the transfer direction of the data signal on the data bus from the stack position according to the time of reading and writing, and further assigns the address to itself based on the stack position When the address signal transferred from the control board is input, it is determined whether it is its own address, and when it is the selected address, the I / O gate array is selected based on the address, and The control board side stores the expansion board ID code in the memory based on the stacking position, and then recognizes the expansion board type from the ID code. Since the memory allocation work is executed based on the number of control points of the recognized type of expansion board, the previously required motherboard is no longer required, which reduces the number of parts and makes it cheaper in terms of cost. In addition, since the mother board is no longer necessary as described above, there is no need to form each module in a box shape as in the prior art, and there is an effect that a small-sized programmable controller can be provided.
[Brief description of the drawings]
FIG. 1 is an external view of a programmable controller according to an embodiment of the present invention.
FIG. 2 is a plan view of an input / output expansion board.
FIG. 3 is a plan view of an input expansion board.
FIG. 4 is a block diagram showing a circuit configuration of an input / output expansion board.
FIG. 5 is a block diagram showing a circuit configuration of an input expansion board.
FIG. 6 is a flowchart showing the operation of the CPU board at the time of initial setting before entering operation.
FIG. 7 is a flowchart showing the operation of the CPU board following FIG. 6;
FIG. 8 is a flowchart showing the operation of the CPU board following FIG.
[Explanation of symbols]
1 CPU board, 2 expansion connector, 11 I / O expansion board,
12, 32 1st expansion connector, 13, 33 2nd expansion connector,
31 Input expansion board, 16, 36 Programmable logic devices,
51 Spacer, 52 Dedicated cable.

Claims (3)

A programmable controller in which one or a plurality of expansion boards to which various devices to be controlled are connected are stacked on the control board and connected to the series,
The expansion board has a plurality of mode pins to which a potential corresponding to a connection position is applied, a stack position recognition unit that recognizes a stack position based on the potential applied to the plurality of mode pins, and an ID code An ID code generation unit for generating
The control board stores the ID code of the expansion board in the memory based on the stacking position, and then recognizes the type of the expansion board from the ID code, and based on the control points of the recognized type of expansion board A programmable controller comprising an expansion board discrimination unit for executing a memory allocation operation. The potential of each mode pin of the stacking position recognition unit is given by the control board or the upper or lower expansion board depending on the stacking position of the expansion board, and in the lowermost expansion board where no expansion board exists in the lower stage 2. The programmable controller according to claim 1, wherein a potential generated in the expansion board is applied. The expansion board is connected to an address bus, a data bus, and a data bus, and includes a plurality of I / O gate arrays provided in accordance with the number of control points of various devices to be controlled. In addition to setting the transfer direction of the address signal, the signal transfer direction setting unit for setting the transfer direction of the data signal on the data bus from the stack position according to the time of reading and writing, and corresponding to the expansion board to be stacked in advance An address decoding unit that has a set address and selects an address based on the stacking position; and when an address signal transferred from the control board is input via an address bus, the address decoding unit selects the address A gate that selects an I / O gate array based on the selected address. The programmable controller according to claim 1 or 2, characterized in that it has a ray selection unit.

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