JP4257232B2 - Defective chip marking method and defective chip marking apparatus - Google Patents

Description

  The present invention relates to a defective chip marking method and a defective chip marking apparatus, and more specifically, a defective chip marking method and a defective chip marking apparatus for printing a defective mark on a defective chip on a semiconductor wafer determined by inspection of electrical characteristics of a semiconductor chip. About.

  Conventionally, defective marks are printed on defective chips on a semiconductor wafer by measuring the electrical characteristics of each chip using a semiconductor chip inspection apparatus composed of a prober, an LSI tester, and the like to inspect the non-defective / defective products. Later, it has been performed through defective marking means provided in the same semiconductor chip inspection apparatus, but recently, it has been performed by a dedicated marking apparatus separated from the semiconductor chip inspection apparatus. This is because the LSI tester or prober constituting the semiconductor chip inspection apparatus has become expensive with the recent increase in functionality or systemization of LSI products, and the running cost of the semiconductor chip inspection apparatus has increased. By separating the defective marking means from the semiconductor chip inspection device in this way, the semiconductor chip inspection device is operated only for the inspection of the non-defective product / defective product, its operating efficiency is improved, and its productivity is improved. The semiconductor wafer that has undergone the defective chip marking process is diced, and only good chips are sent to the assembly and mounting process to become LSI products.

  In the conventional defective chip marking method using the dedicated marking device described above, the MAP data converted into electronic information in the semiconductor chip inspection device, for example, non-defective / defective product data on the semiconductor wafer, position coordinate data of the defective chip, each chip The defect mark is printed on the defective chip on the semiconductor wafer based on the quality data.

  FIG. 6 is a schematic perspective view for illustrating a conventional defective chip marking method, and FIG. 7 is a plan view of a semiconductor wafer for explaining the defective chip marking method in more detail. As shown in FIG. 6, the semiconductor wafer 102 is placed on the suction table 101. Here, a large number of semiconductor chips 103 are formed on the semiconductor wafer 102. The suction table 101 sequentially moves in the X and Y directions of the arrows in the figure, and based on the MAP data described above, the defective chip is defective with the marker 104 only when it reaches the coordinate position of the defective chip. Mark 105 is marked. The defective mark 105 is printed by scratching, ink dot printing, or recently by laser marking.

  In FIG. 7, the marker 104 is illustrated as moving and scanning on the semiconductor wafer 102. Actually, as described with reference to FIG. 6, the suction table 101 moves from the X direction to the Y direction. In FIG. 7, the scanning of the marker 104 is indicated by a one-dot chain line in the drawing due to the movement of the suction table 101. As shown in the drawing, starting from the semiconductor chip A at the end of the first row, raster scanning is sequentially performed up to the chip at the other end of the row to print the defect mark 105. If the row direction is the main direction and the direction perpendicular to the row direction is the slave direction, the scanning of all the semiconductor chips 103 in the above row and the printing of defective marks are completed, and the semiconductor chip in the next row is moved to the previous row. Raster scanning is performed sequentially from the end in the opposite main direction, and the rows scanned in the subordinate direction are changed while scanning and printing on the semiconductor chip alternately in the opposite direction in adjacent rows. All semiconductor chips are scanned and defective marks are printed.

  However, in such a defective chip marking method by raster scanning, the same movement as in the inspection of the semiconductor chip is necessary for the mark printing, and there is a problem that the time required for the defective chip marking process becomes long. In particular, this becomes more apparent when the semiconductor wafer has a large diameter of, for example, 300 mmφ.

Therefore, a printing method as shown in FIG. 8 has been proposed as a method for shortening the printing time of the defective mark (for example, see Patent Document 1). FIG. 8 is a schematic perspective view for illustrating a marking method using a plurality of markers. In this method, defective marks are simultaneously printed with a plurality of markers. As shown in FIG. 8, a plurality of markers 104 arranged in the Y direction are supported by the support unit 106, and first, the first row of semiconductor chips 103 in the X direction of the semiconductor wafer 102 matches the arrangement of the markers 104. The suction table 101 is moved to the position to be moved. Then, the semiconductor wafer 102 is moved in the −X direction by the arrangement pitch distance of the semiconductor chips, and only the marker at the defective chip position is operated based on the MAP data information from the above-described semiconductor chip inspection apparatus, and a plurality of defect marks 105 are operated. Are printed at the same time. Then, this operation is sequentially repeated, and defective marks are printed on defective chips on all semiconductor chips.
JP-A-1-165135 (FIG. 1)

  Certainly, according to the defective chip marking method using the plurality of arranged markers, the time required for the defective chip marking process is shortened compared to the defective chip marking method by the raster scan described above. However, in this case, a mechanical mechanism for simultaneously printing a plurality of defective marks on the dedicated marking device is required, and the marking device becomes expensive. Moreover, new software for driving the mechanical mechanism is required. For these reasons, the running cost of the marking device is greatly increased, and the defective chip marking process using the dedicated marking device is expensive.

  In addition, when marking various types of LSI products with the same marking device, the size of the semiconductor chip varies depending on the LSI product, so the interval between multiple markers must be changed accordingly. Disappear. This flexible change of the marker interval requires a more advanced mechanical mechanism of the marker and its driving mechanism. For this reason, there is a problem that it is difficult to perform a marking process on a wide variety of LSI products with an inexpensive marking device.

  Further, in the case of scratching or ink hitting, it is essential to adjust the height of the nozzles of a plurality of markers so that they are uniform with high precision, and the operation and management of the marking device becomes complicated. was there. Furthermore, since there is a mechanical limit in reducing the marker interval, there is a problem that if the size of the semiconductor chip is reduced, it cannot be dealt with.

  The present invention has been made in view of the above-described circumstances, and can achieve high-speed, low-cost, and simplified marking processing of defective chips, and enables flexible and quick response to a wide variety of LSI products. An object of the present invention is to provide a defective chip marking method and a defective chip marking apparatus.

  In order to solve the above-mentioned problem, the invention according to claim 1 is directed to the total number or predetermined number of semiconductor chips which are two-dimensionally arranged on a semiconductor wafer along two directions perpendicular to each other and divided into rectangles. A defective chip marking method for printing a defective mark on a defective chip determined as a defective product as a result of characteristic inspection, wherein a distribution state of defective chips determined as defective products in the electrical characteristic inspection on the semiconductor wafer After performing the clustering process for collecting adjacent defective chips as defective blocks, random scanning is performed between the defective blocks, and the defective mark is printed.

  The invention according to claim 2 relates to the defect marking method according to claim 1, wherein a defect mark is printed on the total number of the defective chips belonging to one defective block, and then the shortest distance from the one defective block. It is characterized in that a defective mark is printed on the total number of the defective chips belonging to the other defective block by randomly scanning to another defective block located.

  The invention according to claim 3 relates to the defective chip marking method according to claim 1, and is based on coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the step of inspecting the electrical characteristics of the semiconductor chip. One defective chip has one side in common and the adjacent defective chips are extracted, and then extracted in this manner, at least one arbitrary defective chip in the group of consecutive defective chips has one side in common The method is characterized in that adjacent defective chips are extracted and the defective chips are clustered.

  According to a fourth aspect of the present invention, there is provided the defective chip marking method according to the third aspect, wherein one defective chip on the semiconductor wafer is determined based on the coordinate data of the defective chip converted to electronic information on the semiconductor wafer. A two-dimensional search is performed as a clustering starting point, and the defective chip clustering process is performed by sequentially extracting and additionally accumulating adjacent defective chips with one side as a common starting point. Yes.

  The invention according to claim 5 relates to the defective chip marking method according to claim 2, and based on the coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the step of inspecting the electrical characteristics of the semiconductor chip, The other defective block located at the shortest distance from the one defective block on the semiconductor wafer is obtained.

  The invention described in claim 6 relates to the defective chip marking method according to claim 5, wherein the coordinates of the defective chip added last in the clustering to form the one defective block and the other defective blocks are added. The distance from the defective chip coordinate serving as the clustering start point is calculated, and the other defective block at the shortest distance from the one defective block is obtained.

  According to the seventh aspect of the present invention, as a result of the electrical characteristic inspection on the total number or predetermined number of semiconductor chips that are two-dimensionally arranged on the semiconductor wafer along two directions perpendicular to each other and divided into rectangles, A defective chip marking device for printing a defective mark on a defective chip determined to be a non-defective product, the printing means for printing the defective mark, and the semiconductor wafer of the defective chip determined to be defective by the electrical characteristic inspection A clustering unit that examines the distribution state above and collects adjacent defective chips as defective blocks; and a printing control unit that randomly scans between defective blocks and causes the printing unit to print the defective mark. It is characterized by.

  The invention according to claim 8 relates to the defective chip marking device according to claim 7, wherein the printing control means controls the driving of the printing means so that the total number of the defective chips belonging to one defective block is controlled. A defective mark is printed, and then randomly scanned from the one defective block to another defective block located at the shortest distance, and a defective mark is printed on the total number of the defective chips belonging to the other defective block. It is characterized by that.

  A ninth aspect of the invention relates to the defective chip marking device according to the seventh aspect, wherein the clustering means coordinates the defective chips converted into electronic information in the process of inspecting the electrical characteristics of the semiconductor chips on the semiconductor wafer. Based on the data, an adjacent defective chip is extracted with one side common to any one defective chip, and then extracted into at least one arbitrary defective chip in the group of defective chips connected in this way. The method is characterized in that adjacent defective chips are extracted with one side in common and the defective chips are clustered.

  According to a tenth aspect of the present invention, in the defective chip marking device according to the ninth aspect, the clustering unit is configured on the semiconductor wafer based on the coordinate data of the defective chips converted to electronic information on the semiconductor wafer. Two-dimensional search using one defective chip as the starting point of clustering, and extracting adjacent defective chips sequentially with one side as a common starting point from the one defective chip, and adding and cumulatively clustering the defective chips It is characterized by performing.

  An eleventh aspect of the invention relates to the defective chip marking device according to the eighth aspect, wherein the print control means coordinates coordinates of the defective chip converted into electronic information in the process of inspecting the electrical characteristics of the semiconductor chip on the semiconductor wafer. Based on the data, the other defective block in the shortest distance from the one defective block on the semiconductor wafer is obtained.

  According to a twelfth aspect of the present invention, there is provided the defective chip marking device according to the eleventh aspect, wherein the print control means includes the coordinates of the defective chip added last in the clustering for forming the one defective block. The distance from the defective chip coordinate serving as the starting point of the clustering of the other defective block is calculated, and the other defective block at the shortest distance from the one defective block is obtained.

  According to the configuration of the present invention, the marking process for defective chips is accelerated, and the time required for this processing step is significantly reduced. Further, the process of marking a defective chip becomes simple, and the cost reduction becomes extremely easy. In addition, it is possible to freely and quickly cope with semiconductor products of a wide variety of LSI products (or a small amount of LSI products).

  For defective chips that are determined to be defective as a result of an electrical characteristic inspection on the total number or predetermined number of semiconductor chips that are two-dimensionally arranged on a semiconductor wafer along two directions perpendicular to each other and that are divided into rectangles In the defective chip marking that prints the defective mark, the clustering processing means in the central processing unit of the defective chip marking device examines the distribution state of the defective chips determined to be defective in the electrical characteristic inspection on the semiconductor wafer, A clustering process is performed in which adjacent defective chips are grouped as defective blocks. Under the command of the central processing unit, the defective blocks are randomly scanned between the defective blocks using the printing control unit and the printing unit of the same apparatus. By printing, the marking process of defective chips is accelerated, the processing time is greatly reduced, and It was achieved simplification and cost reduction of the process steps. Here, the random scan is a scan in an arbitrary direction that does not have regularity like the raster scan, although the details will be clarified in the embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor wafer for explaining a defective chip marking method according to an embodiment of the present invention. FIGS. 2 to 5 illustrate processing and procedures in the defective chip marking method or apparatus. FIG.

  As shown in FIG. 1, a large number of semiconductor chips 2 that are the same product are arranged on a semiconductor wafer 1. Here, in the same manner as described with reference to FIG. 7 in the prior art, it is illustrated as if the marker moves and scans on the semiconductor wafer 1, but the marker is actually fixed as described with reference to FIG. 6. The semiconductor wafer 1 placed on a suction table or the like moves and scans. In the following description, for the sake of simplicity, it is assumed that the marker moves and scans on the semiconductor wafer 1.

  First, starting from the semiconductor chip A at the end of the first row of the semiconductor wafer 1, the marker (not shown) has a minimum (shortest distance) position coordinate distance from the semiconductor chip A on the semiconductor wafer 1. It moves to the starting point chip 3a of the first defective block 3 to become. Then, the marker prints the defect mark 4 on all the defective chips existing in the first defective block 3, and moves to the end point chip 3b. The printing of defective marks in the first defective block 3 is performed in a predetermined order (described later).

  Subsequently, the marker moves to the second defective block 5 where the distance of the position coordinates from the end point chip 3b of the first defective block 3 is the minimum (shortest distance) and similarly prints the defective mark. FIG. 1 shows the case where the defective block 5 has one defective chip.

  Thereafter, the same procedure as described above is used to move to each defective block on the semiconductor wafer 1 and print a defective mark on the defective chip therein. That is, from the second defective block 5 to the third defective block 6 having the shortest distance, from the third defective block 6 to the fourth defective block 7 having the shortest distance, and from the fourth defective block 7 to the fifth defective block 8 having the shortest distance. In the same manner, the sixth defective block 9 and the final seventh defective block 10 of the semiconductor wafer 1 are sequentially moved to print defective marks on defective chips in each defective block, and finally the semiconductor wafer. Defective marks are printed on all defective chips in 1. Although the path between the defective blocks will be described in detail later, the path between the two defective blocks is determined to be the shortest. Thus, the movement between defective blocks is not a raster scan as in the prior art, but a random scan.

  The defective block group on the semiconductor wafer 1, that is, the defective blocks 3 to 10, is a non-defective / non-defective product of all the semiconductor chips on the semiconductor wafer described above in a central processing unit (computer) provided in a dedicated defective chip marking device. It is formed by mathematical calculation according to a predetermined program in the calculation unit of the computer based on the position coordinate data of the defective chip of the MAP data converted into electronic information by the non-defective product inspection. This becomes the clustering means of the defective chip marking device of the present invention. The calculation unit also calculates the shortest distance between each defective block at the same time. Formation of the defective block group and calculation of the shortest distance by the arithmetic unit described above are performed for each semiconductor wafer and stored in the storage unit of the computer. According to the present invention, the predetermined program described above is incorporated into a computer provided in a conventional dedicated marking device, whereby formation of a defective block group and calculation of the shortest distance between defective blocks can be easily performed. Here, the position coordinate of the semiconductor chip including the defective chip is a coordinate on a semiconductor wafer at a predetermined location (for example, a central portion, an end portion, etc.) of the semiconductor chip.

  Next, a method of forming a defective block by the above mathematical operation using clustering means will be described with reference to FIGS. In the present invention, the defective block group is formed by a system called chip link (additional accumulation) through clustering of all defective chips in the semiconductor wafer, which will be described later. Here, when there are a plurality of defective blocks formed on the semiconductor wafer 1, they are collectively referred to as a defective block group, and when there is only one defective block, it is simply referred to as a defective block.

  First, an example of the clustering of the defective chips will be described with reference to FIG. FIG. 2 is a plan view on a semiconductor wafer showing a clustering process for forming each defective block shown in FIG. The clustering means of the computer determines from the list of position coordinate data of the defective chip of the MAP data on the right side of the semiconductor wafer from the left side of the specific semiconductor wafer as shown in the search direction 11 shown in FIG. The position coordinates of defective chips are searched. The position coordinates of the defective chip first found by this search are set as the start point coordinates 12. When this starting point coordinate 12 is found, this is used as a starting point for forming a defective block, and adjacent defective chips are sequentially extracted, accumulated, and clustered.

  This clustering may be performed under a predetermined search rule determined as shown in FIG. As shown in FIG. 2 (b), for example, in the search direction 11 shown in the arrow direction, that is, from W0 to the left W1, the front W2, the right W3, and the rear W4 in the order of priority, the next next The coordinates of defective chips are searched. Then, when the next defective chip coordinate 13 shown in FIG. 2A is searched, the arrow direction from the start point coordinate 12 to the next defective chip coordinate 13 is set to W0 and again in the order of left, front, right, and rear. The next adjacent defective chip coordinates are searched in the priority order. By repeating this operation, finally, the end point coordinates 14 at which the adjacent defective chip coordinates cannot be found are reached. In this way, adjacent defective chips are clustered with one side in common. Then, the chip formed by such clustering is chip-linked, and this is assigned a defective block number like the defective block 15, and the first defective block 3 to the seventh defective block 10 shown in FIG. A defective block group is formed. Here, the defective chip adjacent to one side in common is specifically the side of the semiconductor chip adjacent to the scribe region between the semiconductor chips provided for dicing the semiconductor wafer described above. It is a chip.

  Next, a procedure for forming a defective block group of one semiconductor wafer will be described with reference to FIG. FIG. 3 is a flowchart showing a procedure for dividing defective chips on a semiconductor wafer and forming a defective block group. As shown in FIG. 3, for example, in a computer search system, the position coordinates (X, Y) = (1, 1) of the semiconductor chip of the target semiconductor wafer are set (step ST1). Next, the position coordinate data of the defective chip of the MAP data formed in the defect / non-defective product inspection process of the target semiconductor wafer is searched, and the start point coordinates as described in FIG. 2 are searched (step ST2). Then, the coordinates (X, Y) are reset to the start point coordinates (step ST3). Then, defective chips adjacent to each other are clustered and chip-linked by the method described with reference to FIG. 2 (step ST4). Then, a defective block number is given to the list of position coordinates of the chip-linked defective chip (step ST5).

  Next, the position coordinate of the chip-linked defective chip is deleted from the list of position coordinate data of the defective chip in the MAP data (step ST6). Next, it is determined whether or not the number of position coordinates of the semiconductor chip left after the deletion in the position coordinate data list of the defective chip in the MAP data is zero (step ST7). If not, the process proceeds to step ST2. . Then, returning to the coordinates (X, Y) again, the defective chip search of the MAP data is started, and the processing of the above-described steps ST2 to ST7 is performed. Further, the processing ends when the number of position coordinates of the semiconductor chip remaining after the deletion becomes zero (step ST8).

In this way, a defective block group as shown in FIG. 4 is formed. As shown in FIG. 4, a first defective block, a second defective block,... Nth defective block are formed, and a position coordinate list of chip-linked defective chips is formed in each defective block. For example, in the first defective block, the position coordinates of the chip-linked defective chips, (X ₁₁ , Y ₁₁ ), (X ₁₂ , Y ₁₂ ),..., (X _1a , Y _1a ) list are the second _ones . In the defective block, the position coordinates of the chip-linked defective chip, (X ₂₁ , Y ₂₁ ), (X ₂₂ , Y ₂₂ ),..., (X _2b , Y _2b ) list, and the nth defective block , (X _n1 , Y _n1 ), (X _n2 , Y _n2 ),..., (X _nc , Y _nc ) lists are formed. Here, (X ₁₁ , Y ₁₁ ), (X ₂₁ , Y ₂₁ ),..., (X _n1 , Y _n1 ) are the above-described start point coordinates of each defective block, and (X _1a , Y _1a ), ( _X2b , _Y2b ),..., ( _Xnc , _Ync ) are the end point coordinates of each defective block.

  Next, with reference to FIG. 5, in the defective block group of one semiconductor wafer as described above, the procedure for determining the path between the defective blocks performed in FIG. FIG. 5 is a flowchart showing a procedure for determining a path between defective blocks. As shown in FIG. 5, in the calculation unit, the position coordinates (X, Y) of the semiconductor chip of the target semiconductor wafer are set to (1, 1) (step ST9). Next, the actual distance on the semiconductor wafer between the above-described start point coordinates and coordinates (1, 1) of the defective block group of the target semiconductor wafer is calculated (step ST10). Since the actual dimensions of the semiconductor chip are known in advance by the semiconductor product, this calculation can be performed by simple mathematical operation processing. Next, a defective block having a minimum starting point coordinate is selected from the calculation of the actual distance (step ST11), an end point coordinate in the selected defective block is extracted, and the coordinate (X, Y) is set as the end point coordinate. (Step ST12).

  Next, the selected defective block is deleted from the defective block group of the one semiconductor wafer (step ST13). Next, it is determined whether or not the number of defective blocks remaining after the deletion in the defective block group of the one semiconductor wafer is zero (step ST14). If not, the process proceeds to step ST10 and the above-described steps are again performed. Processing from ST10 to ST14 is performed. Then, the process ends when the number of defective blocks remaining after the deletion becomes zero (step ST15).

  In this way, based on the calculation of the shortest distance between each defective block group and each defective block of each semiconductor wafer formed by mathematical calculation by a computer provided in the dedicated marking device, the marker of the printing means of the dedicated marking device Is scanned as described with reference to FIG. 1, and a defect mark is printed on a defective chip on the semiconductor wafer. Here, the printing unit has a marker and a marker driving unit as a basic structure, and the printing control unit drives and controls the suction table on which the semiconductor wafer is placed under the command from the computer described above. The drive part is controlled to print the defect mark as described above.

  Thus, according to the configuration of this embodiment, the time required to print a defective mark on a defective chip on one semiconductor wafer is, for example, 200 mmφ compared with the conventional raster scanning printing method. In the case of this semiconductor wafer, it is halved to ½. The shortening of the marking time of the defective mark on the defective chip becomes more remarkable as the diameter of the semiconductor wafer increases. In the simulation prediction, it is confirmed that the semiconductor wafer diameter is greatly reduced to 1/3 under certain conditions when the diameter of the semiconductor wafer is 300 mmφ.

  Further, according to the configuration of this embodiment, as described above, the semiconductor is obtained by mathematical calculation from the MAP data converted into electronic information by the semiconductor chip inspection apparatus in the inspection process of the non-defective product / defective product of the semiconductor chip. Based on the formation of defective blocks by clustering defective chips on the wafer and the determination of the path between each defective block, the conventional dedicated marking device prints defective marks on all defective chips on the semiconductor wafer. . As described above, since the marking method or the marking device uses software, there is no problem caused by the modification of the mechanical mechanism of the marking device as described in Patent Document 1.

  Specifically, in the above-described defective chip marking using a plurality of array markers, the dedicated marking device becomes expensive and the running cost of the device also increases. In some cases, as described above, new software is simply incorporated into an existing marking device, and the cost is greatly reduced.

  Further, according to the configuration of this embodiment, unlike the case of Patent Document 1, the size of the semiconductor chip of the LSI product can be changed on the software even when a variety of LSI products are marked with the same marking device. In addition, a variety of LSI products can be marked with an inexpensive marking device easily and freely.

  Further, in the case of Patent Document 1, there is a problem that the operation and management of the marking device becomes complicated when the defect mark printing on the defective chip is a scratch or ink dot, and the size of the semiconductor chip is small. In this case, the distance between the markers is limited and cannot be handled. However, according to the configuration of this embodiment, since one marker can sufficiently cope with the operation, the operation and management of the marking apparatus are performed. Becomes very simple, and can sufficiently cope with the reduction of the semiconductor chip size.

  In the above-described embodiment, a case where rectangular semiconductor chips that are the same semiconductor product are arranged on a semiconductor wafer has been described. The present invention is not limited to such a case. The present invention can be similarly applied to a case where a plurality of types of products such as custom products are manufactured and arranged on the same semiconductor wafer. Here, after measuring only the electrical characteristics of the semiconductor chip of the same product among a plurality of types of semiconductor chips on the semiconductor wafer and inspecting the non-defective product / defective product of the same product, the present invention is applied to A defect mark may be printed on a defective chip of the product.

  Further, the clustering of defective chips according to the present invention is not limited to following the search rule for the position coordinates of defective chips as described in FIG. The clustering may be performed by searching for defective chips in accordance with the priority order of right, front, left, and rear in the search direction and their chip links. In any case, adjacent defective chips may be searched using a predetermined search rule.

  Further, the present invention is not limited to the order of the chip links in the order of printing of the defective marks in the defective block, and the defective chip is arranged so that the marker path in the same defective block is the shortest. A defect mark may be printed. In this case, it is necessary to derive the shortest path in the defective block by the computer search system described above.

  In the above embodiment, as a method for obtaining a defective block located at the shortest distance from one defective block, the end point coordinate of one defective block and the start point coordinate of another defective block are the shortest. However, the present invention is not limited to this method. As described above, it is determined that the position coordinates of the defective chip that is the final in the method of printing the defective mark that minimizes the marker path in the defective block and the start point coordinates of the other defective blocks are the shortest. You may do it.

  Further, in the present invention, the above-described path determination may be performed so that the marker path over all of the defective block groups on the semiconductor wafer becomes the shortest. It is also a random scan that moves between defective blocks along such a path. In this case, it is necessary to derive the shortest path passing through all the defective block groups by the above-described arithmetic unit. For this reason, the mathematical calculation by the calculation unit is complicated and the simulation cost is slightly higher than in the case of the above-described embodiment, but the cost required for the defective chip marking processing step is reduced as compared with the case of the conventional technique described above. To do.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and design changes and the like within a scope not departing from the gist of the present invention are possible. Even if it exists, it is included in this invention. For example, the arithmetic unit described above is not provided in the defective marking device, but is provided in the semiconductor chip inspection device, and the marker of the defective marking device is based on the result data mathematically calculated by the arithmetic unit. It is also possible to scan the top and print a defective mark.

It is a top view of the semiconductor wafer which shows the defective chip marking method which is one Example of this invention. It is a partial enlarged plan view of a semiconductor wafer showing clustering of defective blocks in the defective chip marking method. It is a flowchart which shows the defective block formation in the same defective chip marking method. It is a figure which shows the defective block group in the same defective chip marking method. It is a flowchart which shows the path | route determination between the defective blocks in the same defective chip marking method. It is a schematic perspective view which shows the structure of the marking apparatus of a prior art. It is a top view of the semiconductor wafer which shows the marking method of the technique. It is a schematic perspective view which shows the structure of the marking apparatus of another prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip 3 1st defective block 3a Start point chip 3b End point chip 4 Defect mark 5 2nd defective block 6 3rd defective block 7 4th defective block 8 5th defective block 9 6th defective block 10 7th defective block 11 Search direction 12 Start point coordinate 13 Next defective chip coordinate 14 End point coordinate 15 Defective block

Claims (12)

For defective chips that are determined to be defective as a result of an electrical characteristic inspection on the total number or predetermined number of semiconductor chips that are two-dimensionally arranged on a semiconductor wafer along two directions perpendicular to each other and that are divided into rectangles A defective chip marking method for printing a defective mark,
After examining the distribution state of defective chips determined as defective products in the electrical characteristic inspection on the semiconductor wafer, and performing a clustering process to group adjacent defective chips as defective blocks, randomly scan between defective blocks The defective chip marking method, wherein the defective mark is printed.   A defect mark is printed on the total number of the defective chips belonging to one defective block, and then randomly scanned to another defective block located at the shortest distance from the one defective block to belong to the other defective block. 2. The defective chip marking method according to claim 1, wherein a defective mark is printed on the total number of defective chips.   Based on the coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the process of inspecting the electrical characteristics of the semiconductor chip, the adjacent defective chip is extracted by making one side common to any one defective chip, Next, the defective chips are clustered by extracting adjacent defective chips with at least one arbitrary defective chip in the group of defective chips that are extracted in this way and having one side in common. The defective chip marking method according to claim 1.   Based on the coordinate data of the defective chip converted to electronic information on the semiconductor wafer, one defective chip on the semiconductor wafer is two-dimensionally searched as the starting point of the clustering, and the one defective chip is used as the starting point. 4. The defective chip marking method according to claim 3, wherein adjacent defective chips are sequentially extracted and added and accumulated to perform clustering processing of the defective chips.   Based on the coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the step of inspecting the electrical characteristics of the semiconductor chip, the other defective block at the shortest distance from the one defective block on the semiconductor wafer 3. The defective chip marking method according to claim 2, wherein the defective chip marking method is obtained.   Calculating the distance between the coordinates of the defective chip added last in the clustering to form the one defective block and the coordinates of the defective chip serving as the starting point of the clustering of the other defective blocks; 6. The defective chip marking method according to claim 5, wherein the other defective block located at the shortest distance from one defective block is obtained. For defective chips that are determined to be defective as a result of an electrical characteristic inspection on the total number or predetermined number of semiconductor chips that are two-dimensionally arranged on a semiconductor wafer along two directions perpendicular to each other and that are divided into rectangles A defective chip marking device for printing a defective mark,
Printing means for printing a defect mark;
Clustering means for examining a distribution state on the semiconductor wafer of defective chips determined to be defective by the electrical characteristic inspection, and collecting adjacent defective chips as defective blocks;
A defective chip marking device comprising: a printing control unit that randomly scans between defective blocks and causes the printing unit to print the defective mark.   The printing control unit controls the driving of the printing unit to print a defective mark on the total number of the defective chips belonging to one defective block, and then, the other is located at the shortest distance from the one defective block. 8. The defective chip marking device according to claim 7, wherein a defective mark is printed on all of the defective chips belonging to the other defective block by randomly scanning the defective block.   The clustering means is adjacent to any one defective chip in common on one side based on the coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the process of inspecting the electrical characteristics of the semiconductor chip. A defective chip is extracted, and then, by extracting at least one arbitrary defective chip in the group of defective chips connected in this manner, a defective chip adjacent to each other is extracted in common. 8. The defective chip marking device according to claim 7, wherein clustering processing is performed.   The clustering means performs a two-dimensional search for one defective chip on the semiconductor wafer as a starting point of the clustering based on the coordinate data of the defective chip converted to electronic information on the semiconductor wafer, and the one defective 10. The defective chip marking device according to claim 9, wherein the defective chips are clustered by sequentially extracting and additionally accumulating defective chips adjacent to each other starting from a chip as a starting point.   The printing control means is at the shortest distance from the one defective block on the semiconductor wafer based on the coordinate data on the semiconductor wafer of the defective chip converted into electronic information in the process of inspecting the electrical characteristics of the semiconductor chip. 9. The defective chip marking device according to claim 8, wherein the other defective block is obtained. The print control unit is configured to provide a distance between the coordinates of the defective chip added last in the clustering for forming the one defective block and the coordinates of the defective chip serving as a starting point of the clustering of the other defective blocks. The defective chip marking device according to claim 11, wherein the other defective block located at the shortest distance from the one defective block is calculated.

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