JP4283373B2 - Security system that can detect unauthorized modification of gaming machines - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the security of a microcomputer for controlling a gaming machine mounted on a board used for controlling these gaming machines (hereinafter referred to as a gaming machine control board), such as a pachinko gaming machine, an arrangement-type pachinko gaming machine, and a revolving gaming machine. The present invention relates to a security system that belongs to the field of systems and detects unauthorized modification of a gaming machine carried into an actual amusement park after passing a type test.
[0002]
[Prior art]
In the current gaming machine, the control CPU is periodically reset and 1 is added to the internal counter at that timing to make a lottery counter. The lottery.
[0003]
[Problems to be solved by the invention]
Therefore, it is only necessary to analyze the program to know the timing of the lottery lottery and to generate a start winning signal from the outside at that timing. By using this, an illegal operation is performed in which a “hanging” circuit for inputting an illegal prize signal from the outside is attached to the prize sensor and the prize signal is intentionally input to the control CPU.
Therefore, the present invention has been made in view of the drawbacks of the prior art, and in view of the fact that the impedance of the entire winning circuit is changed if a “hanging” circuit is attached to the CPU, the impedance status is reset at start-up. Measured at times, etc., and judged to be abnormal when the measured value was not within a predetermined range.
[0004]
[Means for Solving the Problems]
That is, the present invention relates to a user ROM storing a user program and a setting allowable range of an impedance value of a regular external circuit when a game machine manufacturer makes a model application, and a gaming machine capable of detecting unauthorized modification of the gaming machine control board. A CPU for controlling, an external terminal connected to an external circuit, and an input control means for realizing measurement of the impedance of the terminal at the time of “High level” or “Low level” applied to the input terminal; When the input of the comparison / control means for determining whether the impedance of the terminal is within the allowable range set by the gaming machine manufacturer and the system reset for initializing the entire gaming machine, And the setting allowable range 6 a written in the user ROM 6 is written in each setting register in the comparison / control means 5. A boot ROM7 the boot program is stored for performing the boot processing such as control of the write after impedance measurement, a work for RAM8 user program for controlling the operation of the gaming machine, consists RAM9 Prefecture for the boot program work,
The input control circuit converts an applied voltage of the external terminal into a digital value; an input control circuit for identifying whether the applied voltage of the external terminal is “High level” or “Low level”; A measurement trigger control circuit that transmits a select signal to the comparison / control means based on whether the output value of the A / D converter is "High level" or "Low level" based on the output value of the input control circuit And
The comparison / control unit is configured to store the upper and lower limit set values of “High level” and the upper and lower limit set values of “Low level” based on a select signal of the measurement trigger input control circuit; / D converter output value input and comparison with upper limit or lower limit value Upper limit value data comparator and lower limit value data comparator, and measurement trigger control for upper limit value data comparator and lower limit value data comparator Based on the select signal from the circuit, the upper limit setting value at the “High level” or the upper limit setting value at the “Low level” for the upper limit value data comparator, and the lower limit setting at the “High level” for the lower limit data comparator. Data multiplexer for switching and inputting the lower limit set value at the time or “Low level”, and the previous To achieve this purpose by the possible security systems detecting tamper of the game machine which is configured by an OR circuit for ORing the output data of the upper limit value data comparator and a lower limit value data comparator.
According to a second aspect of the present invention, the upper limit value data comparator and the lower limit value data comparator are such that the measured value “High level” is equal to or lower than the upper limit set value of the “High level” and equal to or higher than the lower limit value of the “High level”. It is determined whether the measured value “Low level” is less than or equal to the “Low level” upper limit set value and greater than or equal to the “Low level” lower limit set value, and both are cleared. A security system capable of detecting unauthorized modification of gaming machines that are configured to determine
[0005]
[Action]
In the security system according to the present invention, for example, at the beginning of powering on the gaming machine, that is, before starting impedance measurement of the measurement target external terminal (hereinafter referred to as terminal) of the gaming machine control microcomputer in the boot mode, The setting allowable range of the impedance value of the external circuit stored in the ROM is written to each setting register. Then, impedance measurement is started.
The measured impedance value of the terminal is digitally converted by the A / D converter and input to the upper limit value data comparator and the lower limit value data comparator. In addition, a set value of the allowable impedance allowable range of the terminal is input to one side of each of the above comparators, and it is diagnosed whether the measured impedance value of the terminal is within the allowable range at the H level and the L level. Will do. As a result, when it is not within the allowable range set by the gaming machine manufacturer side, that is, when it is determined that an illegal board or the like is connected to the outside, “1” is output from the OR circuit and the CPU is stopped or The determination result will be notified to the outside.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
In the following, the invention will be described in detail according to the illustrated embodiment.
FIG. 1 is a schematic block diagram of a security system according to the present invention. A gaming machine control board 1 for controlling a gaming machine has a gaming machine control micro that can detect unauthorized modification of the gaming machine control board 1. A computer 2 is mounted. The microcomputer 2 includes a CPU (central processing unit) 3, an input control unit 4, a comparison / control unit 5, a user ROM 6 in which a regular model application value 6 a and a user program are stored, and a boot ROM 7. User RAM 8 and boot RAM 9 are built in, and a security system is realized by the above-described configuration.
[0007]
The central processing unit 3 (CPU) controls each device incorporated in the gaming machine control microcomputer 2.
The input control means 4 performs control for realizing measurement of the impedance of the terminal 13 at the “High level” applied to the terminal 13 or at the “Low level”.
The comparison / control means 5 diagnoses whether or not the impedance of the terminal 13 is within an allowable range set by the gaming machine manufacturer side, and the result is a status display target external terminal 14 of the gaming machine control microcomputer 2 (hereinafter, referred to as the gaming machine manufacturer's microcomputer 2). Control for output to terminal 14) is performed.
The user ROM 6 is a read-only memory in which a normal type application value 6a created by the user and a user program for controlling the operation of the gaming machine and a security code are stored.
The boot ROM 7 determines whether or not the gaming machine control microcomputer 2 is legitimate (security check) when the power is turned on or when a system reset is input to initialize the entire gaming machine, and measurement of impedance at this time. This is a read-only memory in which a program (boot program) for setting data in the upper / lower limit value setting data register (5a / 5b / 5c / 5d) for executing the above control is stored. These upper limit / lower limit set values are written in the setting registers 5a to 5d by operating the boot program when the power is turned on.
The user RAM 8 is a work RAM for executing a user program for controlling the operation of the gaming machine.
The boot RAM 9 is a work RAM when executing a boot program that is not accessible in the user mode.
Reference numeral 10 denotes a general bus in which the address bus, data bus, control signal bus, and the like in the gaming machine control microcomputer 2 are integrated.
Reference numeral 11 denotes an internal signal connected from the terminal 13 to the input control means 4 and the comparison / control means 5.
An internal signal line 12 is output from the comparison / control means 5 to the terminal 14.
Reference numeral 15 denotes a model of an external circuit (for example, a winning sensor) showing a normal impedance that passes the type test applied to the terminal 13.
Reference numeral 16 denotes a “hanging circuit” model that indicates an illegal impedance that is increased or subtracted from the normal impedance by an unauthorized modification applied to the terminal 13.
[0008]
FIG. 2 is a schematic block diagram of the input control means 4 and the comparison / control means 5 according to the present invention.
The input control means 4 includes a measurement trigger control circuit 4a, an input control circuit 4b, and an A / D converter 4c. 4d indicates a control signal indicating a logic level output from the input control circuit 4b, and 4e indicates a control signal. A select signal for setting an allowable range when the impedance applied to the terminal 13 according to the logic level of the signal 4d is "High level" or "Low level". 4f is digitally converted by the A / D converter 4c 4g represents a register (hereinafter referred to as PDSR 4g) that stores the measured value data so that the CPU 3 can read the measured value data 4f.
The comparison / control means 5 includes a "High level" upper limit set value data register 5a (hereinafter referred to as HUDR 5a), a "Low level" upper limit set value data register 5b (hereinafter referred to as LUDR 5b), and a "High level" lower limit set value data register 5c ( Hereinafter, the upper limit value data multiplexer 5e (hereinafter, upper limit MUX5e), HLDR5c, or LLDR5d for switching data stored in the HLDR 5c), the “Low level” lower limit set value data register 5d (hereinafter, LLDR5d), HUDR5a, or LUDR5b. A lower limit value data multiplexer 5f (hereinafter referred to as a lower limit MUX5f) for switching stored data, an upper limit value data comparator 5g, a lower limit value data comparator 5h, a logical sum (OR) circuit 5i, and a status display control circuit 5j. Have
[0009]
Based on the logic level of the control signal 4d output from the input control circuit 4b, the measurement trigger control circuit 4a combines the predetermined control signals of the CPU 3 (for example, a read signal and a memory access signal) to measure impedance of the terminal 13. A select signal for setting an allowable range at the time of “Low level” or “High level” of the impedance applied to the terminal 13 is generated according to the trigger signal such as start start / stop and the logic level of the control signal 4d. The timing at which the CPU 3 recognizes whether the input level of the terminal 13 is “Low level” or “High level” is transmitted as a measurement trigger signal.
The input control circuit 4b is an amplifier circuit that amplifies the current flowing through the terminal 13 as a voltage, a terminating resistor for enabling impedance measurement, and the impedance measurement of the terminal 13 when the terminal 13 is at "High level" or "Low level". A built-in internal resistor (specifies pull-up / pull-down by control) for setting the level is recognized, the terminal 13 level is recognized as "Low level" or "High level", and a microcomputer for controlling a gaming machine 2 on the second bus (10) to inform the CPU 3.
The A / D converter 4c measures the impedance at the “High level” or “Low level” applied to the terminal 13, converts this amount into a digital value, and converts the upper limit value data comparator 5g and the lower limit value data comparator 5h. To supply.
The data stored in the HUDR 5a and the HLDR 5c is the allowable range of the normal impedance at the “High level” applied to the terminal 13 from the peripheral circuit of the gaming machine control board developed by the gaming machine manufacturer. The data stored in the LLDR 5d is the allowable range of the normal impedance at the “Low level”. These data are stored in the LUDR 5b and the LLDR 5d on the gaming machine manufacturer side because their values differ depending on the gaming machine development manufacturer.
These data are sent to one side of the upper limit value data comparator 5g and the lower limit value data comparator 5h, and are compared with the measured value data 4f digitally converted by the A / D converter 4c. ) Is output from the circuit 5i. That is, the control signal 10a indicating the determination result of whether or not the impedance applied to the terminal 13 is normal is sent to the CPU 3 via the bus 10, and when the determination result is not within the allowable range, for example, the CPU 3 is stopped. . The control signal 10a is also sent to the status display control circuit 5j, and the status display control circuit 5j performs status display control for notifying the determination result to the outside according to the logical value of the control signal 10a.
[0010]
With the configuration described above, the operation of the comparison / control means 5 of the present embodiment will be specifically described.
A / D converter 4c by the measurement data is converted as a digital value, but in its value, "High level" _{Z H} as that of the "Low level" ones _{Z L} is present.
Further, the “High level” upper limit set value UZ _H , the lower limit set value DZ _H and the “Low level” upper limit set value UZ _L and the lower limit set value DZ _L are stored in the user ROM 6 as permissible ranges for which the regular model application has been made. Based on the select signal of the measurement trigger control circuit 4a, when the measurement value is “High level”,
The upper limit data comparator 5g receives an upper limit set value UZ _H , and the lower limit value data comparator 5h receives a “High level” lower limit set value DZ _H to compare data, and the measured value is “Low level”. time,
Upper limit to the data comparator 5g upper limit set value UZ _L of "Low level" is input, the lower limit value data comparator 5h lower limit set value DZ _L of "Low level" is inputted comparison of data is performed.
As a result, the comparison circuits (comparators) 5g and 5h according to the present embodiment output the logical expressions A <B and A> B indicating the allowable ranges, respectively. As a result, when the “High level” is out of the allowable range, and when the “Low level” is out of the allowable range, “1” is output from the OR circuit 5i, and the “Low level” and “High level” are output. Only when “level” is “0”, it is determined to be a regular one.
[0011]
In this embodiment, the logic circuit is composed of an OR circuit. However, the present invention is not limited to this, and a logical expression of an upper limit value B ≦ A and a lower limit value B ≧ A is output. When the “High level” is within the allowable range, and when the “Low level” is within the allowable range, “1” may be output from the AND circuit.
[0012]
【The invention's effect】
As described above, according to the system according to the present invention, whether or not the external circuit is regular can be determined based on whether or not the impedance of the external circuit is within the range set by the gaming machine manufacturer. Even if a so-called “hanging” circuit is connected to an external terminal and an attempt is made to disguise a prize, it can be detected, so that it is possible to prevent fraudulent actions that could not be eliminated with the conventional circuit.
In addition, since the impedance of the gaming machine varies from manufacturer to manufacturer, it is more difficult for the fraudster to perform fraud because the impedance of the hanging circuit needs to be adjusted according to each model.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a security system according to the present invention.
FIG. 2 is a schematic block diagram of input control means 4 and comparison / control means 5 according to the present invention.
[Explanation of symbols]
1 gaming machine control board 2 gaming machine control microcomputer 3 CPU (central processing unit)
4 Input control means 4a Measurement trigger control circuit 4b Input control circuit 4c A / D converter 4d Control signal 4e indicating the logic level output from the input control circuit 4b The impedance "" applied to the terminal 13 by the logic level of the control signal 4d Select signal 4f for setting an allowable range at "Low level" or "High level" Impedance measurement value data 4g of terminal 13 digitally converted by A / D converter 4c so that CPU 3 can read measurement value data 4f 4g (abbreviation: PDSR4g) for storing measured value data in
5 Comparison / Control Unit 5a “High Level” Upper Limit Set Value Data Register (abbreviation: HUDR5a)
5b “Low level” upper limit set value data register (abbreviation: LUDR5b)
5c “High level” lower limit set value data register (abbreviation: HLDR5c)
5d “Low level” lower limit set value data register (abbreviation: LLDR5d)
5e Upper limit value data multiplexer (abbreviation: upper limit MUX5e) for switching data stored in HUDR5a or LUDR5b
5f Lower limit value data multiplexer (abbreviation: lower limit MUX5f) for switching data stored in the HLDR 5c or LLDR 5d
5g Comparator for upper limit value data 5h Comparator for lower limit value data 5i Logical sum (OR)
5j Status display control circuit 6 User ROM
6a Regular model application value (set to HUDR5a / LUDR5b / HLDR5c / LLDR5d)
7 Boot ROM
8 User RAM
9 Boot RAM
10 General bus 10a such as an address bus / data bus / control signal bus in the gaming machine control microcomputer 2 Control signal 11 indicating whether or not the impedance applied to the terminal 13 is normal The input control means 4 from the terminal 13 And the internal signal 12 connected to the comparison / control means 5 The internal signal 13 output from the comparison / control means 5 to the terminal 14 The measurement target external terminal (abbreviation: terminal 13) of the microcomputer for gaming machine control
14 External terminal (abbreviation: terminal 14) for status display of the microcomputer for gaming machine control
15 Model 16 of an external circuit (for example, a winning sensor) showing a normal impedance that passes the type test applied to the terminal 13 An illegal impedance that is incremented or decremented from the normal impedance by an unauthorized modification applied to the terminal 13 Model of “hanging circuit” shown

Claims (2)

It is connected to the user ROM 6 in which the setting allowable range 6a of the impedance value of the user program and the regular external circuit is stored, the CPU 3 that controls the gaming machine that can detect unauthorized modification of the gaming machine control board 1, and the external circuit. The external terminal 13, the input control means 4 for realizing the impedance measurement of the terminal 13 at the “High level” or “Low level” applied to the input terminal 13, and the impedance of the terminal 13 Comparison / control means 5 for determining whether or not the tolerance is set in advance, and whether or not the chip is authorized at the time of power-on or system reset input for initializing the entire gaming machine And after the setting allowable range 6a written in the user ROM 6 is written in each setting register in the comparison / control means 5, the impedance meter A boot ROM7 a boot program for the boot process of the control and the like are stored in a work for RAM8 user program for controlling the operation of the gaming machine, consists RAM9 Prefecture for the boot program work,
The input control circuit 4 is an A / D converter 4c for converting the applied voltage of the external terminal 13 into a digital value, and input control for identifying whether the applied voltage of the external terminal 13 is "High level" or "Low level". Based on the output value of the circuit 4b and the input control circuit 4b, a selection signal is transmitted to the comparison / control means 5 as to whether the output value of the A / D converter is “High level” or “Low level”. A measurement trigger control circuit 4a,
The comparison / control means 5 is configured to store the upper and lower limit set values of “High level” and the upper and lower limit set values of “Low level” based on the select signal of the measurement trigger input control circuit 4a; An upper limit value data comparator and a lower limit value data comparator for inputting an output value of the A / D converter 4c and comparing it with an upper limit value or a lower limit value, and for the upper limit value data comparator and the lower limit value data comparator Based on the select signal from the measurement trigger control circuit, the upper limit set value at the “High level” for the upper limit value data comparator or the upper limit set value at the “Low level” and the “High level” for the lower limit data comparator. Data multiplex to switch and input the lower limit set value or the lower limit set value at “Low level” When, security system capable of detecting tamper of the gaming machine, characterized in that it is constituted by an OR circuit for ORing the output data of the upper limit value data comparator and a lower limit value data comparator. The upper limit value data comparator and the lower limit value data comparator measure whether or not the “High level” of the measured value is not more than the upper limit set value of the “High level” and not less than the lower limit set value of the “High level”. It is configured to determine whether the value “Low level” is less than or equal to the “Low level” upper limit set value and greater than or equal to the “Low level” lower limit set value, and when both are cleared, it is determined to be normal The security system capable of detecting unauthorized modification of the gaming machine according to claim 1.

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