JP4413315B2 - Security system that can detect unauthorized modification of gaming machines - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the security of a microcomputer for controlling a gaming machine mounted on a board used for controlling these gaming machines (hereinafter referred to as a gaming machine control board), such as a pachinko gaming machine, an arrangement-type pachinko gaming machine, and a revolving gaming machine. The present invention relates to a security system that belongs to the field of systems and detects unauthorized modification of a gaming machine carried into an actual amusement park after passing a type test.
[0002]
[Prior art]
In the current gaming machine, the control CPU is periodically reset and 1 is added to the internal counter at that timing to make a lottery counter. The lottery.
[0003]
[Problems to be solved by the invention]
Therefore, it is only necessary to analyze the program to know the timing of the lottery lottery and to generate a start winning signal from the outside at that timing. By using this, an illegal operation is performed in which a “hanging” circuit for inputting an illegal prize signal from the outside is attached to the prize sensor and the prize signal is intentionally input to the control CPU.
Accordingly, the present invention has been made in view of the drawbacks of the prior art, and in view of the fact that if a “hanging” circuit is attached to the CPU, the time from winning detection to winning passing of the entire winning circuit will be changed. The situation of time is measured for each winning prize or every winning prize, and when the measured value is not within a predetermined range, it is judged that it is abnormal.
Furthermore, when a winning signal is transmitted using a “hanging circuit”, the winning signal always has the same waveform, and even if the time from winning to winning is within the set range, the winning time is not always the same. In view of this, it was determined that such a case is also illegal.
[0004]
[Means for Solving the Problems]
In other words, the present invention is a user ROM in which the user program and the allowable range setting value (upper limit value and lower limit value) data from the winning detection of the regular external circuit at the time when the game machine manufacturer applied for the model to the winning pass is stored. A gaming machine control capable of detecting unauthorized modification of the gaming machine control board, an external terminal connected to an external circuit, and measurement of a time from winning detection applied to the external terminal to winning winning. Input control means for realizing, and a register for storing measurement data for the past several times for determining whether or not the time from winning detection of the external terminal 13 to winning passing is within a preset allowable range The comparison / control means and the allowable range set value data written in the user ROM at the time of power-on or system reset input to initialize the entire gaming machine / Boot ROM that stores a boot program that performs boot processing, such as control of time measurement from winning detection to winning passing after writing to each setting register in the control means, and work of a user program that controls the operation of the gaming machine A user RAM that is used for booting, and a boot RAM that is used for boot program work,
The input control means includes a time Ta from winning detection including a noise signal as an input signal to the external terminal until winning detection after removing the noise, a time Tb from winning passing including the noise signal to winning passing after removing the noise, noise Time Tc from winning detection after removal to winning passing including noise signal and / or time Td from winning detection after removing noise to winning passing after removing noise are measured, and the measured times Ta, Tb, Tc and / Or Td is compared with the upper limit and lower limit data of the time from winning detection to winning passing stored in the user ROM, and if the measured time Ta, Tb, Tc and / or Td is within the upper limit / lower limit data range determines that the regular prize, if it is outside the upper and lower limit range is configured to determine that it is not the winning of normal, the comparator / control unit measures time Ta, Tb, T And / or Td to achieve a plurality of times consecutively present the constructed gaming machine capable of security systems detecting tamper of to determine that unauthorized winning when the same data object.
According to a second aspect of the present invention, the input control means includes a winning sensor signal detection circuit for identifying whether or not the input signal of the external terminal is a winning including a noise signal, and measurement times Ta and Tb based on the detection signal of the detection circuit. , Tc or Td for measuring the start trigger signal to the timer circuit for generating the start trigger signal, the waveform shaping circuit for removing the noise component of the input signal to the external terminal, and the voltage of the signal from which the noise is removed A voltage change detection circuit for detecting whether or not a prize has been won, and a measurement trigger generation for generating a measurement trigger signal to the timer circuit for measuring the time Ta, Tb, Tc or Td based on the detection signal of the detection circuit Circuit, a clock generation circuit for generating a clock to be supplied to the timer circuit, and a frequency of the clock supplied from the clock generation circuit. The time Ta, Tb, is composed of a timer circuit for measuring a Tc or Td,
The comparison / control means inputs each setting register for storing upper and lower limit set values of the time Ta, Tb, Tc or Td, a status register for storing actual measurement value data, and an output value of the timer circuit g. An upper limit value data comparator and lower limit value data comparator for comparing with the upper limit value or the lower limit value, the upper limit value data comparator based on a select signal from the measurement control circuit, and the upper limit value data comparator. And an AND circuit that generates a stop signal to the CPU based on the logical data of the lower limit value data comparator output, and a status display control circuit that generates a signal for displaying the status of the measurement result on the terminal based on the logical data. A security system capable of detecting unauthorized modification of gaming machines That.
According to a third aspect of the present invention, the upper limit value data comparator and the lower limit value data comparator are configured such that each measurement time Ta, Tb, Tc, or Td is within the upper limit set value range and within the lower limit set value range. Determine whether
A: Any one of the measurement times Ta, Tb, Tc, Td B: Any two of the measurement times Ta, Tb, Tc, Td C: Any three of the measurement times Ta, Tb, Tc, Td D: A security system capable of detecting unauthorized modification of a gaming machine configured to be judged as legitimate when any one of the measurement times Ta, Tb, Tc, and Td is cleared from one of A to D. It is.
[0005]
[Action]
In the security system according to the present invention, for example, at the beginning of powering on the gaming machine, that is, before starting the measurement of the time from winning detection of the measurement target external terminal of the gaming machine control microcomputer to winning passing in the boot mode, The setting allowable range of the time Ta, Tb, Tc or Td of the external circuit stored in the user ROM is written to each setting register. Then, after the user program for controlling the operation of the gaming machine is activated, the measurement of the time Ta, Tb, Tc or Td is started when a prize is actually received.
The measurement value of the measurement target external terminal is counted by the timer circuit and input to the upper limit value data comparator and the lower limit value data comparator. In addition, the set value of the normal time allowable range of the measurement target external terminal is input to one side of each of the above comparators, and diagnosis is performed as to whether or not the time of the measurement value of the measurement target external terminal is within the allowable range. become. As a result, when it is not within the allowable range set by the gaming machine manufacturer side, that is, when it is determined that an illegal board or the like is connected to the outside, “0” is output from the AND circuit, and the CPU is stopped or determined. The result will be notified to the outside.
If any of the measurement times Ta, Tb, Tc, or Td continuously matches the measured value, the comparison / control unit determines that an illegal winning has been performed and stops the CPU or displays the determination result. It will inform the outside.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
In the following, the invention will be described in detail according to the illustrated embodiment.
FIG. 1 is a schematic block diagram of a security system according to the present invention. A gaming machine control board 1 for controlling a gaming machine has a gaming machine control micro that can detect unauthorized modification of the gaming machine control board 1. A computer 2 is mounted. The microcomputer 2 includes a CPU (central processing unit) 3, an input control unit 4, a comparison / control unit 5, a user ROM 6 in which a regular model application value 6 a and a user program are stored, and a boot ROM 7. User RAM 8 and boot RAM 9 are built in, and a security system is realized by the above-described configuration.
[0007]
The central processing unit 3 (CPU) controls each device incorporated in the gaming machine control microcomputer 2.
The input control means 4 performs control for realizing measurement of the time from winning detection of a signal input to the measurement target external terminal 13 to winning winning.
The comparison / control means 5 diagnoses whether or not the time from winning detection of the measurement target external terminal 13 to winning passing is within an allowable range set by the gaming machine manufacturer side, and the result is the microcomputer 2 for controlling the gaming machine 2 Control for output to the status display target external terminal 14 (hereinafter referred to as terminal 14).
The user ROM 6 is a read-only memory in which a normal type application value 6a created by the user and a user program for controlling the operation of the gaming machine and a security code are stored.
The boot ROM 7 determines whether or not the gaming machine control microcomputer 2 is legitimate (security check) when the power is turned on or when a system reset for initializing the entire gaming machine is input, and from the winning detection to the winning passing. Stores a program (boot program) for setting data in the upper / lower limit value setting data registers (5a, 5e, 5b, 5f, 5c, 5g, 5d, 5h) for executing control such as time measurement This is a read-only memory. These upper limit / lower limit set values are written in the setting registers (5a · 5e, 5b · 5f, 5c · 5g, 5d · 5h) by operating the boot program when the power is turned on.
The user RAM 8 is a work RAM for executing a user program for controlling the operation of the gaming machine.
The boot RAM 9 is a work RAM when executing a boot program that is not accessible in the user mode.
Reference numeral 10 denotes a general bus in which the address bus, data bus, control signal bus, and the like in the gaming machine control microcomputer 2 are integrated.
Reference numeral 11 denotes an internal signal connected from the measurement target external terminal 13 to the input control means 4 and the comparison / control means 5.
An internal signal line 12 is output from the comparison / control means 5 to the terminal 14.
Reference numeral 15 denotes a regular winning signal that passes the type test applied to the external terminal 13 to be measured, and 16 denotes an illegal winning signal due to unauthorized modification applied to the terminal 13.
[0008]
FIG. 2 is a schematic block diagram of the input control means 4 and the comparison / control means 5 according to the present invention.
The input control means 4 includes a winning sensor signal detection circuit 4a, a start trigger generation circuit 4b, a waveform shaping circuit 4c, a voltage change detection circuit 4d, a measurement trigger generation circuit 4e, a clock generation circuit 4f, and a timer circuit 4g.
The comparison / control means 5 is an upper limit set value data register 5a (hereinafter referred to as 5a) for storing an upper limit set value of a time from winning detection including a noise signal to winning detection after removing the noise, removing noise from the winning pass including the noise signal. Upper limit set value data register 5b (hereinafter referred to as 5b) for storing the upper limit set value of the time until the subsequent winning pass, and upper limit setting for storing the upper limit set value of the time from winning detection after noise removal until winning pass including the noise signal From the value data register 5c (hereinafter 5c), the upper limit setting value data register 5d (hereinafter 5d) for storing the upper limit set value of the time from winning detection after noise removal to winning passing after noise removal, from winning detection including a noise signal Lower limit set value data register 5e (hereinafter referred to as 5e) that stores the lower limit set value of the time until winning detection after noise removal, from winning pass including noise signal Lower limit set value data register 5f (hereinafter referred to as 5f) for storing the lower limit set value of the time until winning pass after noise removal, and the lower limit set value of the time from winning detection after eliminating noise to winning pass including noise signal are stored. Lower limit set value data register 5g (hereinafter referred to as 5g), lower limit set value data register 5h (hereinafter referred to as 5h) for storing the lower limit set value of time from winning detection after noise removal to winning passage after noise removal, winning including a noise signal A register (hereinafter referred to as 5i) for storing measured value data so that the CPU 3 can read the time from detection to winning detection after noise removal, and the CPU 3 reads the time from winning passing including noise signals to winning winning after noise removal. A register (hereinafter 5j) for storing measured value data so that it can be output, and the time from winning detection after noise removal to winning passing including a noise signal A register for storing measurement value data (hereinafter referred to as 5k) so that the CPU 3 can read out, and a register for storing measurement value data so that the CPU 3 can read out the time from winning detection after noise removal to winning passing after noise removal (hereinafter referred to as the following) 5l), an upper limit data multiplexer 5n (hereinafter 5n) for switching data stored in the measurement control circuits 5m, 5a to 5d, and a lower limit data multiplexer 5o (hereinafter 5o) for switching data stored in 5e to 5h, It comprises an upper limit value data comparator 5p, a lower limit value data comparator 5q, a logical product (AND) circuit 5r, and a status display control circuit 5s.
[0009]
The winning sensor signal detection circuit 4a is a circuit that detects a winning including a noise signal, and has a built-in circuit for detecting whether the chattering portion rises or falls when winning of the signal is detected or when the winning is passed. This is notified to the generation circuit 4b.
The start trigger generation circuit 4b generates a start signal for starting time measurement to the timer circuit 4g based on the winning detection signal including the noise signal transmitted from the winning sensor signal detection circuit 4a and the winning passage signal. Signal 1) (shown as ◯ 1 in the figure) and signal 2) (shown as ◯ 2 in the figure) correspond to this, and signal 1) (described as ◯ 1 in the figure) represents the noise signal. Signal 2) (indicated by ○ 2 in the figure) at the time of detecting a winning including a start signal when starting winning including a noise signal.
The waveform shaping circuit 4c incorporates a filter circuit having a shift register configuration, and removes a chattering noise component of the winning signal.
The voltage change detection circuit 4d detects the presence / absence of a winning based on the winning signal from which noise has been removed by the waveform shaping circuit 4c.
The measurement trigger generation circuit 4e generates an end signal for ending the time measurement to the timer circuit 4g based on the voltage change signal (presence / absence of winning) of the voltage change detection circuit 4d. The end signal 3) (shown as ◯ 3 in the figure) and the end signal 4) (shown as ◯ 4 in the figure) correspond to this, and the end signal 3) (shown as ◯ 3 in the figure) At the time of winning detection after noise removal, the end signal 4) ( denoted as “ 4” in the figure) indicates the time of winning passing after noise removal.
The clock generation circuit 4f generates a clock to be supplied to the timer circuit 4g.
The timer circuit 4g is based on various trigger signals from the start trigger generation circuit 4b and the measurement trigger generation circuit 4e. (1) Time Ta from winning detection including a noise signal to winning detection after noise removal,
(2) Time Tb from the winning pass including the noise signal to the winning pass after noise removal,
(3) Time Tc from winning detection after noise removal to winning passing including noise signal,
(4) Time Td from winning detection after noise removal to winning passing after noise removal
Measure.
The measurement control circuit 5m controls the entire winning time measuring system at the terminal 13, and generates a select signal for controlling each register and setting an allowable range for each measuring of the winning time.
The data stored in the registers 5a to 5d is the normal upper limit allowable range of the winning signal detection to the passing time input to the terminal 13 from the peripheral circuit of the gaming machine control board developed by the gaming machine manufacturer. The data stored in 5e to 5h is a normal lower limit allowable range.
The data stored in these registers 5a to 5h is determined by the gaming machine manufacturer because the value varies depending on the gaming machine development manufacturer. These data are sent to one side of the upper limit value data comparator 5p and the lower limit value data comparator 5q, and compared with the measured value data counted by the timer circuit 4g, and the result is a logical product (AND) circuit 5r. Is output from. That is, the control signal 10a indicating whether or not the winning signal input to the terminal 13 is normal is sent to the CPU 3 via the bus 10, and when the determination result is not within the allowable range, for example, the CPU 3 is stopped. To do. The control signal 10a is also sent to the status display control circuit 5s, and the status display control circuit 5s performs status display control for notifying the outside of the determination result according to the logical value of the control signal 10a.
[0010]
With the configuration described above, the operation of the comparison / control means 5 of the present embodiment will be specifically described.
The comparison circuits (comparators) 5p and 5q of this embodiment output logical expressions of A> B and A <B indicating the allowable ranges, respectively. As a result, when any one is out of the allowable range, “0” is output from the logical product (AND) circuit 5r, and it is determined to be illegal. Only when both are “1”, it is determined to be normal.
[0011]
FIG. 4 is a schematic block diagram of a second embodiment of the comparison / control means 5 according to the present invention.
The storage unit 5u for measured data of Ta to Td is a register or the like for storing each measured value data output from the timer circuit 4g.
The coincidence comparison comparator 5v of the measurement times Ta to Td is a coincidence comparison comparator of the Ta to Td measurement value data, and whether or not the arbitrarily selected measurement value data (for example, three consecutive measurement value data) match all. And the determination result is notified to the determination circuit 5w.
The determination circuit 5w makes a determination based on the comparison result information of each measurement value data sent from the coincidence comparison comparator 5v, and notifies the CPU of the determination result.
[0012]
With the configuration described above, the operation of the comparison / control means 5 of the second embodiment will be specifically described.
The Ta-Td coincidence comparison comparator 5v outputs a logical expression of Ta1 = Ta2 = Tan indicating coincidence of arbitrary measurement value data, for example, Ta measurement value data Ta1, Ta2,. As a result, if they match, “0” is output from 5 va, and “0” is output from 5 vb, 5 vc, and 5 vd in the same manner. The determination circuit 5w makes a determination based on the comparison result information sent from each comparator, and when the information is any one, two, three, or all “0”, it is determined as “illegal”. It is also determined that the information is “regular” when one, two, three, or all of the information is “1”.
[0013]
In the case of “0” in the second embodiment, that is, the basis for determining “illegal” when the measured value data match, the regular winning is different in the winning angle and speed of the ball for each winning, and it is naturally a measured value. Since the data changes every time, for example, there is no possibility that all three measured value data of time Ta coincide. If they coincide with each other, it is possible to consider an illegal false winning interval signal aiming at the jackpot period.
[0014]
【The invention's effect】
As described above, according to the system according to the present invention, it is determined whether or not the external circuit is regular depending on whether or not the time from the winning detection of the external circuit to the winning passage is within the range set by the gaming machine manufacturer. Because it can be judged, it can be detected even if a so-called “hanging” circuit is connected to an external terminal to try to disguise a prize, thus preventing fraudulent acts that could not be eliminated by previous circuits. It becomes possible.
In addition, since the time from the winning detection of the gaming machine to the winning passage varies depending on the manufacturer, it is necessary for the fraudster to adjust the time from the winning detection of the “hanging” circuit to the winning passage in accordance with each model. In addition, it is more difficult to cheat.
Furthermore, even if the fraudster sets the winning time within the range of the normal upper limit and lower limit, the time cannot be random, so the same time from winning detection to passing the winning will continue. Focusing on the fact that it must be done, and in such a case, since it is configured to be determined to be fraudulent, fraudulent acts can be more effectively prevented.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a security system according to the present invention.
FIG. 2 is a schematic block diagram of input control means 4 and comparison / control means 5 according to the present invention.
FIG. 3 is a timing chart showing respective times Ta, Tb, Tc, Td from winning detection to winning passing according to the present invention.
FIG. 4 is a schematic block diagram of a second embodiment of the comparison / control means 5 according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Game machine control board 2 Microcomputer for game machine control 3 CPU (central processing unit)
4 input control means 4a winning sensor signal detection circuit 4b start trigger generation circuit 4c waveform shaping circuit 4d voltage change detection circuit 4e measurement trigger generation circuit 4f clock generation circuit 4g timer circuit 5 comparison / control means 5a noise detection from winning detection including noise signal Upper limit set value data register 5b for the time until winning detection after removal 5b Upper limit set value data register 5c for the time from winning pass including the noise signal to winning pass after removing the noise 5c Win including the noise signal from winning detection after removing noise Upper limit setting value data register 5d for the time until passing 5d Upper limit setting value data register 5e for the time from winning detection after noise removal to winning passing after noise removal 5e Time from winning detection including noise signal to winning detection after noise removal Lower limit set value data register 5f Including noise signal Lower limit set value data register for the time from winning a prize to passing the winning after noise removal 5g Lower limit setting value data register for the time from winning detection after removing noise to winning winning including the noise signal 5h Prize winning detection to noise after removing noise Lower limit set value data register 5i for time until winning after passing is removed 5i Register 5j for storing measured value data of time from winning detection including a noise signal to winning detection after removing noise so that the CPU 3 can read the measured value data Register for storing measured value data of time from winning a prize including a noise signal to winning passing after noise removal so that the CPU 3 can read the measured value data 5k Winning after removing noise so that the CPU 3 can read the measured value data Register for storing measured value data of time from detection to passing a prize including a noise signal A register that stores measurement value data of a time from winning detection after noise removal to winning passage after noise removal so that the CPU 3 can read out the measurement value data. 5m Measurement control circuit 5n Switches data stored in 5a to 5d. Upper limit value data multiplexer 5o Lower limit value data multiplexer for switching data stored in 5e to 5h 5p Upper limit value data comparator 5q Lower limit value data comparator 5r Logical product (AND) circuit 5s Status display control circuit 5t Timer circuit output data 5u Ta to Td measurement value data storage means 5v Ta to Td coincidence comparison comparator 5w determination circuit 6 ROM for user
6a Regular model application value (set to 5a-5h)
7 Boot ROM
8 User RAM
9 Boot RAM
DESCRIPTION OF SYMBOLS 10 Comprehensive bus such as address bus / data bus / control signal bus in game machine control microcomputer 2 10a Control signal indicating determination result of whether winning signal input to terminal 13 is normal 11 Input control means from terminal 13 4 and an internal signal connected to the comparison / control means 5 12 an internal signal output from the comparison / control means 5 to a terminal 14 13 an external terminal to be measured of the gaming machine control microcomputer 14 a status of the gaming machine control microcomputer is displayed External connection terminal 15 for a normal winning signal that passes the type test applied to the terminal 13 16 Unauthorized winning signal due to unauthorized modification applied to the terminal 13

Claims (3)

User ROM 6 storing user program and allowable range setting value (upper limit value and lower limit value) data 6a from winning detection of the regular external circuit to the passing of winning at the time when the game machine manufacturer applied for the model, and gaming machine A CPU 3 that controls gaming machines capable of detecting unauthorized modification of the control board 1, an external terminal 13 connected to an external circuit, and a time measurement from winning detection applied to the external terminal 13 to winning winning is realized. Input control means 4 for
A comparison / control means 5 having a register for storing measurement data for the past several times for determining whether or not the time from winning detection to winning winning of the external terminal 13 is within a preset allowable range;
The allowable range set value data 6a written in the user ROM 6 at the time of power-on or at the time of system reset input for initializing the entire gaming machine is written to each setting register in the comparison / control means 5 and then a prize is detected. A boot ROM 7 storing a boot program for performing a boot process such as control of time measurement until passing, a user RAM 8 for user program work for controlling the operation of the gaming machine,
A boot RAM 9 for boot program work,
The time Tb from the winning detection that the input signal to the external terminal 13 includes the noise signal to the winning detection after the noise removal until the winning detection after the noise removal, and the time Tb from the winning pass including the noise signal to the winning pass after the noise removal , The time Tc from the winning detection after noise removal to the winning passage including the noise signal and / or the time Td from the winning detection after noise removal to the winning passage after the noise removal are measured, and the measured times Ta, Tb, Comparison between Tc and / or Td and the upper limit and lower limit data 6a of the time from winning detection to winning passing stored in the user ROM 6 is performed, and the measured times Ta, Tb, Tc and / or Td are upper limit / lower limit data. It determines that the range if the regular prize, if it is outside the upper and lower limit range is configured to determine that it is not the winning of normal, the comparator / control unit measures time T , Tb, Tc and / or Td is several times consecutively gaming machine capable of security systems detect the tampering of which is characterized by being configured to determine that unauthorized winning when the same data. The input control means 4 is a winning sensor signal detection circuit 4a for identifying whether or not the input signal of the external terminal 13 is a winning including a noise signal, and measurement times Ta, Tb, Tc based on the detection signals of the detection circuit 4a. Alternatively, a start trigger generation circuit 4b that generates a start trigger signal to a timer circuit for measuring Td, a waveform shaping circuit 4c that removes a noise component of an input signal to the external terminal 13, and a voltage of the signal from which noise has been removed And a voltage change detection circuit 4d for detecting whether or not a prize has been won, and a measurement trigger signal to the timer circuit for measuring the time Ta, Tb, Tc or Td based on the detection signal of the detection circuit 4d. A measurement trigger generation circuit 4e, a clock generation circuit 4f that generates a clock to be supplied to the timer circuit 4g, and the clock generation circuit 4f The time Ta based on the frequency of the supplied clock, Tb, is composed of a timer circuit 4g for measuring the Tc or Td,
The comparison / control means 5 has each setting register (5a · 5e, 5b · 5f, 5c · 5g or 5d · 5h) for storing the upper and lower limit set values of the time Ta, Tb, Tc or Td and the actual measurement. A status register (5i, 5j, 5k or 5l) for storing value data and an output value of the timer circuit 4g are inputted and an upper limit value data comparator 5p for comparing with an upper limit value or a lower limit value and a lower limit value A stop signal to the CPU 3 based on the logical data of the upper limit value data comparator 5p and the upper limit value data comparator 5p and the lower limit value data comparator 5q based on the data comparator 5q and a select signal from the measurement control circuit 4m. And an AND circuit 5r for generating a measurement result status display on the terminal 14 based on the logic data of the 5r. Capable security systems detecting tamper of claim 1, wherein the game machine characterized in that it is composed of a status display control circuit 5s that generates No.. The upper limit value data comparator 5p and the lower limit value data comparator 5q determine whether each measurement time Ta, Tb, Tc or Td is within the upper limit set value range and within the lower limit set value range,
A: Any one of the measurement times Ta, Tb, Tc, Td
B: Any two of the measurement times Ta, Tb, Tc, Td
C: Any three of the measurement times Ta, Tb, Tc, and Td
D: All of the measurement times Ta, Tb, Tc, Td
3. The security system capable of detecting unauthorized modification of a gaming machine according to claim 2, wherein when any one of A to D is cleared, it is determined to be legitimate.

Images