JP4284576B2 - Fault detection method for voltage driven semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage-driven semiconductor element constituting a power converter, and more particularly, a power converter configured by connecting three or more voltage-driven semiconductor elements in series to each arm in order to increase the voltage of a power converter circuit. The present invention relates to a failure detection method for a voltage driven semiconductor device.
[0002]
[Prior art]
FIG. 3 shows a circuit for one phase of an inverter in which three IGBTs are connected in series as a conventional example in which IGBTs (insulated gate bipolar transistors) are connected in series to each arm in order to increase the voltage in the power converter. Indicates.
[0003]
As shown, this circuit includes IGBTs Q1, Q2, Q3 (upper arm) and Q4, Q5, Q6 (lower arm), a DC power supply (voltage Ed), and snubber capacitors Cs1, Cs2.
, Snubber diodes Ds1, Ds2, snubber resistors Rs1, Rs2, and a snubber circuit (RC snubber circuit) corresponding to each IGBT.
[0004]
GDU1 to GDU6 are Q1 to Q6 gate drive circuits. Specifically, for example, they are described in FIG. 2 of 1999 patent application No. 129893 (filing date; May 11, 1999) by the same applicant. FIG. 4 shows the configuration of the gate drive circuit.
[0005]
That is, as shown in FIG. 4, the TR1, TR2 for turning on and off the IGBT, the interface circuit IF, the overvoltage discrimination circuit OV for discriminating whether the voltage detected by the detection resistor Rd is an overvoltage, and this when the IGBT is turned off. A re-ON circuit RO for re-ON in the active region is formed.
[0006]
The operation when the gate drive circuit shown in FIG. 4 is used in the circuit configuration shown in FIG. 3 will be described below with reference to the waveform diagram shown in FIG.
[0007]
Due to a difference in turn-off timing caused by variations in element characteristics between Q1 and Q3, for example, Q1 starts a turn-off operation first, and Q2 and Q3 are still on during a period of Δt (difference in turn-off timing) from this start time. In this state, only the collector-emitter voltage V _{CE of} Q1 starts to rise, and with this rise, when the voltage detected by the detection resistor Rd reaches the overvoltage level, the collector of Q1 is detected by the overvoltage discrimination circuit OV. The emitter voltage V _CE is determined as an overvoltage. The re-ON circuit RO operates according to the determination result, and the gate-emitter voltage V _GE is controlled to a voltage in the vicinity of the threshold value of Q1, thereby turning on Q1 again in the active region. When Q1 again turned on, it is possible to collector-emitter voltage V _CE of the transistor Q1 is lowered, the overvoltage is prevented from being applied between the Q1 collector-emitter, to avoid element destruction due to overvoltage application.
[0008]
Also conventionally, when the device failure occurs in any of the IGBT of Q1~Q6 detects on to the IGBT, by known techniques such as monitoring the relationship between the off-signal and the collector-emitter voltage V _CE Thus, the protection operation for performing the off operation on all the IGBTs is performed.
[0009]
[Problems to be solved by the invention]
In the gate drive circuit having the configuration shown in FIG. 4, the operation when any one of the IGBTs connected in series causes an element breakdown (short circuit breakdown) for some reason is shown in FIG. This will be described below with reference to waveform diagrams.
[0010]
FIG. 6 shows an example of an operation waveform when Q3 among the Q1 to Q3 of the circuit shown in FIG. 3 causes element destruction.
[0011]
That is, as in the waveform diagram shown in FIG. 5, when Q1 starts the turn-off operation first, and Q2 and Q3 start the turn-off operation with a delay of the turn-off timing from the start time, first, overvoltage discrimination is performed. collector-emitter voltage V _CE of the transistor Q1 in circuit OV is determined that an overvoltage, re-on circuit RO is operated, thereby re-turn on Q1 in the active region. If a short circuit breakage occurs in Q3 while Q2 and Q3 thereafter are turned off, the voltage Ed of the DC power supply is shared between Q1 and Q2, and therefore the collector-emitter voltage V _CE (Q1 ), V _CE (Q2) try to increase to Ed / 2 (approximately Ed / 3 when Q3 is in a normal state), respectively, and the collector-emitter voltage V _{CE of} Q2 is discriminated as an overvoltage in the overvoltage discrimination circuit OV. Then, the re-on circuit RO operates and Q2 is also re-on within the active region.
[0012]
As a result, since Q2 is turned on again, both Q1 and Q2 continue to be turned on in the active region, and when the lower arm IGBTs Q4 to Q6 are turned on, the arm is short-circuited. There was a risk that accidents due to device failures would expand.
[0013]
The above-described operation is a problem that occurs because it is difficult to detect at high speed in the conventional element failure detection method.
[0014]
An object of the present invention is to solve the above-mentioned problems and to provide a failure detection method for a semiconductor element capable of detecting the element breakdown of this type of voltage-driven semiconductor element at high speed.
[0015]
[Means for Solving the Problems]
The present invention provides a power conversion device in which three or more voltage-driven semiconductor elements are connected in series to each arm.
During the turn-off operation of each of the voltage-driven semiconductor elements connected in series, it is determined whether a voltage applied to each voltage-driven semiconductor element is an overvoltage, and at least two of the voltage-driven semiconductor elements are selected. A failure detection method for a voltage-driven semiconductor element in which element breakdown occurs in any one of the voltage-driven semiconductor elements connected in series when a voltage applied to the voltage-driven semiconductor element is determined to be an overvoltage It is characterized by making it carry out.
[0016]
According to the present invention, when any one of the voltage-driven semiconductor elements of each arm formed by connecting voltage-driven semiconductor elements in series has a short circuit failure, the remaining healthy voltage-driven semiconductor elements are turned off. Therefore, it is possible to detect a device failure at high speed by monitoring whether or not the voltage applied to each semiconductor device for each turn-off operation of the voltage-driven semiconductor device is an overvoltage.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, which is an example in which the failure detection method for a voltage driven semiconductor element of the present invention is added to the gate drive circuit shown in FIG.
[0018]
That is, the gate drive circuit shown in FIG. 1 includes a gate drive circuit configured as shown in FIG. 4, a gate voltage monitoring circuit CK, and an element failure determination circuit CV composed of, for example, an AND element and an OR element shown in FIG. Is added.
[0019]
The operation when the gate drive circuit shown in FIG. 1 is used in the circuit configuration shown in FIG. 3 will be described below with reference to the waveform diagram shown in FIG.
[0020]
That is, similarly to the waveform diagram shown in FIG. 5, Q1 starts the turn-off operation first, and when Q2 and Q3 start the turn-off operation with a delay of the turn-off timing from the start time, collector-emitter voltage V _CE of the transistor Q1 by the overvoltage determining circuit OV is determined that the overvoltage, operate the re-on circuit RO of Q1, causes re-turn on Q1 in the active region, a gate voltage monitoring circuit CK of Q1 And outputs a logic “H” level to the outside and to the element failure determination circuit CV of Q1. If a short-circuit breakdown occurs in Q3 during subsequent turn-off operations of Q2 and Q3, the DC power supply voltage Ed is shared by Q1 and Q2, and therefore the collector-emitter voltage V _CE (Q1 ), V _CE (Q2) try to increase to the level of Ed / 2, respectively, and the collector-emitter voltage V _CE of Q2 is discriminated as an overvoltage by the overvoltage discrimination circuit OV of Q2, and the re-on circuit RO of Q2 operates. Q2 is also turned on again in the active region, and the logic "H" level is output to the outside and the element failure determination circuit CV of Q2 via the gate voltage monitoring circuit CK of Q2.
[0021]
From the time when Q2 is turned on again, the output of the element failure determination circuit CV of Q1 and the output of the element failure determination circuit CV of Q2 become the logic “H” level, and this logic “H” level is transferred to the outside. While outputting as an “element failure determination signal”, the operation of the re-on circuit RO of Q1 and the re-on circuit RO of Q2 is stopped, and the gate-emitter voltages V _GE (Q1) and V _GE (Q2 of Q1 and Q2) ) To a reverse bias level during normal OFF operation, and as a result, Q1 and Q2 are turned off. At this time, the collector-emitter voltages _VCE (Q1) and _VCE (Q2) of Q1 and Q2 are approximately Ed / 2.
[0022]
When the number of IGBTs in series in each arm is 4 or more, the overvoltage level and the number of IGBTs that have become overvoltage may be set in consideration of the breakdown voltage of the IGBT to be used, variations in element characteristics, etc. The function of the element failure determination circuit CV can be easily removed from the gate drive circuit and installed outside.
[0023]
【The invention's effect】
According to the present invention, it is possible to detect an element failure at high speed for each turn-off operation of the voltage-driven semiconductor element, and to prevent an accident from expanding in this type of power conversion device.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of FIG. 1. FIG. 3 is an overall configuration diagram of a power converter. FIG. 5 is a waveform diagram for explaining the operation of FIG. 4. FIG. 6 is a waveform diagram for explaining the operation of FIG.
Q ... Insulated gate bipolar transistor (IGBT), GDU ... Gate drive circuit, Ed ... DC power supply voltage, R ... Resistance, C ... Capacitor, TR ... Transistor, IF ... Interface circuit, OV ... Overvoltage discrimination circuit, RO ... Re-on Circuit, CK ... Gate voltage monitoring circuit, CV ... Element failure determination circuit.

Claims (1)

In a power conversion device in which three or more voltage-driven semiconductor elements are connected in series to each arm,
Determining whether the voltage applied to each voltage-driven semiconductor element is an overvoltage during the turn-off operation of each of the voltage-driven semiconductor elements connected in series;
When the voltage applied to at least two voltage-driven semiconductor elements among the voltage-driven semiconductor elements is determined as an overvoltage,
A failure detection method for a voltage-driven semiconductor element, wherein element breakdown occurs in any of the voltage-driven semiconductor elements connected in series.

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