JP4289983B2 - Phase velocity detector - Google Patents

Description

  The present invention relates to synchronous control and positioning control of a plurality of electric motors that require high accuracy such as a shaftless rotary printing machine and a machine tool, and in particular, not only when the motor is stopped or during low-speed rotation but also during high-speed rotation. The present invention relates to an apparatus for detecting phase and speed with extremely high accuracy.

  For shaftless rotary printing machines that perform high-precision synchronous control between multiple motors and machine tools that perform precise positioning, the phase and speed of the motor or output shaft must be detected with high accuracy. A rotary encoder with high precision is required, but this rotary encoder conventionally uses an absolute encoder or an increment encoder.

In order to improve the detection accuracy of the phase using an absolute encoder, an absolute encoder having an analog signal for interpolating the absolute digital signal in addition to the absolute digital signal has been conventionally devised (see, for example, Patent Document 1). .
However, although such improvements have been made, digital signals are still used, and it is necessary to incorporate tracks and sensors for the number of digits of the digital signal in the absolute encoder and to prepare a large number of signal lines outside. is there. Ordinarily, an absolute encoder may take time to actually acquire phase data after instructing the phase reading from the control device side, and in particular, it detects the phase of a rotating body that is operating at high speed in a short time. It was difficult or impossible to do.

On the other hand, an incremental encoder generates a plurality of cycles according to rotation and has a Z-phase output that identifies A-phase and B-phase outputs, which are two-phase rectangular waves having a phase difference of 90 °, and one rotation. Yes (hereinafter referred to as a rectangular wave incremental encoder), the rising or falling edge of the A-phase and B-phase output rectangular waves is counted by the phase counter on the control device side, and the phase counter is reset to zero by the Z-phase Thus, the rotational phase is conventionally obtained (see, for example, Patent Document 2).
This method has an advantage that the rotational phase can be detected in real time because only the edges of the rectangular wave are counted by the counter. However, the resolution of the rectangular wave incremental encoder is considered to be, for example, an upper limit of about 20000 pulses per revolution at present, and when this is used after multiplying by 4 times as usual, the resolution for detecting the phase per revolution is 80000. Is the limit.
As described above, there is a limit in detecting the phase at an arbitrary time because of the limited detection resolution. If this is shown in the figure, it becomes as shown in FIG.
That is, in (a) of FIG. 31, as the arbitrary time t1 is farther from the rising or falling edge of the rectangular wave of the rectangular wave incremental encoder, the detected phase error becomes larger.

Here, in addition to outputting the rectangular wave, there is an encoder that outputs a two-phase sine wave (hereinafter referred to as a sine wave incremental encoder), and this is used to detect the phase conventionally. (For example, refer to Patent Document 3).
FIG. 31B shows an example of the output waveform of the sine wave incremental encoder. As shown in the figure, the A phase and the B phase, which are sine waves having a phase difference of 90 °, output a sine wave of a plurality of cycles for each rotation of the incremental encoder. If the values of the A phase and the B phase at an arbitrary time t1 in FIG. 31B are a1 and b1, respectively, the phases at this time are pulses obtained by pulsing the A phase and the B phase and counting the edges. By using the phase C as a rough phase and using a microcontroller or the like, the interpolation phase α which is a dense phase can be obtained from the following equation (1).
α = αmax × {arcTAN (a1 / b1)} / 90 (1) Thus, unlike the rectangular wave incremental encoder shown in FIG. In the sine wave incremental encoder of (b), the interpolation phase at an arbitrary time t1 can be obtained by the above equation (1), and the interpolation phase and the pulse phase are combined to obtain a highly accurate rotational phase. .
Here, in FIG. 31B, an electrical angle of 90 ° is detected by a digital value of αmax by a microcontroller or the like, and θ ° is detected by a digital value of α. For example, if the interpolation phase is an unsigned 12-bit data size, αmax is 4095.

(A) of FIG. 32 explains the composition of one rotation phase when the pulse phase is detected with Y-bit resolution and the interpolation phase is detected with X-bit resolution, and (b) of FIG. Indicates the case where the pulse phase is C and the interpolation phase is α. For ease of explanation, a specific example shows that when the number of cycles per rotation of the sine wave incremental encoder is 512, the resolution of the pulse phase C becomes 2048 if this is multiplied by x4. If the interpolation phase has a data size of 12 bits, the resolution of the interpolation phase α is 4096. At this time, the phase of one rotation is the resolution of the following equation (2).
4096 × 4 × 512 = 8,388,608 (2) The phase of one rotation can be obtained with very high resolution by such means.
Japanese Utility Model Publication No.56-96322 Japanese Patent No. 3073727 JP 2000-314638 A

FIG. 33 shows that when a rotational phase is detected using a rectangular wave incremental encoder that has been conventionally implemented, such as in Patent Document 2, the origin of one rotation is obtained from the Z-phase output, and the phase counter is reset to zero. FIG. 6 shows how the rotation phase is obtained by counting the rising or falling edges of the rectangular waves of the A-phase and B-phase outputs with the phase counter.
33A shows the A-phase, B-phase, and Z-phase outputs of the rectangular wave incremental encoder, and FIG. 33B shows the temporal transition of the phase counter.
Here, the period in which the Z-phase output is “1” has a constant pulse width as shown in FIG. 33 (a), so that in the rotational phase shown in FIG. 33 (b), the period As indicated by P and Q, a period in which the rotational phase is unnecessarily zero occurs, which hinders obtaining a highly accurate rotational phase.

When a sine wave incremental encoder is used, as shown in FIG. 32 (a), the phase of one rotation can be obtained with high resolution by combining the pulse phase and the interpolation phase. If an error occurs in the combination of interpolation phases, the correct rotation phase and rotation speed cannot be obtained.
The present invention has been made to solve the above-mentioned problems, and the object of the present invention is to make an accurate one rotation using an incremental encoder regardless of whether the rotation direction is forward rotation or reverse rotation. It is possible to generate a reference, detect the rotational phase and rotational speed with high accuracy, and the motor with a sine wave incremental encoder or sine wave incremental encoder is not only stopped or at low speed but also at high speed. However, it is to always detect the pulse phase and the interpolation phase accurately and to obtain a rotational phase and a rotational speed with extremely high accuracy.

In the present invention, the above problem is solved as follows.
(1) A sine wave incremental encoder that outputs an incremental signal of an A phase signal and a B phase signal, which are two sine waves having a phase difference of 90 °, is used. Input to the speed detector. This sine wave incremental encoder outputs a plurality of cycles of an A-phase signal and the B-phase signal per rotation and a Z-phase signal that identifies one rotation .
The phase velocity detector includes an A-phase and B-phase comparator, a pulse extractor, a Z-phase comparator, an origin detector, and a pulse phase detector. The comparators include the A-phase signal and the B-phase signal. Then, a binarized rectangular A-phase signal and rectangular B-phase signal are generated and output to the pulse extractor.
The pulse extractor uses the rectangular A-phase signal and the rectangular B-phase signal to generate a normal rotation pulse signal synchronized with the clock signal when the sine wave incremental encoder rotates in the normal direction, and a reverse rotation pulse signal synchronized with the clock signal during the reverse rotation. Is extracted and output. In addition, a synchronized A phase signal and a synchronized B phase signal are output in which the rising and falling edges of the rectangular A phase signal and the rectangular B phase signal are synchronized with the clock signal. A binarized rectangular Z-phase signal is generated. The origin detector receives the normal rotation pulse and the reverse rotation pulse output from the pulse extractor and the rectangular Z-phase signal, and the origin detector outputs whether the normal rotation pulse is output or the reverse rotation pulse. The rotation direction of the sine wave incremental encoder is identified according to whether the sine wave incremental encoder is rotating, and when the sine wave incremental encoder is rotating in the forward rotation direction, a predetermined short period from the front or rear end of the rectangular Z-phase signal A reference origin signal having a pulse width is output, and when the sine wave incremental encoder is rotating in the reverse direction, a reference origin signal having a short predetermined pulse width is output from the rear end or the front end of the rectangular Z-phase signal. The pulse phase detector includes an up / down counter for counting and outputting a value sufficiently larger than a maximum pulse phase based on the number of cycles per rotation of the A phase signal and the B phase signal of the sine wave incremental encoder, and a selection unit. The forward rotation pulse and the reverse rotation pulse output from the pulse extractor are input to the up count terminal and the down count terminal of the up / down counter of the pulse phase detector, respectively, and the reset terminal of the up / down counter is The reference origin signal output from the origin detector is input, and the up / down counter counts up when the forward rotation pulse is input, counts down when the reverse rotation pulse is input, and outputs to the reset terminal. It is reset to zero when the reference origin signal is input.
The selection means outputs the count value as a pulse phase of the sine wave incremental encoder when the output of the up / down counter is positive, and the maximum pulse phase when the output of the up / down counter is negative. The sum of the maximum number of pulses obtained by adding 1 and the count value of the up / down counter is output as the pulse phase of the sine wave incremental encoder .

(2) phase velocity detecting apparatus according to claim 2 of the present invention, the phase velocity detecting apparatus according to claim 1, to an A / D converter and a controller.
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values.
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal by comparing the A-phase signal and the B-phase signal with a level Vh for determining the high level and a level Vl for determining the low level. The rectangular A-phase signal and the rectangular B-phase signal are generated from the signal, and in this case, Vh is equal to or higher than Vl.
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. The value and the B-phase digital value are continuously input, and the controller corrects the pulse phase as follows.
(i) When the sine wave incremental encoder is rotating in the normal direction, when the A phase digital value is positive and the synchro A phase signal is '0', a correction is performed to add 1 to the pulse phase; When the A-phase digital value is negative and the synchro A-phase signal is '1', correction is performed by adding 1 to the pulse phase.
Further, when the B-phase digital value is positive and the synchronized B-phase signal is “0”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is negative and the synchronized B-phase signal is “1”. When ', correction is performed by adding 1 to the pulse phase.
(ii) When the sine wave incremental encoder rotates in reverse, when the A-phase digital value is positive and the synchro A-phase signal is '0', correction is performed to subtract 1 from the pulse phase, When the A-phase digital value is negative and the synchro A-phase signal is “1”, correction is performed by subtracting 1 from the pulse phase.
When the B-phase digital value is positive and the synchronized B-phase signal is “0”, correction is performed by subtracting 1 from the pulse phase, and the B-phase digital value is negative and the synchronized B-phase signal is “1”. When ', correction is performed to subtract 1 from the pulse phase.

(3) phase velocity detecting apparatus according to claim 3 of the present invention, the phase velocity detecting apparatus according to claim 1, to an A / D converter and a controller.
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values.
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal by comparing the A-phase signal and the B-phase signal with a level Vh for determining the high level and a level Vl for determining the low level. The rectangular A-phase signal and the rectangular B-phase signal are generated from the signal, and in this case, the Vh is less than the Vl.
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. The value and the B-phase digital value are continuously input, and the controller corrects the pulse phase as follows.
(i) When the sine wave incremental encoder is rotating forward, when the A phase digital value is negative and the synchro A phase signal is '1', a correction is performed to subtract 1 from the pulse phase; When the A-phase digital value is positive and the synchro A-phase signal is “0”, correction is performed by subtracting 1 from the pulse phase.
Further, when the B-phase digital value is negative and the synchronized B-phase signal is “1”, correction is performed by subtracting 1 from the pulse phase, and the B-phase digital value is positive and the synchronized B-phase signal is “0”. When ', correction is performed to subtract 1 from the pulse phase.
(ii) When the sine wave incremental encoder rotates in reverse, when the A-phase digital value is negative and the synchro A-phase signal is '1', correction is performed to add 1 to the pulse phase, When the A-phase digital value is positive and the synchro A-phase signal is “0”, correction is performed by adding 1 to the pulse phase.
Further, when the B-phase digital value is negative and the synchronized B-phase signal is “1”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is positive and the synchronized B-phase signal is “0”. When ', correction is performed by adding 1 to the pulse phase.

(4) phase velocity detecting apparatus according to claim 4 of the present invention, the phase velocity detecting apparatus according to claim 1, to an A / D converter and a controller.
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values.
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal by comparing the A-phase signal and the B-phase signal with a level Vh for determining the high level and a level Vl for determining the low level. The rectangular A-phase signal and the rectangular B-phase signal are generated from the signal, and in this case, Vh is equal to or higher than Vl.
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. The value and the B-phase digital value are continuously input, and the controller corrects the pulse phase as follows.
(i) When the sine wave incremental encoder is rotating in the forward direction, the pulse phase is determined when the A phase digital value is zero, the B phase digital value is positive, and the synchro A phase signal is '0'. Correction for adding 1 is performed. When the A-phase digital value is zero, the B-phase digital value is negative, and the synchro A-phase signal is '1', correction for adding 1 is performed for the pulse phase.
Further, when the B-phase digital value is zero, the A-phase digital value is negative, and the synchronized B-phase signal is “0”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is zero. When the A-phase digital value is positive and the synchro B-phase signal is '1', correction is performed by adding 1 to the pulse phase.
(ii) When the sine wave incremental encoder rotates in reverse, the pulse phase is not corrected when the A-phase digital value is zero, and the pulse phase is also corrected when the B-phase digital value is zero. No correction is made for.

(5) the phase velocity detecting device according to claim 5 of the present invention, the phase velocity detecting apparatus according to claim 1, to an A / D converter and a controller.
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values.
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal by comparing the A-phase signal and the B-phase signal with a level Vh for determining the high level and a level Vl for determining the low level. The rectangular A-phase signal and the rectangular B-phase signal are generated from the signal, and in this case, the Vh is less than the Vl.
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. The value and the B-phase digital value are continuously input, and the controller corrects the pulse phase as follows.
(i) When the sine wave incremental encoder is rotating forward, the pulse phase is not corrected when the A-phase digital value is zero, and the pulse is also output when the B-phase digital value is zero. No correction is made for the phase.
(ii) When the sine wave incremental encoder is rotating in reverse, when the A phase digital value is zero, the B phase digital value is negative and the synchro A phase signal is '1', the pulse phase is 1 When the A-phase digital value is zero, the B-phase digital value is positive, and the synchro A-phase signal is “0”, correction is performed to add 1 to the pulse phase.
Further, when the B phase digital value is zero, the A phase digital value is positive, and the synchronized B phase signal is “1”, correction is performed by adding 1 to the pulse phase, and the B phase digital value is zero. When the A-phase digital value is negative and the synchronized B-phase signal is “0”, correction is performed by adding 1 to the pulse phase.

( 6 ) The phase velocity detection device according to claim 6 of the present invention is the phase velocity detection device according to claim 2, 3, 4 or 5, wherein a reference counter and a data latch for counting pulses output from the transmitter are provided. .
The reference value output from the reference counter, the pulse phase, the synchronized A-phase signal, the synchronized B-phase signal, the A-phase digital value, and the latch command synchronized with the edge of the pulse output from the transmitter The B phase digital value is latched and input to the controller at predetermined time intervals.
The controller detects a change amount of the rotation phase of the sine wave incremental encoder from the change amount of the output value of the reference counter in the time interval, and detects the change amount of the sine from the change amount of the time interval and the rotation phase. Calculates and detects the rotation speed of the wave incremental encoder.

In the present invention, it is possible to always detect the rotation phase and the rotation speed with high accuracy even when the sine wave incremental encoder or the motor attached with the sine wave incremental encoder is stopped or rotating at a low speed as well as at a high speed. It becomes.
As a result, it is possible to realize high-precision synchronous control among a plurality of motors during high-speed rotation and high-speed positioning control.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
1, 5, and 10 illustrate an embodiment related to claim 1 , FIG. 13 illustrates an embodiment related to claims 2 , 3 , 4, and 5 , and FIG. 29 illustrates an embodiment related to claim 6 . Is described.

  FIG. 1 is a diagram illustrating the overall configuration of the first embodiment, and FIGS. 2, 3 and 4 illustrate the first embodiment in more detail. First, in FIG. 1, 1a is a sine wave incremental encoder, 2a is a phase velocity detection device, the phase velocity detection device 2a includes 3, 5, and 6 devices, 3 is a comparator, and 5 is a reference clock having a constant frequency. Is a pulse extractor according to this embodiment, which will be described in turn.

  The comparator 3 converts the A-phase and B-phase sine waves output from the sine wave incremental encoder 1a into binary rectangular A-phase signals and rectangular B-phase signals of '0' and '1'. The rectangular A phase signal and the rectangular B phase signal are connected to the PA input and PB input of the pulse extractor 6, and the transmitter 5 supplies a reference clock CLK to the CLK input of the pulse extractor 6. Next, the Q1 output and Q2 output of the pulse extractor 6, for example, when the sine wave incremental encoder 1a rotates in the normal rotation direction, the forward rotation pulse corresponding to the rotation is sent to the Q1 output, and the sine wave incremental encoder 1a When rotating in the reverse direction, a reverse pulse corresponding to the rotation is output to the Q2 output. The QA output and the QB output of the pulse extractor 6 are the Q1 output for sending the forward rotation pulse corresponding to the rotation, or the PA input and the PB for generating the Q2 output for sending the reverse rotation pulse. Synchronized A-phase signal QA and synchronized B-phase signal QB are maintained.

Next, the operation of the pulse extractor 6 when the sine wave incremental encoder 1a rotates in the forward rotation direction will be further described with reference to FIG.
(A) of FIG. 2 shows the temporal transition of the output of the A phase and the B phase when the sine wave incremental encoder 1a is rotating forward, and for the forward rotation, for example, the B phase is advanced by 90 ° from the A phase. The sine wave incremental encoder 1a is rotated once to generate N cycles of A phase and B phase sine waves.
FIG. 2 (b) shows the temporal transition of the output of the A-phase comparator 3. The comparator 3 compares the A-phase sine wave input with approximately zero and outputs two values of '0' and '1'. A rectangular A-phase signal, which is a value signal, is output and becomes the PA input of the pulse extractor 6. Similarly, FIG. 2C shows the temporal transition of the rectangular B-phase signal output from the B-phase comparator 3 and the PB input of the pulse extractor 6. Here, (1) and (2) in (b) of FIG. 2 indicate the rising and falling of the PA input, respectively, and (3) and (4) in (c) of FIG. 2 are the PB input. The rise and fall of each are shown, and the description thereof will be described later.

  Further, (d) of FIG. 2 shows a temporal transition of the reference clock CLK output from the transmitter 5, and the reference clock CLK is connected to the CLK input of the pulse extractor 6. Here, (d) in FIG. 2 is shown so that it can be seen in comparison with (c) in FIG. 2 (a) to FIG. 2 (c) for explanation. In a), when N per revolution is, for example, 512 cycles and the rotational speed is 1800 rpm (revolutions per minute), the frequency of the A phase or B phase sine wave in FIG. 2A is 15.36 KHz, The frequency of the reference clock of the transmitter 5 shown in FIG. 2D is, for example, 20 MHz. Thus, the frequency of the transmitter 5 is selected sufficiently higher than the frequency of the sine wave output from the A phase and B phase of the sine wave incremental encoder 1a.

Next, FIG. 2E shows a state in which a normal rotation pulse corresponding to the rotation is output to the Q1 output of the pulse extractor 6 when the sine wave incremental encoder 1a rotates in the normal rotation direction. FIG. 2 (e) is an example of a pulse frequency multiplied by 4 times the input frequency shown in FIG. 2 (a). At this time, if a practical example is shown, in FIG. When N is, for example, 512 cycles, the sine wave incremental encoder 1a generates 2048 forward rotation pulses at 512 × 4 multiplications in one rotation.
Further, as described above, FIG. 2E shows an example of a pulse frequency of x4 times the input frequency shown in FIG. 2A, but it may be x1 or x2. Here, FIG. 2 (f) shows the state of the Q2 output that outputs the reverse pulse of the pulse extractor 6 when the sine wave incremental encoder 1a rotates in the reverse direction. The Q2 output does not change when

  2 (g) and 2 (h) show temporal transitions of the synchro A phase signal QA and the synchro B phase signal QB output from the pulse extractor 6, and output the pulse corresponding to the rotation. The state of the PA input and the PB input that generated the Q1 output or the Q2 output is held and output. More specifically, the rising edge of the PA input indicated by (1) in FIG. 2B is synchronized with the reference clock CLK in FIG. 2D, and the time t1 in FIG. The forward rotation pulse at is generated. Then, as shown in FIG. 2 (g), which is accurately synchronized with the normal rotation pulse by the reference clock CLK of FIG. 2 (d), the synchro A phase signal QA becomes “1”. Further, the falling edge of the PA input indicated by (2) in FIG. 2B is synchronized with the reference clock CLK, and at the same time as generating the normal rotation pulse at the time t2 in FIG. As shown in (g), the synchro A-phase signal QA becomes “0”. Similarly, the rise and fall of the PB input in (3) and (4) of FIG. 2 (c) are synchronized with the reference clock CLK, and forward rotation pulses at times t3 and t4 in FIG. 2 (e). As shown in FIG. 2 (h), the synchronized B-phase signal QB changes to '1' and '0'.

  That is, in this embodiment, changes in the synchro A phase signal QA and the synchro B phase signal QB output from the pulse extractor 6 shown in FIGS. 2 (g) and (h) are shown in FIG. 2 (e). 2 is synchronized with the normal rotation pulse shown in FIG. 2 to determine whether the phase that generated the normal rotation pulse of the Q1 output in FIG. 2E is caused by the A phase or the B phase. By monitoring the phase signal QA and the synchro B phase signal QB, it is possible to always recognize correctly. In the above description, the pulse generated at times t3 and t4 at the rise (3) and fall (4) of PB has been described. However, the pulse is illustrated between t1 and t2, and is illustrated between t3 and t4. The pulse generated is also a pulse generated at the rise and fall times of PB.

  FIG. 3 illustrates the operation of the pulse extractor 6 when the sine wave incremental encoder 1a rotates in the reverse direction. FIG. 3A shows the temporal transition of the output of the A phase and the B phase when the sine wave incremental encoder 1a reverses, and the A phase is 90 ° from the B phase in place of FIG. Advance. 3A to 3H, the same reference numerals as those in FIGS. 2A to 2H denote the same input and output of the pulse extractor 6, and the description thereof is omitted.

  Here, (5) and (6) in FIG. 3 (b) show the rise and fall of the PA input of the pulse extractor 6, respectively, and (7) and (8) in (c) of FIG. ) Indicates the rise and fall of the PB input, respectively. The rising edge of the PA input indicated by (5) in FIG. 3 (b) is synchronized with the reference clock CLK in FIG. 3 (d) to generate a reverse pulse at time t5 in FIG. 3 (f). . Then, the synchronized A-phase signal QA shown in (g) of FIG. 3 which is accurately synchronized with the reverse pulse by the reference clock CLK of (d) of FIG. 3 becomes “1”. Further, the falling edge of the PA input indicated by (6) in FIG. 3B is synchronized with the reference clock CLK, and at the same time as generating a reverse pulse at time t6 in FIG. As shown in (g), the synchronized A-phase signal QA becomes “0”. Similarly, the rise and fall of the PB input in (7) and (8) of FIG. 3 (c) are synchronized with the reference clock CLK, and the reverse pulses at time t7 and t8 in FIG. Simultaneously with the generation, the synchro B-phase signal QB changes to “1” and “0” as shown in FIG. During reverse rotation, the Q1 output of the forward rotation pulse of the pulse extractor 6 shown in FIG. 3 (e) does not change.

  Thus, in this embodiment, when rotating in the reverse direction as in the normal rotation, the synchro A phase signal QA which is the output of the pulse extractor 6 shown in (g) and (h) of FIG. The change of the synchro B phase signal QB is accurately synchronized in time with the reverse pulse shown in FIG. 3 (f), so that the phase that generates the reverse pulse of the Q2 output in FIG. By monitoring the synchro A-phase signal QA and the synchro-B phase signal QB, it is possible to always accurately recognize whether it is caused by the above or the B phase.

  Next, FIG. 4 shows an embodiment of the pulse extractor 6. In FIG. 4, 6 is a pulse extractor, and PA input, PB input, CLK input, Q1 output, Q2 output, QA output and QB output are the same as those shown in FIG. . 601, 603, 605, 607 and 609 are NOT gates, 602, 604, 606, 608, 613, 614, 615 and 616 are D flip-flops, 610 is an AND gate, and 611 and 612 are OR gates. It is. In the following description of this embodiment, it is assumed that the CLK input of various flip-flops performs a latch operation at the rising edge of the input signal.

First, the D flip-flops 602 and 604 and NOT gates 603 and 605 detect rising and falling of the PA input. Similarly, the D flip-flops 606 and 608 and NOT gates 607 and 609 are connected to the PB. Used to detect the rise and fall of the input. Here, the Q output of the D flip-flop 602 is expressed as (602Q) and the output of the NOT gate 603 is expressed as (/ 602Q). In the same way, the output of the AND gate 610 attached with (1) executes the following logical operation.
(1): (602Q) ∩ (/ 604Q) ∩ (606Q) ·················································· (3) 2 detects the rising edge of (1) in FIG. 2 (b), and further detects forward rotation from the third term (∩ (606Q)) because the B phase is “1”. The forward rotation pulse at time t1 in (e) is generated. Similarly, each of the AND gates 610 to which (2) to (4) are attached in FIG. 4 executes the logical operations shown in the following equations (4) to (6), respectively. Then, rising or falling is detected, and forward rotation is detected by the third term, and forward rotation pulses are generated at times t2, t3, and t4 in FIG. Here, it should be noted that (1) to (4) given in (b) and (c) in FIG. 2 correspond to (1) to (4) given to the AND gate 610 in FIG.
(2): (/ 602Q) ∩ (604Q) ∩ (/ 606Q) · · · · · · · · ·
(3): (606Q) ∩ (/ 608Q) ∩ (/ 602Q) · · · · · · · · · · · · (5)
(4): (/ 606Q) ∩ (608Q) ∩ (602Q) Equation (6) And the output of the AND gate 610 of (1) to (4) passes through the OR gate 611. The D flip-flop 613 sends a normal rotation pulse to the Q1 output in synchronization with the rising edge of the CLK input.

On the other hand, each of AND gates 610 with (5) to (8) performs the logical operation of the following equations (7) to (10), respectively, and (5) of (b) and (c) of FIG. ) To (8) are detected, and reverse pulses are generated from time t5 to time t8 in FIG. 3 (f).
(5): (602Q) ∩ (/ 604Q) ∩ (/ 606Q) ····························
(6): (/ 602Q) ∩ (604Q) ∩ (606Q) ··············································
(7): (606Q) ∩ (/ 608Q) ∩ (602Q) ··············· (9)
(8): (/ 606Q) ∩ (608Q) ∩ (/ 602Q) ··················································· (10) The D flip-flop 614 sends a reverse pulse to the Q2 output in synchronization with the rising edge of the CLK input.

  Further, the reason why the output of the equations (3) to (10) becomes '1' depends on the change of the output of the D flip-flop 602 or 606 of the first item of these equations. The outputs of the D flip-flops 602 and 606 are sent to the outputs of the synchronized A-phase signal QA and the synchronized B-phase signal QB via the D flip-flops 615 and 616, respectively. The D flip-flops 615 and 616 and the D flip-flops 613 and 614 operate in synchronization with the rise of the same CLK signal. As a result, the present embodiment binarizes and holds the A phase and B phase of the sine wave incremental encoder 1a synchronized in time with the normal rotation pulse and the reverse rotation pulse transmitted from the Q1 output and the Q2 output. The synchronized A-phase signal QA and the synchronized B-phase signal QB are transmitted, and whether the phase that generated the forward pulse and the reverse pulse is caused by the A phase or the B phase, the synchronized A phase signal QA and It is possible to accurately recognize the sync B-phase signal QB by monitoring.

In FIG. 4, the NOT gate 601 inverts the reference clock CLK, and supplies a clock to the CLK inputs of D flip-flops 602, 604, 607, and 609 that detect rising and falling of the PA input and PB input. The D flip-flop is supplied so that a normal rotation pulse and a reverse rotation pulse that can be obtained depending on the output of each AND gate 610 are generated in synchronization with the falling edge of the reference clock CLK, and are synchronized with the rising edge of the reference clock CLK. This is provided for the sake of convenience in order to ensure a sufficient data setup time for the D input of the groups 613, 614, 615 and 616.
The OR gates 611 and 612 shown in FIG. 4 are shown as an example in which the A phase and the B phase of the sine wave incremental encoder 1a are multiplied by x4. Instead, the OR gates 611 and 612 are multiplied by x2 or x1. There may be. Also, the Q1 output and the Q2 output are shown in the embodiment for outputting the forward rotation pulse and the reverse rotation pulse, respectively. When the Q2 output is normal rotation, for example, “0” is output, and when the Q2 output is reverse rotation, “1” is output. The sine wave incrementally synchronized with the Q1 output and the Q2 output accurately in time. The synchro A phase signal QA and the synchro B phase signal QB obtained by binarizing the A phase and the B phase of the encoder 1a may be transmitted.

  FIG. 5 is a diagram for explaining the overall configuration of the second embodiment, and FIGS. 6, 7, 8, and 9 explain the second embodiment in more detail. In FIG. 5, 1b is a sine wave incremental encoder to which a Z-phase signal for identifying one rotation is added to the sine wave incremental encoder 1a of FIG. 1, 2b is a phase velocity detector, 4 is a comparator, and 7 is a main encoder. In the origin detector according to the embodiment, reference numerals 3, 5 and 6 denoted by the same reference numerals as those in FIG.

  First, the sine wave incremental encoder 1b outputs the Z-phase signal, which will be described with reference to FIG. FIG. 6 illustrates the signal output from the sine wave incremental encoder 1b, and FIG. 6 (a) shows the temporal transition of the output of the A phase and the B phase as in FIG. 2 (a). Will be omitted. Next, FIG. 6B shows the temporal transition of the output of the Z phase output from the sine wave incremental encoder 1b, for example, with the Low level set to 0V and the High level set to 5V. As shown in FIG. 6 (b), the Z phase becomes a high level for each rotation and identifies one rotation. In FIG. 5, the output of the Z phase of the sine wave incremental encoder 1b is shaped by the comparator 4 built in the phase velocity detector 2b, and the waveform is shaped into a binary Z phase of '0' and '1'. A signal is sent to the PZ input of the origin detector 7 described later.

  Next, the origin detector 7 in FIG. 5 has a P1 input, a P2 input, a PZ input, a CLK input, and a QZ output, and the P1 input receives the normal rotation sent from the Q1 output of the pulse extractor 6. A pulse is input, and the reverse pulse from the Q2 output is input to the P2 input. Further, as described above, the output of the comparator 4 is input to the PZ input of the origin detector 7, and the reference clock CLK from the transmitter 5 is input to the CLK input. The rectangular Z-phase signal input to the PZ input has a wide or indefinite pulse width. However, when the origin detector 7 rotates in the forward direction or the reverse direction, An accurate reference origin signal having a short pulse width generated at the same phase of the sine wave incremental encoder 1b is transmitted from the QZ output.

  Next, the operation of the origin detector 7 will be described in more detail with reference to FIG. First, FIG. 7A shows the temporal transition of the outputs of the A phase and the B phase when the sine wave incremental encoder 1b rotates in the normal rotation and reverse rotation directions. After t3. FIG. 7B shows the temporal transition of the Z-phase output of the sine wave incremental encoder 1b in comparison with the outputs of the A-phase and B-phase of FIG. Therefore, after the Z phase is output from time t1 to t2 at the time of forward rotation, the rotation direction is quickly reversed at time t3. Here, in FIG. 7B, it should be noted that the phase of the sinusoidal incremental encoder 1b at the time t1 during forward rotation is the same as the phase at the time t5 during reverse rotation. Similarly, it should be noted that the phase of the sine wave incremental encoder 1b at time t2 at the time of forward rotation is the same as the phase at time t4 at the time of reverse rotation.

  Next, (c) of FIG. 7 shows the time transition of the CLK input of the origin detector 7, and one cycle of the CLK input is Tosc. FIG. 7 (d) shows the temporal transition of the QZ output of the origin detector 7. As shown in the figure, during normal rotation, the pulse width is Tosc in synchronization with the rise of the Z phase at time t1. The reference origin signal is generated, and at the time of reverse rotation, the reference origin signal having a pulse width of Tosc is generated in synchronization with the fall of the Z phase at time t5 and used as the QZ output. Thus, the present embodiment generates a reference origin signal having a pulse width defined in a short time even when the pulse width of the Z phase output from the sine wave incremental encoder 1b is wide, and also during forward rotation. Even in the case of reverse rotation, the reference origin signal is accurately generated with the same phase of the sine wave incremental encoder 1b.

  An embodiment of the origin detector 7 will be described with reference to FIG. In FIG. 8, the origin detector 7, P1 input, P2 input, PZ input, CLK input and QZ output are the same as those described in FIG. 5, and the description thereof is omitted. 701, 705, 706 and 707 are NOT gates. 702 is a JK flip-flop, 703 and 704 are D flip-flops, 708 and 709 are AND gates, and 710 is an OR gate. First, the JK flip-flop 702 uses the P1 input of the forward pulse and the P2 input of the reverse pulse output from the pulse extractor 6 of FIG. 5 as the K and J inputs, respectively, so that the Q output becomes the sine wave incremental encoder. The rotation direction of 1b is detected, and is 0 for forward rotation and 1 for reverse rotation. When forward rotation, an after-mentioned AND gate 708 is selected via a NOT gate 705, and when reverse rotation, an later-described AND gate 709 is selected. Here, when the forward rotation pulse and the reverse rotation pulse of the K and J inputs change in synchronization with the rising edge of the reference clock CLK, in order to secure the data setup time of the K and J inputs, the NOT gate 701 is used for convenience. And the rotation direction is sent to the Q output of the JK flip-flop 702 in synchronization with the fall of the reference clock CLK.

  Similarly, in FIG. 8, the D flip-flops 703 and 704 connected in series are for detecting the rise and fall of the rectangular Z-phase signal of PZ input, and the AND gate 708 is the D flip-flop. A reference origin signal for forward rotation is generated from the outputs of 703 and the NOT gate 706, and the AND gate 709 generates a reference origin signal for reverse rotation from the outputs of the D flip-flop 704 and the NOT gate 707. The outputs of the AND gates 708 and 709 are combined into one according to the OR gate 710, and the reference origin signal is output to the QZ output.

  The embodiment of FIG. 8 will be further described with reference to FIG. FIG. 9 illustrates the operation of the origin detector 7. FIG. 9 (a) shows the temporal output of the A phase and B phase when the sine wave incremental encoder 1b rotates in the forward and reverse directions. It is assumed that the rotation is normal until time t1 and rotates in the reverse direction after time t1. FIG. 9B shows the P1 input which is a normal rotation pulse of the origin detector 7, which is the same as the signal shown in FIG. 2E and will not be described. Similarly, FIG. (C) shows the P2 input which is a reverse pulse of the origin detector 7, which is the same as the signal shown in (f) of FIG. 3 and will not be described. 9D and 9E show the PZ input and QZ output of the origin detector 7, respectively.

Here, the process of generating the QZ output of the reference origin signal of (e) of FIG. 9 by expanding the period of time T1 and T2 of FIG. 9 will be described. 9 (f), (g) and (h) are enlarged views of (b), (c) and (d) of FIG. 9, and (i) of FIG. 9 is inputted with the reference clock CLK. In the practical example, when the reference clock CLK is 20 MHz, Tosc is only 0.05 μS.
Next, (j) in FIG. 9 shows the output of the JK flip-flop 702 that detects the rotation direction. For example, the forward rotation pulse at time t40 in FIG. Is set to '1' at time t51 by the reverse pulse at time t50 in FIG. 9 (g). Thus, the output of the JK flip-flop 702 indicates the rotation direction of the sine wave incremental encoder 1b, and in the forward rotation at time T1, the AND gate 708 is selected via the NOT gate 705, and at time T2. In the case of reverse rotation, the AND gate 709 is selected.

  9 (k) and (l) show the outputs of the D flip-flops 703 and 704. The D flip-flops 703 and 704 are shifters of the PZ input. The rising edge of the PZ input at time t60 changes from “0” to “1” at time t61 in FIG. 9K and at time t62 in FIG. The output of the AND gate 708 selected at the time of normal rotation becomes “1” as shown from time t61 to time t62 in FIG. Similarly, the fall of the PZ input at time t70 in FIG. 9 (h) starts from “1” at time t71 in FIG. 9 (k), and at time t72 in FIG. 9 (l). The output of the AND gate 709 selected at the time of reverse rotation becomes “1” as shown from time t71 to t72 in FIG. 9 (n).

  The outputs of the AND gates 708 and 709 are output to the QZ output by the OR gate 710 as a reference origin signal having a pulse width Tosc as shown in FIG. As described above, the generation of the QZ output shown in FIG. 9E has been described with reference to FIGS. Here, in FIGS. 9A and 9E, the phase of the sinusoidal incremental encoder 1b at time t2 when QZ becomes '1' during forward rotation and QZ becomes '1' during reverse rotation. The phases of the sine wave incremental encoder 1b at the time t3 are equal, and thereby the origin of one rotation of the sine wave incremental encoder 1b is detected equally during forward rotation and reverse rotation. Further, as shown in FIG. 9 (d), even if the pulse width of PZ input “1” is long, the QZ output serving as the reference origin signal shown in FIGS. 9 (e) and 9 (o) is The pulse width of the reference clock CLK is sufficiently short as Tosc, thereby detecting the origin of one rotation of the sine wave incremental encoder 1b with high accuracy. In the above description, the reference origin signal is obtained from the front end of the Z-phase signal at the forward rotation and from the rear end at the reverse rotation as shown in FIGS. Obviously, it may be obtained from the rear end of the Z-phase signal during forward rotation and from the front end during reverse rotation.

  FIG. 10 is a diagram illustrating the overall configuration of the third embodiment, and FIGS. 11 and 12 illustrate the third embodiment in more detail. First, in FIG. 10, 2c is a phase velocity detector, 8 is a pulse phase detector according to this embodiment, and 1b, 3, 4, 5, 6 and 7 having the same symbols as those in FIG. 5 have the same functions. I will omit the explanation.

  The phase velocity detector 2c incorporates a pulse phase detector 8 according to this embodiment, and the pulse phase detector 8 has a P1 input, a P2 input, a PZ input, and a pulse phase output of j-bit data size, A forward rotation pulse transmitted from the Q1 output of the pulse extractor 6 is input to the P1 input, and a reverse rotation pulse from the Q2 output of the pulse extractor 6 is input to the P2 input. In addition, an accurate reference origin signal of the sine wave incremental encoder 1b is input to the PZ input from the origin detector 7 regardless of whether the rotation direction is normal rotation or reverse rotation. Thereby, the pulse phase detector 8 outputs an accurate pulse phase of the sine wave incremental encoder 1b even when rotating in the forward direction and the reverse direction.

FIG. 11 shows an embodiment of the pulse phase detector 8. In FIG. 11, 801 is an up / down counter, 802 is a coefficient unit, 803 is an adder, and 804 is a selector. The up / down counter 801 counts up the P1 input by UP input and down-counts the P2 input by DOWN input. The P1 input has the pulse described in FIG. 2 (e). The forward rotation pulse sent from the Q1 output of the extractor 6 is inputted. Here, in order to facilitate the following explanation, a practical example will be shown. The sine wave incremental encoder 1b generates a 512-cycle A-phase or B-phase sine wave per rotation, which is multiplied by x4. If a normal rotation pulse is generated, the maximum number of pulses per rotation is 2048.
By counting the forward rotation pulses, the rotation phase of the sine wave incremental encoder 1b can be detected in the range of 0 for one rotation to 2047 for the maximum pulse phase. When 2047 is expressed in hexadecimal, it is 7FFh, and in binary, 111, 1111, and 1111b have a maximum data size of 11 bits. At this time, the maximum count value counted by the up / down counter 801 is 11 It is larger than the bits, for example, 16 bits. In the present invention, when a numerical value is expressed in hexadecimal, 'h' is added to the end of the numerical value, and when a numerical value is expressed in binary number, 'b' is added to the end of the numerical value.

Next, the P2 input is inputted with a reverse pulse sent from the Q2 output of the pulse extractor 6 described in FIG. 3 (f), and a signal to the DOWN input of the up / down counter 801 Become. When the sine wave incremental encoder 1b rotates in the reverse direction, if the up / down counter 801 has a 16-bit data size, the count value is counted down as follows, for example.
0001h
0000h
FFFFh
FFFEh = 1111, 1111, 1111, 1110b (11) Here, since the data size of the up / down counter 801 is selected to be sufficiently large, the count value does not become zero due to the down count. The RST input, which will be described later, is reset to zero every rotation, and as a result, the most significant bit (hereinafter referred to as MSB) of the count value is always a sign bit.

  Summarizing the above description of the count value output by the up / down counter 801, the maximum value of the pulse phase detected by one rotation of the sine wave incremental encoder 1b is taken as the i-bit data size. For example, the count value counted by the up / down counter 801 has a data size of j bits sufficiently exceeding i bits.

  Next, in FIG. 11, the j-bit count value output from the up / down counter 801 is sent to the selector 804 and the adder 803. Here, the flow of numerical data in FIG. 11 is indicated by a bold line, and the same applies to the description of other figures of the present invention. Then, if the maximum pulse phase of the sine wave incremental encoder 1b is Pmax, the coefficient unit 802 outputs a constant that is the maximum number of pulses per rotation that is obtained by adding 1 to this (Pmax + 1). If this is shown by a specific example, the coefficient unit 802 outputs the maximum number of pulses 2048 when the maximum pulse phase Pmax is 2047.

  The adder 803 outputs the data obtained by adding the output of the up / down counter 801 and the output of the coefficient unit 802 to the selector 804, and the selector 804 changes the A input from A1 to Aj as described above. The count value output from the up / down counter 801 is input, and the data output from the adder 803 is input to the B input composed of B1 to Bj. The selector 804 selects the A input when “0” is input to the S input, and selects the B input when “1” is input to the S input to change the Q output from Q1 to Qj. Thus, the pulse phase is always detected correctly both when the sine wave incremental encoder 1b rotates in the forward direction and when it rotates in the reverse direction.

Next, the operation of the embodiment of FIG. 11 will be further described with reference to FIG. 12A shows the temporal transition of the forward rotation pulse of the P1 input, and it is assumed that the forward rotation pulse is input until time t3 and after time t8, and FIG. 12B shows the reverse rotation of the P2 input. FIG. 12 (c) shows the state of the PZ input and shows one rotation at times t1, t2, t5, t6 and t9. It is assumed that the origin is detected and becomes “1”.
FIG. 12 (d) shows the count value output by the up / down counter 801. In normal rotation, for example, it counts up from time t1, reaches the maximum pulse phase Pmax at time t2, and at the time of the PZ input. The counter continues to count up while being reset to zero, and at the time of reverse rotation, it counts down from time t4. At time t5, the count value becomes zero and also becomes zero by the PZ input.
After time t5, the countdown continues in the negative direction as described in the above equation (11), reaches the negative maximum pulse phase (−Pmax) at time t6, and is once reset to zero by the PZ input. Continue the countdown. Thus, as shown in FIG. 12 (d), the output of the up / down counter 801 detects the phase of the sine wave incremental encoder 1b positively or negatively.

Next, (e) in FIG. 12 shows the one-bit output of Qj which is the MSB of the output of the up / down counter 801, that is, the S input of the selector 804, and the Qj output is shown in (d) of FIG. When the indicated count value is positive, it is “0”, and when it is negative, it is “1”.
12 (f) shows the temporal transition of the output of the selector 804, that is, the pulse phase output from the pulse phase detector 8. The S input of the selector 804 is '0' until time t5. As a result, the output of the up / down counter 801 is directly used as the pulse phase as the output of the selector 804. After time t5, the S input of the selector 804 is '1', so that the output of the adder 803 is pulsed. The phase is the output of the selector 804.
Here, if the output value of the coefficient multiplier 802 is (Pmax + 1),
(Pmax + 1) −output of up / down counter 801... (12) is the output of the adder 803, and the pulse phase is a positive number as shown after time t5 in FIG. Obtainable.
In addition, when the PZ input becomes '1' at time t6 in FIG. 12 (f), the pulse phase should be preset to the maximum pulse phase in the case of reverse rotation. As shown at time t6, the up / down counter 801 simply resets to zero as in the normal rotation, and realizes the pulse phase detector of the sine wave incremental encoder 1b with a simple configuration.

Thus, the present embodiment is characterized in that the data size of the count value of the up / down counter 801 is sufficiently larger than the maximum pulse phase, whereby the maximum pulse phase of the sine wave incremental encoder 1b is different. When used, it is possible to detect the pulse phase only by changing the value of the coefficient unit 802. When the count value of the up / down counter 801 is negative, the MSB of the count value is used. The phase according to the equation (12) is used as a pulse phase, and a positive pulse phase is always obtained not only during forward rotation but also during reverse rotation.
Further, there is a feature that the count value of the up / down counter 801 may be reset to zero by the PZ input not only in the normal rotation but also in the reverse rotation direction. The PZ input of the pulse phase detector 8 has an extremely pulse width generated at the same phase of the sine wave incremental encoder 1b during the forward rotation and the reverse rotation described in FIG. Since a narrow reference origin signal is supplied, there is a feature that the rotational phase can be detected with extremely high accuracy.

FIG. 13 illustrates the overall configuration of the fourth embodiment related to claims 2 , 3 , 4, and 5 of the present invention, and FIG. 14 illustrates the overall operation of FIG. 13. FIG. First, in FIG. 13, 2d uses a phase velocity detector, 9 uses a microprocessor or digital signal processor, but in the following description, it is called a microcontroller, 10 is a parallel output port, 11 and 12 are The parallel input ports 13 and 14 are A / D converters, and those having the same symbols as those in FIG. 10 have the same functions and will not be described.

D1 to Dn of the microcontroller 9 represent a data bus, C represents a control signal such as a read signal, a write signal, and an address, and the parallel output port 10 and the parallel input ports 11 and 12 with D are data inputs. , Q indicates data output, and C indicates control signal input.
The A / D converters 13 and 14 respectively receive the A phase signal and the B phase signal of the sine wave incremental encoder 1b. When the ST input becomes active, the A / D converters 13 and 14 execute A / D conversion to generate an analog sine wave. An A-phase digital value and a B-phase digital value obtained by converting a certain A-phase signal and B-phase signal into digital values are sent from D1 to Dk output, and C indicates an input of a control signal.
The microcontroller 9 outputs the pulse phase output from the pulse phase detector 8 via the parallel input port 11 and the synchro A phase signal and synchro B output from the pulse extractor 6 via the parallel input port 12. For the phase signal, the ST input of the A / D converters 13 and 14 is made active via the parallel output port 10 and the A phase digital value and the B phase digital value are continuously input. Thereby, the microcontroller 9 detects the rotational phase of the sine wave incremental encoder 1b with high accuracy. Here, the C output of the microcontroller 9, the C input of the parallel output port 10, the C input of the parallel input ports 11 and 12, and the C input of the A / D converters 13 and 14 are read, write signals, address signals, etc. Usually, it represents a control signal when the microcontroller is used, and a description thereof will be omitted.

Next, before describing the present invention from claim 2, the entire operation of FIG. 13 will be described in advance with reference to FIG. FIG. 14A shows the temporal transition of the A-phase and B-phase outputs of the sine wave incremental encoder 1b, and the A-phase digital values and B converted as the conversion values of the A / D converters 13 and 14 at time t3. The phase digital values are a1 and b1, respectively.
Corresponding to (a) of FIG. 14, (b) and (c) of FIG. 14 show temporal transitions of the synchro A phase signal QA and synchro B phase signal QB output from the pulse extractor 6. 14D shows the time transition of the reference origin signal QZ output from the origin detector 7, and FIG. 14E shows the time transition of the pulse phase output from the pulse phase detector 8. FIG. Indicates.
Then, QZ becomes '1' at time t4 in FIG. 14 (d), and at this time, the pulse phase is reset to zero in FIG. 14 (e). Further, in FIG. 14 (e), the pulse phase is set to (c-4) at time t1, and thereafter, +1 is incremented with QA in FIG. 14 (b) and QB in FIG. 14 (c). The counter counts up to (c + 2) at time t2, (c + 6) at time t3, and reaches zero at time t4 as described above. 14 (e) shows an example in which the pulse phase is detected by multiplying one cycle of the A phase and the B phase of the sine wave incremental encoder 1b by four for convenience.

Next, (f) of FIG. 14 schematically shows temporal transition of the virtual interpolation phase of the sine wave incremental encoder 1b, and (g) of FIG. 14 shows the sine wave incremental encoder. The timing which detects the rotational phase of 1b is shown.
First, the pulse phase shown in (e) of FIG. 14 is obtained by multiplying one cycle of the A phase and the B phase of the sine wave incremental encoder 1b by four, and (f) of FIG. The virtual temporal transition of the interpolation phase of the least significant bit of the pulse phase (less than one quarter of one cycle of the A phase and the B phase) is shown.
To explain this further, the section shown at time T3 in FIG. 14A is a quarter of one cycle, and the interpolation phase of this section is as shown at time T3 in FIG. 14F. It changes between zero and αmax.
The microcontroller 9 also executes various jobs such as control of an electric motor (not shown in FIG. 13), and the rotation phase of the sine wave incremental encoder 1b is detected for each scan. It is assumed that the processing is performed at times t1, t2, and t3 shown in FIG.
For detecting the rotational phase, the microcontroller 9 detects the pulse phase output from the pulse phase detector 8, the A phase digital value and the B phase digital value output from the A / D converters 13 and 14. The interpolation phase is detected by obtaining, for example, α from the a1 and b1 input at time t3 in FIG.
Thus, the pulse phase is detected as a coarse phase and the interpolation phase is detected as a fine phase, and the rotational phase of the sine wave incremental encoder 1b shown in FIG. 32A is obtained with extremely high accuracy.

Here, in order to obtain the rotational phase of the sine wave incremental encoder 1b with extremely high accuracy, for example, at time t3 in FIG. 14E, the combination of the pulse phase (C + 6) and the interpolation phase α is correctly detected. Even when there are variations in the electronic components constituting the phase velocity detection device 2d and when the sine wave incremental encoder 1b rotates at a high speed, the pulse phase is set at the beginning of time T3 ( C + 5) and at the time of the end of time T3, it should not be erroneously detected as (C + 7).
To a clear explanation for Example 4 As described above, although the overall operation of the Figure 13 at the beginning that has been described with reference to FIG. 14, sequentially from the invention relates to claim 2 below description I do.

FIG. 15 illustrates the operation of the comparator 3 in FIG. 13. FIG. 15 (a) shows the temporal transition of the output of the A phase and the B phase when the sine wave incremental encoder 1b is rotating forward. Correspondingly, (b) and (c) of FIG. 15 show the sync A phase signal QA and the sync B phase signal QB in which the outputs of the A phase and B phase comparators 3 are held by the pulse extractor 6. Shows the time transition.
The comparator 3 is “1” when the input is Vh or more and becomes “0” when the input is less than Vl. FIG. 15 shows the operation when Vh is greater than Vl. For example, since the A phase of the sine wave incremental encoder 1b exceeds Vh at time t1 in FIG. 15A, the synchro A phase signal QA is changed from '0' to '0' as shown in FIG. 15B. Since the A phase becomes less than V1 at time t2, the synchronized A phase signal QA changes from '1' to '0' as shown in FIG. 15 (b).
Although the above description has been made on the A phase, the sync B phase signal QB of the B phase is similarly as shown in FIG. 15C, and the sync B phase signal QB is advanced by 90 ° from the QA. Here, (d), (e), and (f) in FIG. 15 are cases where the sine wave incremental encoder 1b rotates in the reverse direction, which will be described later.

  Next, FIG. 16 shows that the comparator 3 has the characteristics shown in (a), (b) and (c) of FIG. 15, and that the sine wave incremental encoder 1b rotates in the forward rotation direction. FIG. 16A, FIG. 16B and FIG. 16C illustrate correction of the pulse phase detected by the pulse phase detector 8 according to the present invention when the output of the B phase crosses near zero. 15A, 15B and 15C, respectively, the outputs of the A and B phases of the sine wave incremental encoder 1b, the synchro A phase signal QA and the synchro B phase output from the pulse extractor 6, respectively. Signal QB is shown.

  First, in FIG. 16A, the microcontroller 9 in FIG. 13 represents the A-phase digital value and the B-phase digital value input from the A / D converters 13 and 14 as VA and VB, respectively. To do. The microcontroller 9 incorporates virtual comparators va and vb (not shown) by a program. When the A-phase digital value VA is positive, the virtual comparator va is '1', and when it is negative, the va is '0'. Similarly, when the B-phase digital value VB is positive, the virtual comparator vb is '1', and when it is negative, vb is '0'.

Next, with reference to FIGS. 16A and 16B, since the A-phase digital value VA is negative at time t1, the virtual comparator va becomes '0', and the synchronized A-phase signal QA is also '0'. Since va and QA match, the pulse phase is assumed to be correct and correction is not performed. Next, since the A-phase digital value VA is positive at time t2, the virtual comparator va is '1'. On the other hand, the synchronized A-phase signal QA is '0' and the va and QA do not match, so the pulse phase is Correction is necessary, and since the A-phase digital value VA is positive and is ahead of the synchro A-phase signal QA, correction is performed by adding 1 to the pulse phase. At time t3, the A-phase digital value VA is positive. Therefore, the virtual comparator va is “1”, and the synchro A phase signal QA is also “1”. Since the va and QA coincide with each other, the pulse phase is assumed to be correct and correction is not performed.
Similarly, since the A-phase digital value VA is positive at time t4, the virtual comparator va becomes “1”, and the synchronized A-phase signal QA is also “1”. Since the va and QA match, the pulse phase is correct. At time t5, since the A-phase digital value VA is negative, the virtual comparator va is “0”, and the synchronized A-phase signal QA is “1”, and the va and QA are inconsistent. The phase needs to be corrected. Since the A-phase digital value VA is negative and is ahead of the synchronized A-phase signal QA, correction is performed by adding 1 to the pulse phase. Further, since the A-phase digital value VA is negative at time t6, the virtual comparator va becomes '0', the synchronized A-phase signal QA is '0', and the va and QA coincide with each other, so that the pulse phase is correct. Do not make corrections. In summary, the correction of the pulse phase is as follows.
Time t1: Since VA <0, va = 0 and QA = 0 → they match, so no correction is required.Time t2: From 0 <VA, va = 1, QA = 0 → no match, so correction is necessary.
At this time, when VA crosses zero at the rising edge, va
Is corrected in the forward direction from QA, and correction of (+1) is performed. Time t3: 0 <VA from va = 1, QA = 1 → Since matching, no correction is required. Time t4: 0 <VA from va = 1, QA = 1 → Matches, so no correction required Time t5: VA <0, va = 0, QA = 1 → mismatch, so correction is required
At this time, when VA crosses zero at the falling edge, va
Advances in the forward direction from QA and corrects (+1). Time t6: Since VA <0, va = 0, QA = 0 → match, so no correction is required

The above describes the A phase when the sine wave incremental encoder 1b rotates in the forward rotation direction. Similarly, referring to FIGS. 16A and 16C for the B phase, the pulse phase The correction is as follows.
Time t7: Since 0 <VB, vb = 1, QB = 1 → match, so no correction is required. Time t8: From VB <0, vb = 0, QB = 1 → No match, so correction is necessary.
At this time, when VB crosses zero at the falling edge, vb
Will advance in the forward direction from QB, and the correction of (+1) will be made. Time t9: Since VB <0, VB = 0, QB = 0 → they match, so no correction is required. 0 → matches, so no correction required Time t11: 0 <VB, vb = 1, QB = 0 → mismatch so correction is required
At this time, when VB crosses zero at the rise, vb
Advances in the forward direction from QB, and the correction of (+1) is performed. Time t12: Since 0 <VB, vb = 1, QB = 1 → they match, so correction is unnecessary

FIG. 16 described above explains the correction of the pulse phase when the sine wave incremental encoder 1b rotates in the forward direction. Next, the case where the sine wave incremental encoder 1b rotates in the reverse direction will be described. First, (d), (e), and (f) of FIG. 15 show temporal transitions in the case of inversion of the same signal as (a), (b), and (c) of FIG. The sync B phase signal QB is delayed by 90 ° from the sync A phase signal QA. FIG. 17 illustrates the correction of the pulse phase when the sine wave incremental encoder 1b rotates in the reverse direction. FIGS. 17A, 17B, and 17C are the same as FIGS. The case of reversal of the same signal as in a), (b) and (c) is shown, and the correction of the pulse phase will be described sequentially from the A phase.
Time t21: Since VA <0, va = 0 and QA = 0 → match, so correction is not required. Time t22: From 0 <VA, va = 1, QA = 0 → mismatch, so correction is necessary.
At this time, when VA crosses zero at the rising edge, va
Is corrected in the reverse direction from QA and the correction of (-1) is performed. Time t23: 0 <VA from VA = 1, QA = 1 → Since matching, no correction is required. Time t24: 0 <VA from va = 1, QA = 1 → matches, so no correction required Time t25: VA <0, va = 0, QA = 1 → no match, so correction is required
At this time, when VA crosses zero at the falling edge, va
Advances from QA in the reverse direction and corrects (-1). Time t26: From VA <0, va = 0, QA = 0 → Since it matches, the pulse is rotated when rotating in the reverse direction so that correction is unnecessary. When the phase needs to be corrected, the forward correction (-1) is performed unlike the case of FIG.

Next, with reference to FIGS. 17A and 17C, correction of the B phase pulse phase when the sine wave incremental encoder 1b rotates in the reverse direction will be described.
Time t27: Since 0 <VB, vb = 1, QB = 1 → they match, so correction is not required Time t28: From VB <0, vb = 0, QB = 1 → no match, so correction
At this time, when VB crosses zero at the falling edge, vb
Is corrected in the reverse direction from QB, and the correction of (-1) is performed. Time t29: Since VB <0, Vb = 0, QB = 0 → Same, no correction is required. Time t30: From VB <0, vb = 0, QB = 0 → Match, so no correction required Time t31: 0 <VB, vb = 1, QB = 0 → mismatch, correction required
At this time, when VB crosses zero at the rise, vb
Advances in the reverse direction from QB, and the correction of (-1) is performed. Time t32: Since 0 <VB, vb = 1, QB = 1.fwdarw.

An example in which the correction of the pulse phase in FIGS. 16 and 17 described above is implemented by the program of the microcontroller 9 will be described with reference to FIG. Here, in this embodiment, as shown in FIG. 18, it is assumed that the block or the route of the processing is performed by the serial number attached with 'f', and the microcontroller 9 in FIG. And f3 are performed first.
f1: The A phase digital value VA and the B phase digital value VB are input. Also, after inputting the sync A phase signal QA and the sync B phase signal QB, go to f2.
f2: When VA is zero, the pulse phase is not corrected and the process is terminated via the route f21. If VA is not zero, go to f3.
f3: When VB is zero, the pulse phase is not corrected and the process is terminated through the route f21. If VB is not zero, go to f4.
As described above, when the A-phase digital value VA or the B-phase digital value VB is zero, the process is finished without performing the correction of the pulse phase according to FIGS.

Next, blocks f4 to f6 in FIG. 18 determine whether or not to correct the pulse phase for the A phase. When correcting the pulse phase for the A phase, the rotation direction is determined in the blocks f7 and f8. This determines whether the correction amount is (+1) or (-1).
First, the process from the block f4 to the route f5n from the block f5 through the block f5 to the block f7 will be described. When the A-phase digital value VA is less than zero in the block f4, the processing reaches the block f5 (in block f4, “no” VA is less than or equal to zero, but excludes the case where VA is zero in the block f2, so when reaching the block f5, it becomes 'less than zero'). At this time, the virtual comparator va is set to '0' Become.
Next, in the block f5, when the synchro A phase signal QA is '1', the route f5n is reached.
That is, when the route f5n is reached, the virtual comparator va is '0', and the synchro A phase signal QA is inconsistent with '1' and the pulse phase needs to be corrected. At this time, the virtual comparator va Since it is '0', this is a case where the A phase falls, and correction at time t5 in FIG. 16 is necessary for normal rotation, and correction at time t25 in FIG. 17 is necessary for reverse rotation.
Next, in block f7, referring to time t5 in FIG. 16, when the B-phase digital value VB is negative at the fall of the A-phase, it is determined that the rotation direction is normal rotation, and (+1) of the pulse phase Branching to the block f14 to be corrected, and referring to the time t25 in FIG. 17, when the B phase digital value VB is positive at the fall of the A phase, the rotation direction is determined to be reverse, and the pulse phase (− Branch to block f15 where the correction of 1) is performed.

The above-described process from the block f4 through the block f5 to the route f5n and the processing of the block f7 are summarized as follows, and are shown in comparison with the processing of FIG. 16 and FIG.
f5n: VA = 0 from VA <0 at f4, QA = 1 at f5,
va and QA are inconsistent and need to be corrected, go to block f7
This route f5n is when the phase A is falling. F7: When 0 <VB is not satisfied, forward rotation to f14 ........ time t5 in FIG.
When 0 <VB is satisfied, reverse rotation to f15... Time t25 in FIG.
Similarly, the process from the block f4 through the block f6 to the route f6n and the process of the block f8 are summarized as follows, and are shown in comparison with the processes of FIGS.
f6n: 0 <VA at f4, va = 1 from fA, QA = 0 at f6,
va and QA are inconsistent and need to be corrected, go to block f8
This route f6n is when the A-phase is rising. F8: When 0 <VB is satisfied, forward rotation is performed to f14 .... time t2 in FIG.
When 0 <VB is not satisfied, the rotation is reversed to f15... Time t22 in FIG.

Next, the process from the block f4 through the block f5 to the route f5y and the process from the block f4 through the block f6 to the route f6y are as follows. At this time, the correction of the pulse phase is not required and the B phase is corrected. Move on to processing.
f5y: VA <0 at VA <0 at f4, QA = 0 at f5
Since va and QA match, no correction is required and the process goes to block f9.
It is the time t1, t6 in FIG. 16 or the time t21, t26 in FIG. 17. f6y: 0 <VA at f4, VA = 1 from fA, QA = 1 at f6
Since va and QA match, no correction is required and the process goes to block f9.
It is the time t3, t4 in FIG. 16 or the time t23 and t24 in FIG.

As described above, in FIG. 18, the correction of the pulse phase performed in the blocks f4 to f8 for the A phase has been described. Next, the correction of the pulse phase performed in the blocks f9 to f13 for the B phase will be described.
The block f9 to the block f11 in FIG. 18 determine whether or not the pulse phase needs to be corrected for the B phase, and whether the correction amount is (+1) or not (-1) depending on the rotation direction in the blocks f12 and f13. To decide what to do.
First, the process from the block f9 to the route f10n through the block f10 to the block f12 reaches the block f10 when the B-phase digital value VB is less than zero in the block f9 (when 'no' in the block f9) VB is less than or equal to zero, but excludes the case where VB is zero in the block f3, so that when reaching the block f10, it becomes “less than zero”). At this time, the virtual comparator vb becomes “0”.
Next, in the block f10, when the synchro B phase signal QB is "1", the route f10n is reached.
That is, when the route f10n is reached, the virtual comparator vb is “0” and the synchro B phase signal QB is inconsistent with “1”, and the pulse phase needs to be corrected. At this time, the virtual comparator vb Since it is '0', this is a case where the B phase falls, and correction at time t8 in FIG. 16 is necessary for normal rotation, and correction at time t28 in FIG. 17 is necessary for reverse rotation.
Next, in block f12, referring to time t8 in FIG. 16, when the A-phase digital value VA is positive at the fall of the B-phase, the rotation direction is determined to be normal rotation and the pulse phase is corrected by (+1). Referring to time t28 in FIG. 17, when the A phase digital value VA is negative at the fall of the B phase, the rotation direction is determined to be reverse and the pulse phase (−1) is determined. Branches to block f15 where the correction is performed.

The above process from the block f9 through the block f10 to the route f10n and the process of the block f12 are summarized as follows, and are shown in comparison with the processes of FIGS.
f10n: V9 at f9 from VB <0, vb = 0 at f10, QB = 1 at f10
vb and QB are inconsistent and need to be corrected, go to block f12
This route f10n is when the B phase falls. F12: When 0 <VA is satisfied, the rotation is forward to f14, and time t8 in FIG.
When 0 <VA is not satisfied, the rotation is reversed to f15... Time t28 in FIG.
Similarly, the process from the block f9 to the route f11n through the block f11 and the process of the block f13 are summarized as follows, which is shown in comparison with the processes of FIGS.
f11n: 0 <VB at f9, vb = 1 from fB, QB = 0 at f11,
vb and QB are inconsistent and need to be corrected, go to block f13
This route f11n is when the B phase rises. F13: When 0 <VA is not satisfied, forward rotation is performed to f14.
When 0 <VA is satisfied, the rotation is reversed to f15... Time t31 in FIG.

The process from the block f9 through the block f10 to the route f10y and the process from the block f9 through the block f11 to the route f11y are as follows. At this time, no correction of the pulse phase is required and the route f21y is passed through. The process of FIG. 18 is finished.
f10y: vb = 0 from f9 at v9, QB = 0 at f10
Since vb and QB match, no correction is required and the end
At time t9, t10 in FIG. 16 or at time t29, t30 in FIG. 17 f11y: 0 <VB at f9, QB = 1 at vb = 1, f11
Since vb and QB match, no correction is required and the end
It is the time t7, t12 in FIG. 16 or the time t27 and t32 in FIG.

Thus, the microcontroller 9 periodically performs the processing of FIG. 18, and when the comparator 3 performs the operation shown in FIG. 15, the sine wave incremental encoder 1b rotates in the forward direction. Even when rotating in the reverse direction, as shown in FIGS. 16, 17, and 18, the pulse phase is corrected when the A phase and B phase of the sine wave incremental encoder 1b cross zero.
In this correction, the pulse phase is corrected on the basis of the A-phase digital value VA and the B-phase digital value VB, and the higher-order pulse phase shown in FIG. The interpolation phase of the lower digits in FIG. 32A is obtained from the equation (1) using the A-phase digital value VA and the B-phase digital value VB that are used as a reference when correcting the pulse phase. Is.
In this way, it is compensated that the combination of the pulse phase and the interpolation phase is always correct, and it is possible to always detect the correct rotational phase even when the sine wave incremental encoder 1b rotates at a high speed as well as a low speed. .
Here, such a pulse correction is required because the pulse phase detection mechanism including the pulse extractor 6 and the pulse phase detector 8 in FIG. 13 and the interpolation phase including the A / D converters 13 and 14 are used. This is because the detection mechanisms are different from each other, and it is not compensated that the combination of the pulse phase and the interpolation phase is always correct due to variations in operation levels, delays in operation time, and the like.

Next, an embodiment related to claim 3 will be described with reference to FIGS. 19, 20, 21 and 22. FIG. First, FIG. 19 shows the operation of the comparator 3 different from that in FIG. 15. FIG. 19A shows the temporal output of the A phase and the B phase when the sine wave incremental encoder 1b is rotating forward. Corresponding to this, (b) and (c) of FIG. 19 show synchronized A phase signals QA and synchronized B phases in which the outputs of the comparators 3 of A phase and B phase are held by the pulse extractor 6. The time transition of the signal QB is shown.
The comparator 3 is “1” when the input is Vh or more and becomes “0” when the input is less than Vl. FIG. 19 shows the operation when Vh is less than Vl. Since the A phase of the sine wave incremental encoder 1b exceeds Vh at time t1 in FIG. 19A, the synchro A phase signal QA changes from “0” to “1” as shown in FIG. 19B. Thus, at time t2, the A phase becomes less than Vl. Therefore, as shown in FIG. 19B, the synchro A phase signal QA changes from '1' to '0'.
Although the above description has been made on the A phase, the sync B phase signal QB of the B phase is similarly as shown in FIG. 19C, and the sync B phase signal QB is advanced by 90 ° from the QA. 19D, 19E, and 19F show the case where the sine wave incremental encoder 1b rotates in the reverse direction, which will be described later.

  Here, when Vh in FIG. 15 is larger than Vl, it is when the comparator 3 has a normal hysteresis characteristic. Separately, it is considered that Vh in FIG. 19 is less than Vl. This is because the rotational phase of the sine wave incremental encoder 1b can be reliably detected even when there are variations in characteristics of the electronic components constituting the apparatus such as the comparator 3.

  Next, FIG. 20 shows that the comparator 3 has the characteristics shown in (a), (b) and (c) of FIG. 19, and the sine wave incremental encoder 1b rotates in the normal rotation direction. FIG. 20A, FIG. 20B, and FIG. 20C illustrate the correction of the pulse phase detected by the pulse phase detector 8 according to the present embodiment when the output of the B phase crosses near zero. 19A, 19B and 19C, respectively, the outputs of the A and B phases of the sine wave incremental encoder 1b, the synchro A phase signal QA and the synchro B output from the pulse extractor 6, respectively. The phase signal QB is shown.

  First, in FIG. 20A, the A-phase digital value and the B-phase digital value input from the A / D converters 13 and 14 by the microcontroller 9 in FIG. 13 are expressed as VA and VB, respectively. To do. The microcontroller 9 incorporates virtual comparators va and vb (not shown) by a program. When the A-phase digital value VA is positive, the virtual comparator va is '1', and when it is negative, the va is '0'. Similarly, when the B-phase digital value VB is positive, the virtual comparator vb is '1', and when it is negative, vb is '0'.

Next, with reference to FIGS. 20A and 20B, since the A-phase digital value VA is negative at time t41, the virtual comparator va becomes '0' and the synchronized A-phase signal QA is also '0'. Since va and QA match, the pulse phase is assumed to be correct and correction is not performed.
Next, since the A-phase digital value VA is negative at time t42, the virtual comparator va becomes “0”, while the synchronized A-phase signal QA is “1”, and the va and QA do not match, so the pulse phase is corrected. Since the A-phase digital value VA is negative and delayed from the synchro A-phase signal QA, correction is performed by subtracting 1 from the pulse phase. At time t43, the A-phase digital value VA is positive. The virtual comparator va becomes “1”, the synchro A phase signal QA is also “1”, and since va and QA coincide with each other, the pulse phase is assumed to be correct and correction is not performed.
Similarly, since the A-phase digital value VA is positive at time t44, the virtual comparator va becomes '1', and the synchronized A-phase signal QA is also '1'. Since va and QA match, the pulse phase is correct. At time t45, since the A-phase digital value VA is positive, the virtual comparator va is “1”, and the synchronized A-phase signal QA is “0”. Since the va and QA do not match, the pulse The phase needs to be corrected. Since the A-phase digital value VA is positive and lags behind the synchro A-phase signal, correction is performed by subtracting 1 from the pulse phase.
Since the A-phase digital value VA is negative at time t46, the virtual comparator va becomes '0', and the synchronized A-phase signal QA is '0'. Since va and QA coincide with each other, the pulse phase is assumed to be correct. Not performed. In summary, the correction of the pulse phase is as follows.
Time t41: Since VA <0, va = 0 and QA = 0 → match, so no correction is required. Time t42: From VA <0, va = 0, QA = 1 → No match, so correction is necessary.
At this time, when VA crosses zero at the rising edge, va
Is delayed in the forward rotation direction from QA, and correction of (-1) is performed. Time t43: 0 <VA since va = 1, QA = 1 → Since matching, no correction is required. Time t44: 0 <VA from va = 1, QA = 1 → Match, so no correction required Time t45: 0 <VA from VA = 1, QA = 0 → mismatch, correction required
At this time, when VA crosses zero at the falling edge, va
Is delayed in the forward direction from QA, and the correction of (-1) is performed. Time t46: Since VA <0, va = 0, QA = 0 → they match, so correction is unnecessary

The above describes the A phase when the sine wave incremental encoder 1b rotates in the forward rotation direction. Similarly, with reference to FIGS. The correction is as follows.
Time t47: Since 0 <VB, vb = 1, QB = 1 → match, so no correction is required. Time t48: From 0 <VB, vb = 1, QB = 0 → No match, so correction is necessary.
At this time, when VB crosses zero at the falling edge, vb
Is delayed in the forward direction from QB, and the correction of (-1) is performed. Time t49: Since VB <0, Vb = 0, QB = 0 → Same, no correction is required. Time t50: From VB <0, vb = 0, QB = 0-> match, so no correction required Time t51: VB <0, vb = 0, QB = 1-> mismatch, correction required
At this time, when VB crosses zero at the rise, vb
Is delayed in the forward direction from QB, and the correction of (-1) is performed. Time t52: Since 0 <VB, vb = 1, QB = 1 → they match, so correction is unnecessary

FIG. 20 described above explains the correction of the pulse phase when the sine wave incremental encoder 1b rotates in the forward direction. Next, the case where the sine wave incremental encoder 1b rotates in the reverse direction will be described.
First, (d), (e), and (f) in FIG. 19 show temporal transitions in the case of inversion of the same signal as in (a), (b), and (c) of FIG. The sync B phase signal QB is delayed by 90 ° from the sync A phase signal QA. FIG. 21 illustrates the correction of the pulse phase when the sine wave incremental encoder 1b rotates in the reverse direction. FIGS. 21 (a), 21 (b) and 21 (c) are the same as FIGS. The case of the same signal reversal as in a), (b) and (c) is shown, and the correction of the pulse phase will be described sequentially from the A phase.
Time t61: Since VA <0, va = 0, QA = 0 → match, so no correction is required. Time t62: From VA <0, va = 0, QA = 1 → No match, so correction is necessary.
In this case, when VA crosses zero at the rising edge, va is delayed in the reverse direction from QA, and the correction of (+1) is performed. Unnecessary Time t64: 0 <VA since va = 1, QA = 1 → match, so correction is not required. Time t65: From 0 <VA, va = 1, QA = 0 → mismatch, so correction is necessary.
In this case, when VA crosses zero at the falling edge, va is delayed in the reverse direction from QA, and correction is performed (+1). If the pulse phase needs to be corrected when rotating in the reverse rotation direction, unlike in the case of FIG. 20, the delay (+1) is corrected.

Next, with reference to FIGS. 21A and 21C, the correction of the pulse phase of the B phase when the sine wave incremental encoder 1b rotates in the reverse direction will be described.
Time t67: Since 0 <VB, vb = 1, QB = 1 → match, so no correction is required.
At this time, when VB crosses zero at the falling edge, vb
Is delayed from QB in the reverse direction and correction of (+1) is performed. Time t69: Since VB <0, Vb = 0, QB = 0 → they match, so no correction is required. Time t70: VB <0, vb = 0, QB = 0 → Correction is not necessary because it matches. Time t71: Since VB <0, vb = 0, QB = 1 → Inconsistency, correction is required
At this time, when VB crosses zero at the rising edge, vb
Is delayed in the reverse direction from QB, and correction of (+1) is performed. Time t72: Since 0 <VB, vb = 1, QB = 1 → they match, so correction is unnecessary

An example in which the correction of the pulse phase in FIGS. 20 and 21 described above is implemented by the program of the microcontroller 9 will be described with reference to FIG. Here, as in FIG. 18, in FIG. 22, it is assumed that the block or the route of processing is performed by the serial number attached with “f”, and the microcontroller 9 in FIG. 22 has blocks f 1, f 2 and f 3. The following processing is performed first.
f1: The A phase digital value VA and the B phase digital value VB are input. Also, after inputting the sync A phase signal QA and the sync B phase signal QB, go to f2.
f2: When VA is zero, the pulse phase is not corrected and the process is terminated via the route f21. If VA is not zero, go to f3.
f3: When VB is zero, the pulse phase is not corrected and the process is terminated through the route f21. If VB is not zero, go to f4.
Thus, when the A-phase digital value VA or the B-phase digital value VB is zero, the processing is finished without performing the correction of the pulse phase according to FIGS.

Next, blocks f4 to f6 in FIG. 22 determine whether or not to correct the pulse phase for the A phase. When correcting the pulse phase for the A phase, the blocks f7 and f8 depend on the rotation direction. It is determined whether the correction amount is (+1) or (-1).
First, the processing from the block f4 to the route f5n from the block f4 through the block f5 to the block f7 will be described. When the A-phase digital value VA is less than zero in the block f4, the processing reaches the block f5 (in block f4, “no” At this time, VA is less than or equal to zero, but excludes the case where VA is zero in the block f2, so that when reaching the block f5, it becomes “less than zero”). At this time, the virtual comparator va becomes “0”. Become.
Next, in the block f5, when the synchro A phase signal QA is "1", the route f5n is reached.
That is, when the route f5n is reached, the virtual comparator va is “0” and the synchro A phase signal QA is not equal to “1”, and the pulse phase needs to be corrected. At this time, the virtual comparator va Since it is '0', this is a case where the A phase is rising, and correction at time t42 in FIG. 20 is necessary for normal rotation, and correction at time t62 in FIG. 21 is necessary for reverse rotation.
Next, in block f7, referring to time t42 in FIG. 20, when the B phase digital value VB is positive at the rise of the A phase, the rotation direction is determined to be normal rotation, and the pulse phase is set to (-1). Branching to the block f15 for performing correction, and referring to the time t62 in FIG. 21, when the B phase digital value VB is negative at the rise of the A phase, the rotation direction is determined to be reverse, and the pulse phase is set to (+1). Branches to block f14 to perform the correction.

The above-described process from the block f4 to the route f5n via the block f5 and the process of the block f7 are summarized as follows, and are shown in comparison with the processes of FIGS.
f5n: VA = 0 from VA <0 at f4, QA = 1 at f5,
va and QA are inconsistent and need to be corrected, go to block f7
This route f5n is when the A phase rises. F7: When 0 <VB is satisfied, forward rotation and go to f15... Time t42 in FIG.
When 0 <VB is not satisfied, the rotation is reversed to f14... Time t62 in FIG.
Similarly, the process from the block f4 to the route f6n via the block f6 and the process of the block f8 are summarized as follows, and are shown in comparison with the processes of FIGS.
f6n: 0 <VA at f4, va = 1 from f, QA = 0 at f6
va and QA are inconsistent and need to be corrected, go to block f8
This route f6n is when the A phase falls.
f8: When 0 <VB is not satisfied, forward rotation and go to f15... time t45 in FIG.
When 0 <VB is satisfied, reverse rotation to f14... Time t65 in FIG.

Next, the process from the block f4 through the block f5 to the route f5y and the process from the block f4 through the block f6 to the route f6y are as follows. At this time, the correction of the pulse phase is not required. Move on to processing.
f5y: VA <0 at VA <0 at f4, QA = 0 at f5
Since va and QA match, no correction is required and the process goes to block f9.
This is the time t41 and t46 in FIG. 20 or the time t61 and t66 in FIG.
f6y: 0 <VA at f4, va = 1 from fA, QA = 1 at f6
Since va and QA match, no correction is required and the process goes to block f9.
This is the time t43, t44 in FIG. 20 or the time t63 and t64 in FIG.

The correction of the pulse phase performed in blocks f4 to f8 for the A phase in FIG. 22 has been described above. Next, the correction of the pulse phase performed in blocks f9 to f13 for the B phase will be described.
The blocks f9 to f11 in FIG. 22 determine whether or not to correct the pulse phase for the B phase. In blocks f12 and f13, whether the correction amount is (+1) or (-1) depending on the rotation direction. To decide what to do.
First, the process from the block f9 to the route f10n through the block f10 to the block f12 reaches the block f10 when the B-phase digital value VB is less than zero in the block f9 (when 'no' in the block f9) VB is less than or equal to zero, but excludes the case where VB is zero in the block f3, so that when reaching the block f10, it becomes “less than zero”). At this time, the virtual comparator vb becomes “0”.
Next, in the block f10, when the synchro B phase signal QB is "1", the route f10n is reached.
That is, when the route f10n is reached, the virtual comparator vb does not match “0” and the synchro B phase signal QB does not match “1”, and the pulse phase needs to be corrected. At this time, the virtual comparator vb Is “0”, the phase B is rising, and correction at time t51 in FIG. 20 is required for forward rotation, and correction at time t71 in FIG. 21 is required for reverse rotation.
Next, in block f12, referring to time t51 in FIG. 20, when the A-phase digital value VA is negative at the rise of the B-phase, the rotation direction is determined to be normal rotation and the pulse phase is corrected by (−1). Referring to time t71 in FIG. 21, when the A phase digital value VA is positive at the rise of the B phase, the rotation direction is determined to be reverse, and the pulse phase is corrected by (+1). Branch to block f14 where

The above-described process from the block f9 through the block f10 to the route f10n and the processing of the block f12 are summarized as follows, and are shown in comparison with the processing of FIG. 20 and FIG.
f10n: From VB <0 at f9, vb = 0, and at f10, QB = 1.
vb and QB are inconsistent and need to be corrected, go to block f12
This route f10n is when the B phase rises.
f12: When 0 <VA is not satisfied, forward rotation and go to f15... time t51 in FIG.
When 0 <VA is satisfied, reverse rotation to f14... Time t71 in FIG.
Similarly, the process from the block f9 to the route f11n through the block f11 and the process of the block f13 are summarized as follows, which is shown in comparison with the processes of FIGS.
f11n: 0 <VB at f9, vb = 1 from fB, QB = 0 at f11
vb and QB are inconsistent and need to be corrected, go to block f13
This route f11n is when the B phase falls.
f13: When 0 <VA is satisfied, forward rotation and go to f15... time t48 in FIG.
When 0 <VA is not satisfied, the rotation is reversed to f14... Time t68 in FIG.

The process from the block f9 through the block f10 to the route f10y and the process from the block f9 through the block f11 to the route f11y are as follows. The process of FIG. 22 is finished.
f10y: vb = 0 from f9 at v9, QB = 0 at f10
Since vb and QB match, no correction is required and the end
This is the time t49, t50 in FIG. 20 or the time t69, t70 in FIG.
f11y: 0 <VB at f9, vb = 1, and QB = 1 at f11
Since vb and QB match, no correction is required and the end
This is the time t47, t52 in FIG. 20, or the time t67 and t72 in FIG.

  In this way, the microcontroller 9 periodically performs the processing of FIG. 22, and when the comparator 3 performs the operation shown in FIG. 19, the sine wave incremental encoder 1b also rotates in the forward rotation direction. Even when rotating in the reverse direction, as shown in FIGS. 20, 21, and 22, the pulse phase is corrected even when the A phase and the B phase of the sine wave incremental encoder 1b cross zero, and the sine wave is corrected. Even when the incremental encoder 1b rotates at a high speed as well as a low speed, the correct pulse phase is always detected.

Here, in FIG. 13, an embodiment of correcting the pulse phase output from the pulse phase detector 8 is shown and described in FIGS. 18 and 22, and in this embodiment, the sine wave incremental is used. The case where the A-phase digital value VA or the B-phase digital value VB of the encoder 1b is zero is excluded.
Next, when the VA or VB is zero in FIG. 13, an example of the correction of the pulse phase according to the present invention will be described.

First, FIG. 23, FIG. 24 and FIG. 25 show the A-phase signal of the sine wave incremental encoder 1b when the comparator 3 in FIG. 13 has the characteristics shown in (a) to (f) of FIG. Alternatively, when the B-phase signal is zero, an example of correction of the pulse phase according to claim 4 will be described. 23, (a) of FIG. 23 shows temporal transitions of the A-phase signal and the B-phase signal when the sine wave incremental encoder 1b rotates in the forward rotation direction, and (b) of FIG. ) And (c) show the synchronized A-phase signal QA and synchronized B-phase signal QB output from the pulse extractor 6, respectively. In FIG. 23 (a), the level at which the comparator 3 operates is Vh and Vl as in FIG. 15 (a), and Vh is larger than Vl. The microcontroller 9 in FIG. Are the A-phase digital value and the B-phase digital value input from the A / D converters 13 and 14, respectively, as VA and VB. Then, it is assumed that the A-phase digital value VA becomes zero at times t13 and t14, the B-phase digital value VB becomes zero at times t15 and t16, and then the A phase is taken as an example in FIG. As shown in b), the synchro A-phase signal QA changes with a delay of '1' at time (t13 + Δt13) and '0' at time (t14 + Δt14).

Next, (d) of FIG. 23 shows the pulse phase output from the pulse phase detector 8, and the pulse phase is counted up in synchronization with the synchro A phase signal QA and the synchro B phase signal QB. Or, if the A phase is taken as an example, when the synchro A phase signal QA becomes '1' at time (t13 + Δt13), the pulse phase changes from (C-1) to (C) at time (t14 + Δt14). ), The pulse phase is counted up from (C + 1) to (C + 2) when the synchro A phase signal QA becomes '0'.
FIG. 23E shows the interpolation phase virtually calculated by the microcontroller 9 from the A-phase digital value VA and the B-phase digital value VB. For example, the interpolation phase from time t13 to t15 is shown. Increases from zero and the maximum interpolation phase is counted up to αmax.

  Here, for example, when the microcontroller 9 detects that the interpolation phase is zero at time t13 because the A-phase digital value VA is zero, the pulse phase is as shown in (d) of FIG. 1). However, if the pulse phase at point A is (C-1) in FIG. 23E, the interpolation phase increases from point A and reaches zero after reaching the maximum interpolation phase αmax, that is, time t13. Is corrected by adding 1 to (C), and the temporal transition of the corrected virtual pulse phase is shown in FIG. Thus, the reason why the pulse phase shown in (d) of FIG. 23 does not become the ideal (f) of FIG. 23 is that the level Vh for detecting “1” and “0” in realizing the comparator 3. This is because it is impractical or impossible to set both the level Vl for detecting 'to zero, and it cannot be prohibited that Vh and Vl become as shown in FIG.

Then, when the sinusoidal incremental encoder 1b rotates in the forward rotation direction, the correction process according to the present invention described above for the A phase can be summarized as follows. When the phase A digital value VA detects zero at the phase rising time t13 and the synchro phase A signal QA detects '0' as shown in FIG. 23B, the Vh is greater than zero. Therefore, it is determined that the sync A phase signal QA is supposed to be “1” and the pulse phase is not counted up, and the pulse phase (C−1) at time t13 in FIG. ) To add 1 to (C). Similarly, the microcontroller 9 detects that the A-phase digital value VA is zero at the falling time t14 of the A-phase shown in (a) of FIG. 23, and the synchro A as shown in (b) of FIG. When the phase signal QA detects “1”, it is determined that the place where the synchronized A-phase signal QA should be “0” is delayed due to the fact that Vl is smaller than zero. ) Is corrected by adding 1 to the pulse phase (C + 1) at time t14 (C + 2).
The phase A has been described above. Similarly, for the phase B, the microcontroller 9 detects that the phase B digital value VB is zero at the times t15 and t16 in FIG. The same processing is performed.

  FIG. 23 described above is when the sine wave incremental encoder 1b rotates in the forward direction, but when the sine wave incremental encoder 1b rotates in the reverse direction next time, the microcontroller 9 causes the A-phase signal of the sine wave incremental encoder 1b. Alternatively, when the B phase signal is detected as zero, the correction of the pulse phase will be described with reference to FIG. 24. FIGS. 24A to 24E show the time transition of the same signal as that of FIG. In FIG. 24 (d), the pulse phase counts down with time, and the interpolation phase in FIG. 24 (e) also decreases. In FIG. 24A, it is assumed that the A-phase digital value VA is zero at times t33 and t34, and the B-phase digital value VB is zero at times t35 and t36. As shown in FIG. 24 (b), the synchro A-phase signal QA changes with a delay to '1' at time (t33 + Δt33) and to '0' at time (t34 + Δt34).

  The pulse phase output from the pulse phase detector 8 in FIG. 24D is counted up or down completely in synchronization with the sync A phase signal QA and the B phase digital value VB. Taking the phase as an example, the pulse phase changes from (C) to (C-1) at the time (t33 + Δt33), and the sync A phase at the time (t34 + Δt34). When the signal QA becomes '0', the pulse phase counts down from (C-2) to (C-3). FIG. 24E shows the interpolation phase virtually calculated by the microcontroller 9 from the A-phase digital value VA and the B-phase digital value VB. For example, the interpolation is performed from time t33 to t36. The phase is such that the maximum interpolation phase counts down from αmax to zero.

  Here, for example, when the microcontroller 9 detects that the A-phase digital value VA is zero at the point B at time t33 in FIG. 24A, the microcontroller 9 sets the interpolation phase to the point B in FIG. As shown, zero is calculated. At this time, the pulse phase is (C) as shown in FIG. Here, if the pulse phase at point A is (C) in (e) of FIG. 24, the pulse phase at point B where the interpolation phase decreases from point A and becomes zero is also correct in (C). Thus, when the sine wave incremental encoder 1b rotates in the reverse direction, even if the microcontroller 9 detects the A-phase digital value VA or the B-phase digital value VB as zero, it differs from the normal rotation. There is no need to correct the pulse phase.

When the comparator of FIG. 13 described above has the operating characteristics of FIG. 15, the correction of the pulse phase described in FIG. 23 at the time of forward rotation and FIG. 24 at the time of reverse rotation is performed by the microcontroller 9. An example of implementation by the program will be described with reference to FIG. First, the microcontroller 9 performs the following processing of blocks f1, f2 and f3 in FIG.
f1: After inputting the A phase digital value VA, the B phase digital value VB, the synchro A phase signal QA, the synchro B phase signal QB and the pulse phase, go to f2.
f2: When VA is zero, go to f4, and when VA is not zero, go to f3.
f3: When VB is zero, the process proceeds to f4. When VB is not zero, the pulse phase is not corrected and the process is finished through the route f3n.
Thus, when the A-phase digital value VA or the B-phase digital value VB is zero, the pulse phase correction according to FIGS. 23 and 24 is performed, and the process proceeds to block f4.
Next, in the block f4, the rotation direction of the sine wave incremental encoder 1b is detected, and as described in FIG. 24 at the time of reverse rotation, since the correction of the pulse phase is not necessary, the process is finished through the route f4n. When the rotation is normal, the process proceeds to block f5 to correct the pulse phase described with reference to FIG. The rotation direction may be detected by, for example, normal rotation if the pulse phase has increased from the previous scan, and reverse rotation if it has decreased.

The block f5 determines whether the A-phase digital value VA is zero or the B-phase digital value VB is zero, and the blocks f6 to f8 are the pulse phases when the A-phase VA is zero. The following processing is performed with reference to FIG.
f5: When VA is zero, the process proceeds to f6, and the pulse phase is corrected by the A phase. When VA is not zero, VB is zero and the process proceeds to f9 to correct the pulse phase by the B phase. f6: When VA is zero and VB is positive, the process proceeds to f8 when VA rises. When VA is zero and VB is negative, the process proceeds to f7 when VA falls.
f7: At this time, when VA falls to zero, at this time, if QA is '1', QA becomes '0', but since it is delayed, the process proceeds to f12 and is corrected to add 1 to the pulse phase I do. When QA is “0”, no correction is necessary, and the process is finished through f11n.
f8: At this time, when VA becomes zero when rising, if QA is '0', since QA is delayed from becoming '1', the process proceeds to f12, and correction for adding 1 to the pulse phase is performed. Do. When QA is “1”, no correction is necessary, and the process is finished through f11n.
Next, blocks f9 to f11 relate to correction of the pulse phase when the VB of the B phase is zero, and the following processing is performed with reference to FIG.
f9: When VB is zero and VA is negative, the process proceeds to f11 when VB rises. When VB is zero and VA is positive, VB falls and the process proceeds to f10.
f10: At this time, VB becomes zero when falling, and if QB is '1' at this time, since QB is delayed from becoming '0', the process proceeds to f12, and correction is performed to add 1 to the pulse phase. I do. When QB is “0”, no correction is necessary, and the process is finished through f11n.
f11: At this time, VB becomes zero when rising, and if QB is '0', since QB is delayed from becoming '1', the process proceeds to f12, and correction for adding 1 to the pulse phase is performed. Do. When QB is “1”, no correction is necessary, and the process is finished through f11n.

  Thus, when the comparator 3 of FIG. 13 performs the operation shown in FIG. 15, the sine wave incremental encoder 1b rotates in the forward direction and in the reverse direction, as shown in FIGS. As shown in FIG. 25, when the microcontroller 9 detects that the A-phase digital value VA or the B-phase digital value VB of the sine wave incremental encoder 1b is zero, the pulse phase is corrected. Thus, the correct pulse phase is always detected even when the sine wave incremental encoder 1b rotates at a high speed as well as a low speed.

Next, when the comparator 3 in FIG. 13 has the characteristics shown in FIGS. 19A to 19F, the A-phase signal or B-phase signal of the sine wave incremental encoder 1b is zero. An embodiment of correction of the pulse phase according to claim 5 will be described with reference to FIGS. 26, 27, and 28. FIG.
First, similar to FIG. 23 with respect to FIG. 26, (a) of FIG. 26 shows temporal transitions of the A-phase signal and the B-phase signal when the sine wave incremental encoder 1b rotates in the forward rotation direction. FIGS. 26B and 26C show the synchro A phase signal QA and the synchro B phase signal QB output from the pulse extractor 6, respectively.
In FIG. 26 (a), the level at which the comparator 3 operates is Vh and Vl as in FIG. 19 (a), and Vh is smaller than Vl. The microcontroller 9 in FIG. Are the A-phase digital value and B-phase digital value input from the A / D converters 13 and 14, respectively, as VA and VB. The phase A digital value VA is assumed to be zero at times t53 and t54, the phase B digital value VB is assumed to be zero at times t55 and t56, and the phase A is taken as an example in FIG. ), The synchro A-phase signal QA changes early to '1' at time (t53-Δt53) and to '0' at time (t54-Δt54).

Next, (d) of FIG. 26 shows the pulse phase output by the pulse phase detector 8, and the pulse phase is counted up in synchronization with the synchro A phase signal QA and the synchro B phase signal QB. If the A phase is taken as an example, the pulse phase changes from (C-1) to (C) when the sync A phase signal QA becomes '1' at time (t53-Δt53). When the synchro A-phase signal QA becomes “0” at (t54−Δt54), the pulse phase is counted up from (C + 1) to (C + 2).
FIG. 26E shows the interpolation phase virtually calculated by the microcontroller 9 from the A-phase digital value VA and the B-phase digital value VB. For example, the interpolation phase from time t53 to t55 is shown. Is counted up from zero to the maximum interpolation phase αmax.

In FIG. 26, the correction of the pulse phase when the A-phase digital value VA or the B-phase digital value VB is zero will be described as follows. For example, the microcontroller 9 performs the time shown in FIG. When the A-phase digital value VA is detected as zero at the point B at t53, the interpolation phase is calculated as zero shown at the point B in (e) of FIG. 26. At this time, it is shown by (d) in FIG. As described above, the pulse phase is (C).
Here, if the pulse phase at point A in FIG. 26 (e) is (C-1), point B becomes zero after the interpolation phase increases from point A and reaches the maximum interpolation phase αmax, that is, time The pulse phase at t53 should be (C) by adding 1, and is equal to the pulse phase obtained from (d) of FIG. This is because the pulse phase of FIG. 26 is counted up at a time earlier than time t53 by time Δt53.
Thus, when the sine wave incremental encoder 1b rotates in the forward direction, even if the microcontroller 9 detects the A-phase digital value VA or the B-phase digital value VB as zero, it is necessary to correct the pulse phase. There is nothing.

FIG. 26 described above is a case where the sine wave incremental encoder 1b rotates in the forward rotation direction when the comparator 3 has the characteristics shown in FIGS. 19 (a) to 19 (f). When the microcontroller 9 detects that the A-phase signal or B-phase signal of the sine wave incremental encoder 1b is zero when rotating in the reverse direction, the correction of the pulse phase will be described with reference to FIG. 27 (a) to (e) show the time transition of the same signal as that of FIG. 26. In FIG. 27 (d), the pulse phase counts down with time, and in FIG. 27 (e). The interpolation phase also changes in the decreasing direction.
In FIG. 27A, it is assumed that the A-phase digital value VA becomes zero at times t73 and t74, and the B-phase digital value VB becomes zero at times t75 and t76. As shown in FIG. 27 (b), the synchro A phase signal QA changes early to '1' at time (t73-Δt73) and to '0' at time (t74-Δt74).

The pulse phase output from the pulse phase detector 8 in FIG. 27 (d) counts up or down completely in synchronization with the synchro A phase signal QA and the B phase digital value VB. Taking the phase as an example, the pulse phase changes from (C) to (C-1) and from time (t74-Δt74) when the synchro A-phase signal QA becomes '1' at time (t73-Δt73). When the synchro A phase signal QA becomes '0', the pulse phase counts down from (C-2) to (C-3).
FIG. 27E shows the interpolation phase virtually calculated by the microcontroller 9 from the A-phase digital value VA and the B-phase digital value VB. For example, the interpolation is performed from time t75 to t73. The phase is such that the maximum interpolation phase counts down from αmax to zero.

In FIG. 27, the correction of the pulse phase when the A-phase digital value VA or the B-phase digital value VB is zero will be described as follows. For example, the microcontroller 9 performs the time shown in FIG. When the A-phase digital value VA is detected as zero at the point B at t73, the interpolation phase is calculated as zero as indicated by the point B in FIG. 27 (e). At this time, in FIG. As shown, the pulse phase is (C-1).
Here, if the pulse phase at point A is (C) in (e) of FIG. 27, the interpolation phase decreases from point A and becomes zero, that is, the pulse phase at time t73 is originally of (C). As a result, the pulse phase shown in FIG. 27D at time t73 needs to be corrected by adding 1.
Thus, the reason why the pulse phase needs to be corrected is that it is impractical to set both the level Vh for detecting '1' and the level Vl for detecting '0' to zero in realizing the comparator 3. Or it is impossible to realize, and it cannot be prohibited that Vh and Vl are as shown in FIG. 15 or FIG.

When the sine wave incremental encoder 1b rotates in the reverse rotation direction, the correction process according to the present embodiment described above for the A phase can be summarized as follows. When the phase A digital value VA detects zero at the phase rising time t73 and the synchro phase A signal QA detects '1' as shown in FIG. 27B, the Vh is smaller than zero. 27, it is determined that the place where the sync A phase signal QA should be “0” is changed to “1” at an early stage and the pulse phase is excessively counted down, and the time shown in FIG. A correction is made by adding 1 to the pulse phase (C-1) at t73 and returning to (C).
Similarly, the microcontroller 9 detects that the A-phase digital value VA is zero at the falling time t74 of the A-phase shown in (a) of FIG. 27, and the synchro A as shown in (b) of FIG. When phase signal QA detects '0', Vl is greater than zero, and the sync A phase signal QA should change to '0' at an early stage, resulting in an extra pulse phase. It is determined that the count is down, and correction is performed by adding 1 to the pulse phase (C-3) at time t74 in FIG.
The phase A has been described above. Similarly, for the phase B, the microcontroller 9 detects that the phase B digital value VB is zero at times t75 and t76 in FIG. The same processing is performed.

When the comparator 3 of FIG. 13 described above has the operating characteristics of FIG. 19, the correction of the pulse phase described in FIG. 26 at the time of forward rotation and FIG. 27 at the time of reverse rotation is performed by the microcontroller. FIG. 28 shows an example in which the program of No. 9 is implemented. First, the microcontroller 9 performs the following processing of blocks f1, f2 and f3 in FIG.
f1: After inputting the A-phase digital value VA, the B-phase digital value VB, the synchronized A-phase signal QA, the synchronized B-phase signal QB and the pulse phase, go to f2.
f2: When VA is zero, go to f4, and when VA is not zero, go to f3.
f3: When VB is zero, the process proceeds to f4. When VB is not zero, the pulse phase is not corrected and the process is finished through the route f3n.
Thus, when the A-phase digital value VA or the B-phase digital value VB is zero, the correction of the pulse phase according to FIGS. 26 and 27 is performed, and the process proceeds to block f4.
Next, in block f4, the rotation direction of the sine wave incremental encoder 1b is detected, and during forward rotation, the correction of the pulse phase is not necessary as described in FIG. When the rotation is reversed, the process proceeds to block f15, and the pulse phase correction described with reference to FIG. 27 is performed.
The rotation direction may be detected by, for example, normal rotation if the pulse phase has increased from the previous scan, and reverse rotation if it has decreased.

The block f15 in FIG. 28 determines whether the A-phase digital value VA is zero or the B-phase digital value VB is zero. Blocks f16 to f18 indicate that the A-phase VA is zero. This relates to the correction of the pulse phase, and the following processing is performed with reference to FIG.
f15: When VA is zero, the process proceeds to f16, and the pulse phase is corrected by the A phase. When VA is not zero, VB is zero and the process proceeds to f19 to correct the pulse phase by the B phase.
f16: When VA is zero and VB is negative, the process proceeds to f18 when VA rises. When VA is zero and VB is positive, the process proceeds to f17 when VA falls.
f17: At this time, when VA falls, it becomes zero. If QA is '0' at this time, QA becomes '0', but since the pulse phase is excessively counted down, the process proceeds to f22. Then, correction is performed by adding 1 to the pulse phase. When QA is “1”, no correction is necessary, and the process is finished through f21n.
f18: At this time, when VA rises to zero, if QA is '1' at this time, QA becomes '1', but since the pulse phase is excessively down-counted, the process proceeds to f22, Correction is performed by adding 1 to the pulse phase. When QA is “0”, no correction is necessary, and the process ends through f21n.
Next, blocks f19 to f21 relate to correction of the pulse phase when the VB of the B phase is zero, and the following processing is performed with reference to FIG.
f19: When VB is zero and VA is positive, the process proceeds to f21 when VB rises. When VB is zero and VA is negative, the process proceeds to f20 when VB falls.
f20: At this time, when VB falls to zero, when QB is “0”, QB becomes “0”, but since the pulse phase is excessively counted down, the process proceeds to f22. Correction is performed by adding 1 to the pulse phase. When QB is “1”, no correction is necessary, and the process is finished through f21n.
f21: At this time, when VB rises to zero, if QB is '1', QB becomes '1', but since the pulse phase is excessively down-counted, the process proceeds to f22, Correction is performed by adding 1 to the pulse phase. When QB is “0”, no correction is necessary, and the process is finished through f21n.

Thus, when the comparator 3 in FIG. 13 performs the operation shown in FIG. 19, the sine wave incremental encoder 1b rotates in the forward direction and in the reverse direction, as shown in FIGS. As shown in FIG. 28, when the microcontroller 9 detects the A-phase digital value VA or the B-phase digital value VB of the sine wave incremental encoder 1b as zero, the pulse phase is corrected.
Thus, the correct pulse phase is always detected even when the sine wave incremental encoder 1b rotates at a high speed as well as a low speed.

To summarize, a sine wave incremental encoder that outputs two phase A and B phase sine waves with a phase difference of 90 ° and a Z phase indicating a reference signal of one rotation can be used. Regardless of the Z phase signal, an accurate reference origin signal is generated, and the sync A phase signal, sync B phase signal, pulse phase, A phase digital value and B phase digital value are detected from the A phase and B phase signals, The synchro A phase signal, synchro B phase signal and pulse phase are configured to operate in complete synchronization, and the synchro A phase signal and synchro B phase signal are converted to the micro signal based on the A phase digital value and the B phase digital value. The combination of the pulse phase and the interpolation phase is monitored at any time by monitoring the controller 9 and repeatedly executing the correction processing of all the pulse phases shown in FIGS. 18, 22, 25 and 28. We are possible to correctly detect.
Further, as shown in the figure, the sine wave incremental encoder 1b shown in FIG. 13 has a rotational phase with a resolution exceeding 20 bits by simply connecting the phase velocity detection device to the A-phase, B-phase and Z-phase signal lines. It can be obtained stably and is extremely cost-effective.

FIG. 29 is a diagram for explaining the overall configuration of the fifth embodiment, and FIG. 30 further explains the operation of the fifth embodiment.
First, in FIG. 29, 2e is a phase velocity detector, 15 is a NOT gate, 16 is a D flip-flop, 17, 18 and 20 are i-bit, 2-bit and m-bit data latches, respectively. At the rising edge, the D input is latched and sent to the Q output. Reference numeral 19 is a reference counter, and 21 is a parallel input port. In addition, what attaches | subjects the same symbol as FIG. 13 has the same function as these, and omits the description.

Further, in FIG. 29, the NOT gate 15 supplies a signal obtained by inverting the reference clock CLK of the output of the transmitter 5 to the CLK input of the D flip-flop 16, and is applied to the D input of the D flip-flop 16. Is latched and output. That is, the signal at the D input of the D flip-flop 16 is synchronized with the falling edge of the reference clock.
Here, it is assumed that latching is performed at the falling edge instead of the rising edge of the reference clock CLK. The signal applied to the D input of the data latches 17, 18 and 20 described later changes at the rising edge of the reference clock CLK. For the sake of convenience, this is to satisfy the setup time of the data input from the D input to the CLK input of the data latch.
The latch command output from the microcontroller 9 at an arbitrary timing is synchronized with the falling edge of the reference clock CLK by the D flip-flop 16 via the parallel output port 10 and then the A The A / D conversion start of the / D converters 13 and 14 and the D input latch of the data latches 17, 18 and 20 are simultaneously performed.

Next, the data latch 17 receives the pulse phase output from the pulse phase detector 8, and the data latch 18 receives the sync A phase signal and sync B phase signal output from the pulse extractor 6. To do.
The reference counter 19 is an m-bit counter that operates at the rising edge of the reference clock CLK. The reference counter 19 outputs a base time, which is input to the data latch 20. The microcontroller 9 sends the A-phase digital values and B-phase digital values of the A / D converters 13 and 14 to the data latches 17, 18 and 20 via parallel input ports 11, 12 and 21. By inputting an output, the A phase digital value, the B phase digital value, the pulse phase, the synchronized A phase signal, the synchronized B phase signal and the base time at the same time synchronized with the falling edge of the reference clock CLK are obtained. It will be.

  Further, the operation of speed detection according to the present invention shown in FIG. 29 will be described with reference to FIG. FIG. 30A shows the scanning state of the microcontroller 9, and the microcontroller 9 executes various jobs such as control of an electric motor (not shown in FIG. 29). It is assumed that the rotation phase and the rotation speed of the incremental encoder 1b are detected for each scan in, for example, periods represented by M1 and M2, which are '1' at times t1 and t2 shown in FIG. Next, FIG. 30B shows a latch command applied to the D input of the D flip-flop 16 by the microcontroller 9, FIG. 30C shows the reference clock CLK, and FIG. It represents a synchronized latch command sent from the Q output of the D flip-flop 16. The microcontroller 9 outputs a latch command within a period M1 starting from time t1 in FIG. 30A, and the latch command is sent to the D input of the D flip-flop 16 via the parallel output port 10. In addition, a latch command is issued as indicated by R1 in FIG. The latch command R1 is synchronized by the D flip-flop 16 with the falling edge of the reference clock CLK at time t11 in FIG. 30C, and is synchronized as indicated by S1 in FIG. Latch command.

Next, (e) in FIG. 30 shows the A-phase signal and B-phase signal of the sine wave incremental encoder 1b, and (f) in FIG. 30 shows virtually continuous interpolation phases that can be calculated by the microcontroller 9. FIG. 30 (g) shows the temporal transition of the pulse phase output from the pulse phase detector 8. FIG.
Then, at time t11 according to the synchronized latch command S1 in FIG. 30 (d), the outputs of the A / D converters 13 and 14 become the A-phase digital value at the point U1 in FIG. 30 (e). The B phase digital value at the point V1 is held, and in FIG. 30G, the pulse phase (C-1) is held in the data latch 17, and although not shown in FIG. 30, the synchro A phase in FIG. The signal and the sync B phase signal are held in the data latch 18, and the base time is held in the data latch 20.
Next, the microcontroller 9 inputs the held data from the A / D converters 13 and 14 and the data latches 17, 18 and 20 within the period M1 in FIG. Based on the A phase digital value at the point U1 and the B phase digital value at the point V1, the interpolation phase at the point W1 in (f) of FIG. 30 is calculated.

Although the processing at the time t1 of the microcontroller 9 has been described above, the same processing is performed at the time t2 of the next scan.
That is, the microcontroller 9 outputs a latch command in the period M2 starting from the time t2 in FIG. 30A, and the signal applied to the D input of the D flip-flop 16 is as shown in FIG. As shown in R2 of b), a latch command is issued.
The latch command R2 is synchronized with the falling edge of the reference clock CLK at time t21 in FIG. 30C, and becomes a synchronized latch command as indicated by S2 in FIG. At time t21 by the synchronized latch command S2, the outputs of the A / D converters 13 and 14 hold the A-phase digital value at the point U2 and the B-phase digital value at the point V2 in FIG. 30 (g), the pulse phase (C + 2), and although not shown in FIG. 30, the sync A phase signal, sync B phase signal and the base time in FIG. , 18 and 20. The microcontroller 9 inputs the held data from the A / D converters 13 and 14 and the data latches 17, 18, and 20 within the period M2 in FIG. From the A-phase digital value at point U2 and the B-phase digital value at point V2, the interpolation phase at point W2 in (f) of FIG. 30 is calculated.

Here, the feature of this embodiment is that the pulse phase of the sine wave incremental encoder 1b is determined at an arbitrary time determined by the scanning of the microcontroller 9 shown in FIG. 30A, for example, t1 and t2. By obtaining the interpolation phase, it is possible to always detect the rotational phase accurately, and for this reason, for example, the amount of change in the rotational phase between times t11 and t21 is also detected with extremely high accuracy.
Referring to (c) of FIG. 30, the base time by the reference counter 19 latched and inputted at time t11 is counted up to the rising edge of the reference clock CLK at time t12. The base time by the reference counter 19 latched and input at t21 is counted up to the rising edge of the reference clock CLK at time t22.
The scan time obtained by multiplying the base time obtained at time t11 by subtracting the base time obtained at time t21 and the period of the reference clock CLK is shown in FIG. Time ΔT1 is reached.

  Here, the oscillator 5 uses a crystal oscillator with extremely high accuracy, and the reference clock CLK output from the oscillator 5 is stable in frequency and with a constant waveform duty. The time ΔT1 is equal to the time ΔT11 illustrated in FIG. The scan time ΔT11 obtained in this way is obtained by multiplying the number of pulses of the reference clock CLK between two separate edges of the reference clock CLK by the period of the reference clock CLK, thereby obtaining a very accurate scan time. Is. Then, the rotation speed of the sine wave incremental encoder 1b, for example, in FIG. 30, is obtained by subtracting the rotation phase at the time t11 from the rotation phase consisting of the pulse phase and the interpolation phase at the time t21, and the rotation phase at the scan time ΔT11. Is obtained by dividing the change amount by the scan time ΔT11, and the change amount of the rotation phase and the scan time ΔT11 according to the present invention are detected with extremely high accuracy. The rotational speed of the sine wave incremental encoder 1b obtained by calculating the scan time can be made extremely accurate.

  According to the present invention, when the sine wave incremental encoder 1b rotates in the forward direction or in the reverse direction, whether the sine wave incremental encoder 1b is rotated at a high speed as well as a stop or a low speed, The origin detector 7 generates an accurate reference for one rotation from the Z-phase signal, and corrects the pulse phase according to FIG. 18, FIG. 22, FIG. 25 and FIG. It is possible to detect the rotation phase and rotation speed with high accuracy by the interpolation phase, thereby realizing high-accuracy synchronous control and high-speed positioning control between a plurality of electric motors such as a shaftless rotary printing press.

1 is a diagram illustrating an overall configuration of Example 1. FIG. It is a figure explaining operation | movement of the pulse extractor of FIG. 1 in detail at the time of forward rotation. It is a figure explaining operation | movement of the pulse extractor of FIG. 1 in detail at the time of reverse rotation. It is a figure explaining one Example of a pulse extractor. FIG. 6 is a diagram illustrating an overall configuration of a second embodiment. It is a figure explaining the signal which a sine wave incremental encoder outputs. It is a figure explaining the operation | movement of an origin detector in detail. It is a figure explaining one Example of an origin detector. It is a figure explaining operation | movement of one Example of the origin detector of FIG. FIG. 10 is a diagram illustrating an overall configuration of a third embodiment. It is a figure explaining one Example of a pulse phase detector. It is a figure explaining operation | movement of one Example of the pulse phase detector of FIG. FIG. 10 is a diagram illustrating an overall configuration of a fourth embodiment. It is a figure explaining the whole operation | movement of Example 4 of FIG. It is a figure explaining the operation | movement 1 of a comparator. FIG. 1 is a diagram for explaining correction of a pulse phase. FIG. 2 is a diagram for explaining correction of a pulse phase. It is a figure explaining the Example of correction | amendment of the pulse phase of FIG. 16 and FIG. It is a figure explaining the operation | movement 2 of a comparator. FIG. 3 is a third diagram illustrating correction of pulse phase. FIG. 4 is a diagram for explaining correction of a pulse phase. It is a figure explaining the Example of correction | amendment of the pulse phase of FIG. 20 and FIG. FIG. 5 is a diagram for explaining correction of a pulse phase—part 5; FIG. 6 is a diagram for explaining correction of a pulse phase—part 6; It is a figure explaining the Example of correction | amendment of the pulse phase of FIG. 23 and FIG. FIG. 7 is a diagram for explaining correction of a pulse phase—part 7; FIG. 8 is a diagram for explaining correction of a pulse phase; It is a figure explaining the Example of correction | amendment of the pulse phase of FIG. 26 and FIG. FIG. 10 is a diagram illustrating an overall configuration of a fifth embodiment. It is a figure explaining speed detection. It is a figure explaining an incremental signal. It is a figure explaining the phase detection of 1 rotation. It is a figure explaining the detection of the conventional rotation phase.

Explanation of symbols

1a sine wave incremental encoder 1b sine wave incremental encoder 2a phase velocity detector 2b phase velocity detector 2c phase velocity detector 2d phase velocity detector 2e phase velocity detector 3 comparator 4 comparator 5 transmitter 6 pulse extractor 601 NOT gate 602 D flip-flop 603 NOT gate 604 D flip-flop 605 NOT gate 606 D flip-flop 607 NOT gate 608 D flip-flop 609 NOT gate 610 AND gate 611 OR gate 612 OR gate 613 D flip-flop 614 D flip-flop 615 D flip-flop 616 D Flip flop 7 Origin detector 701 NOT gate 702 JK flip flop 703 D flip Flop 704 D flip-flop 705 NOT gate 706 NOT gate 707 NOT gate 708 AND gate 709 AND gate 710 OR gate 8 pulse phase detector 801 up / down counter 802 coefficient unit 803 adder 804 selector 9 microcontroller 10 parallel output port 11 parallel output Input port 12 Parallel input port 13 A / D converter 14 A / D converter 15 NOT gate 16 D flip-flop 17 Data latch 18 Data latch 19 Counter 20 Data latch 21 Parallel input port

Claims (6)

Rotating the sine wave incremental encoder by inputting the A phase signal and the B phase signal of a sine wave incremental encoder that outputs two sine wave A phase signals and B phase signal incremental signals having a 90 ° phase difference. A phase velocity detection device for detecting a phase velocity,
The sine wave incremental encoder outputs a plurality of cycles of the A-phase signal and the B-phase signal for each rotation, and a Z-phase signal for identifying one rotation .
The phase velocity detector includes an A-phase and B-phase comparator and pulse extractor, the Z-phase comparator and origin detector, and a pulse phase detector.
The comparator generates a binarized rectangular A phase signal and a rectangular B phase signal from the A phase signal and the B phase signal, respectively, and outputs them to the pulse extractor.
The pulse extractor uses the rectangular A-phase signal and the rectangular B-phase signal to generate a normal rotation pulse signal synchronized with the clock signal when the sine wave incremental encoder rotates in the normal direction, and a reverse rotation pulse signal synchronized with the clock signal during the reverse rotation. Is extracted and output, and
Outputting a synchronized A phase signal and a synchronized B phase signal in which the rising and falling edges of the rectangular A phase signal and the rectangular B phase signal are synchronized with the clock signal ;
The Z-phase comparator generates a rectangular Z-phase signal binarized from the Z-phase signal,
To the origin detector, the normal rotation pulse and the reverse rotation pulse output from the pulse extractor and the rectangular Z-phase signal are input,
The origin detector identifies a rotation direction of the sine wave incremental encoder according to whether the forward rotation pulse or the reverse rotation pulse is output,
When the sine wave incremental encoder is rotating in the forward direction, a reference origin signal having a short predetermined pulse width is output from the front or rear end of the rectangular Z-phase signal,
When the sine wave incremental encoder rotates in the reverse direction, a reference origin signal having a short predetermined pulse width is output from the rear end or front end of the rectangular Z-phase signal,
The pulse phase detector includes an up / down counter for counting and outputting a value sufficiently larger than a maximum pulse phase based on the number of cycles per rotation of the A phase signal and the B phase signal of the sine wave incremental encoder, and a selection unit. Preparation
The forward pulse and the reverse pulse output from the pulse extractor are input to the upcount terminal and the downcount terminal of the up / down counter of the pulse phase detector, respectively, and the reset terminal of the up / down counter is connected to the reset terminal of the up / down counter. The reference origin signal output from the origin detector is input,
The up / down counter counts up when the forward rotation pulse is input, counts down when the reverse rotation pulse is input, and is reset to zero when the reference origin signal is input to the reset terminal. ,
When the output of the up / down counter is positive, the selection means outputs the count value as a pulse phase of the sine wave incremental encoder,
When the output of the up / down counter is negative, the maximum pulse number obtained by adding 1 to the maximum pulse phase and the count value of the up / down counter are added as the pulse phase of the sine wave incremental encoder < A phase velocity detector characterized by the above. The phase velocity detection device includes an A / D converter and a controller,
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values,
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal with a level Vh that determines the A-phase signal and the B-phase signal as a high level and a level Vl that determines a low level. The rectangular A-phase signal and the rectangular B-phase signal are generated, and the Vh is not less than the Vl,
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. Value and B phase digital value are input continuously,
When the sine wave incremental encoder is rotating in the normal rotation, when the A phase digital value is positive and the synchro A phase signal is '0', correction is performed by adding 1 to the pulse phase, and the A phase When the digital value is negative and the synchro A-phase signal is '1', the pulse phase is corrected by adding 1;
Further, when the B-phase digital value is positive and the synchronized B-phase signal is “0”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is negative and the synchronized B-phase signal is “1”. If ', perform correction to add 1 to the pulse phase,
When the sine wave incremental encoder rotates in reverse, when the A phase digital value is positive and the synchro A phase signal is '0', correction is performed to subtract 1 from the pulse phase, and the A phase digital When the value is negative and the synchro A phase signal is '1', a correction is made to subtract 1 from the pulse phase,
When the B-phase digital value is positive and the synchronized B-phase signal is “0”, correction is performed by subtracting 1 from the pulse phase, and the B-phase digital value is negative and the synchronized B-phase signal is “1”. 'phase velocity detecting apparatus according to claim 1 characterized by performing a correction to subtract 1 for the pulse phase when the. The phase velocity detection device includes an A / D converter and a controller,
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values,
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal with a level Vh that determines the A-phase signal and the B-phase signal as a high level and a level Vl that determines a low level. Generating the rectangular A phase signal and the rectangular B phase signal, wherein Vh is less than Vl;
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. Value and B phase digital value are input continuously,
When the sine wave incremental encoder is rotating in the forward direction, when the A phase digital value is negative and the synchro A phase signal is '1', correction is performed to subtract 1 from the pulse phase, and the A phase When the digital value is positive and the synchro A phase signal is '0', the pulse phase is corrected by subtracting 1;
Further, when the B-phase digital value is negative and the synchronized B-phase signal is “1”, correction is performed by subtracting 1 from the pulse phase, and the B-phase digital value is positive and the synchronized B-phase signal is “0”. If ', perform correction to subtract 1 for the pulse phase,
When the sine wave incremental encoder rotates in reverse, if the A phase digital value is negative and the synchro A phase signal is '1', a correction is made to add 1 to the pulse phase, and the A phase digital When the value is positive and the synchro A phase signal is '0', a correction is made by adding 1 to the pulse phase,
Further, when the B-phase digital value is negative and the synchronized B-phase signal is “1”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is positive and the synchronized B-phase signal is “0”. 'phase velocity detecting apparatus according to claim 1 characterized by performing the correction of adding 1 for the pulse phase when the. The phase velocity detection device includes an A / D converter and a controller,
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values,
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal with a level Vh that determines the A-phase signal and the B-phase signal as a high level and a level Vl that determines a low level. The rectangular A-phase signal and the rectangular B-phase signal are generated, and the Vh is not less than the Vl,
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. Value and B phase digital value are input continuously,
When the sine wave incremental encoder is rotating forward, when the A phase digital value is zero, the B phase digital value is positive, and the synchro A phase signal is '0', 1 is added to the pulse phase. When the A-phase digital value is zero, the B-phase digital value is negative, and the synchro A-phase signal is '1', a correction for adding 1 to the pulse phase is performed.
Further, when the B-phase digital value is zero, the A-phase digital value is negative, and the synchronized B-phase signal is “0”, correction is performed by adding 1 to the pulse phase, and the B-phase digital value is zero. When the A-phase digital value is positive and the synchro B-phase signal is '1', correction is performed by adding 1 to the pulse phase,
When the sine wave incremental encoder is rotating in reverse, the pulse phase is not corrected when the A phase digital value is zero, and the pulse phase is also corrected when the B phase digital value is zero. 2. The phase velocity detection device according to claim 1 , wherein the phase velocity detection device is not performed. The phase velocity detection device includes an A / D converter and a controller,
The A / D converter outputs an A-phase digital value and a B-phase digital value obtained by converting the A-phase signal and the B-phase signal output from the sine wave incremental encoder into digital values,
The A-phase and B-phase comparators compare the A-phase signal and the B-phase signal with a level Vh that determines the A-phase signal and the B-phase signal as a high level and a level Vl that determines a low level. Generating the rectangular A phase signal and the rectangular B phase signal, wherein Vh is less than Vl;
The controller includes the pulse phase output from the pulse phase detector, the synchronized A-phase signal and the synchronized B-phase signal output from the pulse extractor, and the A-phase digital signal output from the A / D converter. Value and B phase digital value are input continuously,
When the sine wave incremental encoder is rotating forward, the pulse phase is not corrected when the A-phase digital value is zero, and the pulse phase is also corrected when the B-phase digital value is zero. Without doing
When the sine wave incremental encoder rotates in reverse, when the A phase digital value is zero, the B phase digital value is negative and the synchro A phase signal is '1', 1 is added to the pulse phase. Correction is performed, and when the A phase digital value is zero, the B phase digital value is positive, and the synchro A phase signal is '0', correction is performed by adding 1 to the pulse phase,
When the B-phase digital value is zero, the A-phase digital value is positive, and the synchronized B-phase signal is '1', correction is performed by adding 1 to the pulse phase, and the B-phase digital value is zero and the A phase wherein the digital value is negative synchro B-phase signal is "0" the phase velocity detecting apparatus according to claim 1 characterized by performing the correction of adding 1 for the pulse phase when the. The phase velocity detection device includes a reference counter that counts pulses output from the transmitter and a data latch,
According to a latch command synchronized with the edge of the pulse output from the transmitter, the output value of the reference counter, the pulse phase, the synchronized A-phase signal, the synchronized B-phase signal, the A-phase digital value, and the B at the same time. Latch the phase digital value and input it to the controller at predetermined time intervals;
The controller detects a change amount of the rotation phase of the sine wave incremental encoder from the change amount of the output value of the reference counter in the time interval, and detects the change amount of the sine from the change amount of the time interval and the rotation phase. 6. The phase velocity detection device according to claim 2 , wherein the rotation velocity of the wave incremental encoder is calculated and detected.

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