JP6903543B2 - ABZ phase divider - Google Patents

Description

The present invention relates to frequency division processing of A-phase signal, B-phase signal, and Z-phase signal output by a high-resolution incremental encoder.

Incremental encoders are attached to drive devices such as motors and rollers such as other manufacturing devices and conveyors to detect the speed, moving distance, or shifting angle of a rotating body or moving body. The incremental encoder outputs A-phase signals and B-phase signals, which are pulse trains with a 90-degree phase difference, in order to detect forward and reverse rotations, and in addition, 1 for each rotation. Some output a Z-phase signal, which is one pulse.

Further, the number of pulses per rotation (the number of incremental signals) output by the incremental encoder is 600 PPR (PPR is Pulse Per Round), 1024 PPR, or the like, which has a normal accuracy, in the conventional control device. ..
In recent years, in control devices, incremental encoders such as 9600PPR, 19200PPR, and 8192PPR have come to be used when high accuracy is required for the detection speed and the transition angle. This high-precision incremental encoder has a high frequency of output A-phase signal, B-phase signal, and Z-phase signal.
When such a high-precision incremental encoder is used, the motor drive device and the like used in combination are newly developed or remodeled to prepare and use the interface of the incremental encoder.

On the other hand, there is a need for the incremental encoder not only to be used in combination with a motor drive device, but also to be used at the same time as another device such as a conventional or third-party display device, monitor device, or other control device. In such a case, such another device does not support a high-precision, high-frequency incremental encoder, and has a disadvantage that it cannot be used.

As a solution to this, there is a method of dividing a signal and using it, and it is a well-known technique to divide one signal output by the incremental encoder, for example, an A-phase signal. For example, if the A-phase signal of the 8192PPR incremental encoder is divided by one-eighth, it becomes a 1024PPR signal.

Further, as a solution different from the above, a technique for dividing the two A-phase signals and the B-phase signals output by the incremental encoder is disclosed in Patent Documents 1 and 2.
Patent Document 1 discloses a technique in which a half frequency dividing circuit is subordinately connected to divide an A-phase signal and a B-phase signal. Further, in Patent Document 2, a frequency division circuit based on the frequency division ratio E is disclosed, and it is presumed that the frequency division ratio E does not depend on the frequency division ratio of 1 / power of 2.

Japanese Patent Application Laid-Open No. 5-99947 Public Relations Japanese Unexamined Patent Publication No. 7-12588

Both Patent Document 1 and Patent Document 2 relate to the division of the A-phase signal and the B-phase signal among the signals output by the incremental encoder, and do not seem to describe the division of the Z-phase signal. .. Here, when the incremental encoder outputs not only the A-phase signal and the B-phase signal but also the Z-phase signal, the A-phase signal, the B-phase signal, and the Z-phase signal that divide all three signals are divided. A frequency divider (hereinafter referred to as an ABZ phase frequency divider) is required.
That is, the subject of the present invention is to provide the ABZ phase frequency divider device that divides the frequency by maintaining the mutual phase relationship between the original A-phase signal, B-phase signal, and Z-phase signal, instead of simply dividing the frequency. It is to be realized.

In the present invention, the above problems are solved as follows.
(1) The present invention comprises an incremental encoder and an ABZ phase frequency divider that inputs an A-phase signal, a B-phase signal, and a Z-phase signal output by the incremental encoder. There is a feature in. Then, the incremental encoder outputs the A-phase signal and the B-phase signal, which are pulse trains having a phase difference of 90 degrees according to the rotation, and outputs the Z-phase signal for each rotation.

Further, the frequency divider has a built-in pulse converter and a counter, and the pulse converter inputs the A-phase signal and the B-phase signal to obtain a frequency obtained by multiplying the frequencies of the A-phase signal and the B-phase signal by an integral number. The multiplication signal and the rotation direction signal indicating the rotation direction of the incremental encoder are detected. Next, the counter is an up / down counter that inputs the multiplication signal, the rotation direction signal, and the Z phase signal, and the counter ups or down counts the multiplication signal according to the rotation direction signal. outputs a count value each, further the counter, the Z-phase signal is to clear the previous SL count value when it becomes active.

The present invention is characterized in that the frequency dividing device is provided with a selector, a frequency dividing AB phase generator, a plurality of frequency dividing Z phase pulse width setting devices, and a comparator, and the selector is a count output by the counter. A continuous 2-bit signal is selected from the value and output. Next, the frequency dividing AB phase generator divides the frequency from the 2-bit signal by a frequency dividing ratio of 1 / K (K is a positive integer) while maintaining the phase relationship between the A phase signal and the B phase signal. It was peripheral, and the feature to generate a division a-phase signal and the divided B-phase signal.

Then the plurality of dividing Z phase pulse width setting unit, and a comparator monitors the count value always the pulse width count value as a base point to zero for the previous SL Z phase signal, the partial a pulse width which is a reciprocal of K of division ratio 1 / K, is a feature to produce the divided Z-phase signal in synchronization with the Z-phase signal.

Such the present invention, especially in that the A-phase signal, B-phase signal, and Z-phase signals divided from pre Symbol dividing A-phase signal, for generating a frequency division B-phase signal, and dividing the Z-phase signal It is an ABZ phase frequency divider.

(2) Further, in the ABZ phase frequency divider device, the pulse width of the frequency division Z phase signal is made variable by changing the values of the plurality of frequency division Z phase pulse width setters to predetermined values. This is an ABZ phase frequency divider.

The effect of the present invention is that even if the A-phase signal, the B-phase signal, and the Z-phase signal output by the high-resolution incremental encoder have a high frequency, a low frequency can be obtained by using the ABZ-phase frequency divider of the present invention. A frequency-divided A-phase signal, a frequency-divided B-phase signal, and a frequency-divided Z-phase signal can be obtained.
This makes it possible to use a high-resolution incremental encoder in combination with a recent control device with excellent performance, and at the same time, use it with a conventional or third-party display device, monitor device, or another control device. ..

It is a block diagram which shows the structure of the Example of this invention. (Example 1) It is a figure explaining the operation of a pulse converter 11 and a counter 12. (Example 1) It is a figure which expands and explains a part of FIG. (Example 1) It is a figure explaining the detail of a selector 13. (Example 1) It is a figure explaining the generation of the frequency division A phase signal A2 and the frequency division B phase signal B2. (Example 1) It is a figure explaining the mechanism which generates the frequency division Z phase signal Z2. (Example 1 and Example 2) It is a figure explaining the generation of the frequency division Z phase signal Z2. (Example 1)

Hereinafter, a diagram of an embodiment of the present invention will be shown and described. FIG. 1 describes the configuration of the first embodiment, FIGS. 2 to 7 explain the operation of each part of the first embodiment in detail, and FIGS. 6 and 2 explain the second embodiment. Is.

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention, in which 1 and 2 are an incremental encoder and an ABZ phase frequency divider according to the present invention, respectively. The incremental encoder 1 outputs an A-phase signal A1, a B-phase signal B1, and a Z-phase signal Z1, and the A-phase signal A1 and the B-phase signal B1 are pulse trains generated according to rotation with a 90-degree phase difference. , When the rotation direction changes, the phase difference becomes opposite. Further, the incremental encoder 1 outputs the Z-phase signal Z1 for each rotation.

Next, the ABZ phase frequency dividing device 2 incorporates the devices 11 to 24 shown in the figure, 11 and 12 are well-known devices, and the devices 13 and later constitute the features of the present invention.
First, 11 and 12 are a pulse converter and a counter, respectively, and the pulse converter 11 inputs the A-phase signal A1 and the B-phase signal B1 output by the incremental encoder 1 and inputs a multiplication signal and a rotation direction signal DR. Is output. The multiplied signal has a frequency of 1, 2, or 4 times the frequency of the A-phase signal A1, but in FIG. 1, the multiplied signal is 4F when the frequency is 4 times.

Subsequently, the counter 12 inputs the multiplication signal 4F, the rotation direction signal DR, and the Z-phase signal Z1 and outputs the count value C. Further, the counter 12 is an up / down counter, and the multiplication signal 4F is counted up or down according to the rotation direction signal DR, and a count value C is output. Here, in FIG. 1, the count value C is expressed as C (n-1), C (n-2), and ~ C0 in n-digit binary numbers.
The operations of the pulse converter 11 and the counter 12 will be further described later with reference to FIGS. 2 and 3.

Similarly, in FIG. 1, 13 and 14 are a selector and an NXOR gate, respectively. First, the selector 13 inputs a count value C by the counter 12 and a selection signal S corresponding to a division ratio of 1 / K (K is a power of 2), and the selection signal S is output from a microcomputer (not shown). It is a thing. Then, the selector 13 selects two consecutive bits of the counter C with the selection signal S, and outputs the upper digit bit from Y1 and the lower digit bit from Y0.

The signal output from the Y1 is the frequency-divided A-phase signal A2, and the frequency-divided B-phase signal B2 is obtained by calculating the outputs of the Y0 and Y1 by the NXOR gate 14. That is, the output Y1 of the selector 13 and the NXOR gate 14 constitute a frequency-dividing AB phase generator, and the A-phase signal A1 and the B-phase signal B1 output by the incremental encoder 1 are the selection signals. The frequency division is divided by the frequency division ratio 1 / K specified by S, and the frequency division A phase signal A2 and the frequency division B phase signal B2 are generated.
The details of the generation of the divided A-phase signal A2 and the divided B-phase signal B2 by the selector 13 and the NXOR gate 14 will be further described later in FIGS. 4 and 5.

Similarly, in FIG. 1, 15, 17, 19, and 22 are frequency-dividing Z-phase pulse width setters, 16, 18, 20, and 23 are comparators, and 21 and 24 are AND gate and OR gate, respectively. OR from frequency dividing Z phase pulse width setting unit 15 gate 24 constantly monitors the count value C, the base point the count value C is zero, the pulse width of the Z-phase signal Z1, before Symbol min It generates a frequency-divided Z-phase signal Z2 having a pulse width that is several times (K times) the inverse of the frequency ratio 1 / K.
The generation of the frequency-divided Z-phase signal Z2 will be further described later in FIGS. 6 and 7.

Next, the operations of the pulse converter 11 and the counter 12 of FIG. 1 will be described with reference to FIGS. 2 and 3.
First, FIG. 2 shows the waveforms of the signals of the incremental encoder 1, the pulse converter 11, and the counter 12 with the passage of time, and FIG. 2A, (b), and ( c) represents the transition of the waveforms of the A-phase signal A1, the B-phase signal B1, and the Z-phase signal Z1 output by the incremental encoder 1, respectively. Then, as shown in FIG. 2C, the Z-phase signal Z1 is a one-pulse signal output by the incremental encoder 1 at times T1, T2, T3, T4, and T5 for each rotation.

Subsequently, (d) and (e) of FIG. 2 represent the temporal transitions of the multiplication signal 4F and the rotation direction signal DR output by the pulse converter 11, respectively. Further, (f) of FIG. 2 shows the state of rotation of the incremental encoder 1 and is as follows.
About (f) in Fig. 2 Rotation in forward rotation until time T21 Rotation in forward rotation from time T21 to T22, Stop time T22 to T41 Rotation in reverse rotation After time T41 Rotation in (f) of Fig. 2 With reference to the state of (e), the rotation direction signal DR in FIG. 2 (e) detects forward rotation at 0 and reverse rotation at 1.

これを数値例で示せば、１回転当たりのパルス数を８，１９２ＰＰＲとし、前記逓倍信号は４Ｆとしているのでここでは逓倍率が４となり、前記最大カウント値Ｃｍａｘは次の数式２の値となる。
(数２)

Then, (g) of FIG. 2 represents the temporal transition of the count value C output by the counter 12, and the count-up operation is performed when the incremental encoder 1 rotates in the forward direction, and the count-down operation is performed when the incremental encoder 1 rotates in the reverse direction. Further, at the times T1, T2, T3, and T4 when the Z-phase signal Z1 becomes 1, the count value C is cleared to zero.
Further, the maximum count value Cmax at + Cmax and −Cmax is a value according to the following formula 1.
(Number 1)

If this is shown by a numerical example, the number of pulses per rotation is 8,192 PPR, and the multiplication signal is 4F. Therefore, the multiplication factor is 4 here, and the maximum count value Cmax is the value of the following equation 2. ..
(Number 2)

Next, FIG. 3 shows an enlarged time between the times T21 and T22 in order to clarify the operations of (a), (b), (d), and (g) of FIG. (A) to (g) of FIG. 3 represent the same signals as those having the same reference numerals in FIG. Further, the temporal transitions of (c), (e), and (f) of FIG. 3 are the same as those of FIG. 2, and the description thereof will be omitted.

Regarding (a) and (b) of FIG. 3, the phase of the A-phase signal A1 is 90 degrees ahead of the B-phase signal B1 when the normal rotation occurs until the time T21, and the above-mentioned A when the time is reversed after the time T22. The phase signal A1 is delayed by 90 degrees. Further, the multiplication signal 4F in FIG. 3 (d) is generated by detecting the rising and falling edges of the A-phase signal A1 and the B-phase signal B1.
Next, the (g) count value C in FIG. 3 is up-counted or down-counted as shown by the (d) multiplication signal 4F and (e) rotation direction signal DR in FIG.

Here, the pulse converter 11 and the counter 12 are well-known devices, but the operations of the 11 and 12 are described with reference to FIGS. 2 and 3 in order to facilitate the description of the present invention described below. Is.

Next, the operations of the selector 13 and the NXOR gate 14 of FIG. 1 will be described with reference to FIGS. 4 and 5.
First, FIG. 4 illustrates a configuration example of the selector 13, and in FIG. 4, 13a and 13b are multiplexers. The multiplexers 13a and 13b input the count value C and the selection signal S, and output the frequency division upper digit Y1 and the frequency division lower digit Y0. The selection signal S is set by a microcomputer (not shown) corresponding to the division ratio of 1 / K.

In FIG. 4, in order to further simplify the explanation, it is assumed that the count value C is binary and the lower 8 bits C (7), ~ C (1), and C (0) are used, and the selection signal S is the same. It is defined as S (2), S (1), and S (0) in binary 3 bits. Then, the multiplexers 13a and 13b select one from eight inputs and output it by the selection signals S (2) to S (0) as shown in the truth table of FIG. Here, the multiplexer 13a is input from the C (0), and the multiplexer 13b is input from the C (1). As a result, two consecutive bits from the count values C (7) to C (0) are output to the outputs Y1 and Y0 of the multiplexers 13a and 13b.
Table 1 below shows the combinations of the value of the selection signal S and the signals output to the outputs Y1 and Y0. The division ratio obtained by the selection signal S is also shown in Table 1, and this division ratio will be described later. Since FIG. 4 shows the count value C as an example of the lower 8 bits in binary, the selection signal S cannot be used at 7 in Table 1.

(Table 1)

The frequency-dividing A-phase signal A2 and the frequency-dividing B-phase signal B2 are generated by using the selector 13 and the NXOR gate 14 described in FIG. 4, and the generation will be described next with reference to FIG. FIG. 5 shows the generation of the divided A-phase signal A2 and the divided B-phase signal B2 obtained by dividing the A-phase signal A1 and the B-phase signal B1 output by the incremental encoder 1 by 1/2 as an example. This is the case where the selection signal S is 1 in Table 1 above.
First, (a), (b), (d), (e), and (f) of FIG. 5 represent the same signals as those of the same reference numerals in FIG. 3, and these explanations are described. Omit.

Then, (h), (i), and (j) of FIG. 5 represent the temporal transition of C (0), C (1), and C (2) of the lower three bits of the count value C. C (2) of (j) in FIG. 5 is the frequency-divided A-phase signal A2. Then, (p) of FIG. 5 represents the values of C (2) and C (1) in decimal, and shows that the values change continuously in the range of 0 to 3.

Next, (q) in FIG. 5 represents the output of the NXOR gate 14, and the inputs of the NXOR gate 14 are C (2) and C (1). Here, NXOR is the negation of the exclusive OR, and the value of (q) in FIG. 5 is as follows at the times T51 and T52 in FIG.
From C (1) = 0 and C (2) = 1 at time T51 with reference to (i) and (j) in FIG. 5 → 0
From C (1) = 1, C (2) = 1 at time T52 → 1
As described above, (q) in FIG. 5 has the waveform shown in the figure, and this becomes the frequency-divided B-phase signal B2. With reference to (j) and (q) of FIG. 5, the frequency division A phase signal A2 is 90 degrees ahead of the frequency division B phase signal B2 during normal rotation, and the frequency division is 90 degrees ahead of the frequency division B phase signal B2 during reverse rotation. The A-phase signal A2 is delayed by 90 degrees, which is the same as the original A-phase signal A1 and the B-phase signal B1.

As described above with reference to FIGS. 4 and 5, the ABZ phase frequency divider 2 according to the present invention transmits the A-phase signal A1 and the B-phase signal B1 output by the incremental encoder 1 to the selector 13 and the NXOR gate. 14 generates the divided A-phase signal A2 and the divided B-phase signal B2, which maintain the mutual phase relationship and divide the frequency by 1 / K.

So far, according to the present invention, the frequency division of the A-phase signal A1 and the B-phase signal B1 output by the incremental encoder 1 has been described, but in addition to this, the frequency division of the Z-phase signal Z1 has been described in FIG. A description will be given with reference to FIGS. 6 and 7. First, in FIG. 1, the frequency dividing Z phase signal Z2 is generated from the frequency dividing Z phase pulse width setting device 15 by the OR gate 24.

Subsequently, FIG. 6 illustrates the mechanism for generating the frequency-divided Z-phase signal Z2, and FIG. 6 (g) shows the temporal transition of the count value C output by the counter 12. The values ZW1, ZW2, ZW3, and ZW4 possessed by the divided Z-phase pulse width setters 15, 17, 19, and 22, respectively, are added to (g) of 2. Here, the divided Z-phase pulse width setters 15, 17, 19, and 22 are also referred to as divided Z-phase pulse width setters ZW1, ZW2, ZW3, and ZW4.
Next, FIG. 6 (t) represents the frequency-divided Z-phase signal Z2 generated by the present invention. The frequency-divided Z-phase signal Z2 is 1, for example, from time Ta to Tc, from Td to Te, and from Tf to Th, which is described in Table 2 by the frequency-divided Z-phase pulse width setter 15 to the OR gate 24. Is generated as follows.

(Table 2)

Explaining the table 2, since the count value C exceeds the frequency-divided Z-phase pulse width setter ZW4 during the time Ta to Tb, the comparator 23 becomes active and outputs 1, and the above-mentioned The frequency-divided Z-phase signal Z2 becomes 1 via the OR gate 24.
Next, between the time Tb and Tc, the count value C is larger than the frequency dividing Z-phase pulse width setting device ZW2 and less than the frequency dividing Z-phase pulse width setting device ZW3. 20 becomes active and 1 is output, and the frequency dividing Z-phase signal Z2 becomes 1 via the AND gate 21 and the OR gate 24.
The time Td to Te and the time Tg to Th are the same as the time Tb to Tc, and the description at this time is omitted.
Next, since the count value C is less than the frequency dividing Z-phase pulse width setter ZW1 between the time Tf and Tg, the comparator 16 becomes active and outputs 1, and the minute is output via the OR gate 24. The peripheral Z-phase signal Z2 becomes 1.
Here, the ZW1 and ZW2 are negative integers, and the ZW3 and ZW4 are positive integers. Further, when the count value C is a value other than the range shown in Table 2, the frequency dividing Z-phase signal Z2 is 0.

As described above, the mechanism for generating the frequency-divided Z-phase signal Z2 has been described with reference to FIG. 6, but will be further described with reference to FIG. FIG. 7 shows the waveform of the signal of each part with the passage of time, and (a), (b), (d), (e), (h), (i), and ( j) represents the same signal as that of the same reference numeral in FIG. 5, and the description thereof will be omitted. The rotation direction of the incremental encoder 1 is represented by forward rotation, stop, and reverse rotation in FIG. 5, but is represented only by forward rotation in FIG. 7.

(C) of FIG. 7 is the Z-phase signal Z1 output by the incremental encoder 1, and the period of 1 of the Z-phase signal Z1 is the same as one cycle of the A-phase signal A1 as shown in the figure, for example. Here, in FIG. 7, the frequency division ratio 1 / K is set to 1/4, the value of the selection signal S is set to 2 in Table 1, and the count values C (3) and C (2) are used. (K) represents the count value C (3), that is, the frequency division A phase signal A2. Then, FIG. 7 (r) shows that the values of C (3) and C (2) are represented by decimal numbers and change continuously in the range of 0 to 3.

Next, (s) in FIG. 7 represents the output of the NXOR gate 14 that inputs the C (3) and C (2), and this becomes the frequency-divided B-phase signal B2. Then, the divided A-phase signal A2 and the divided B-phase signal B2 according to (k) and (s) of FIG. 7 are obtained by dividing (a) and (b) of FIG. 7 by 1/4. Become.

And (t) of FIG. 7 shows the transition of the frequency-divided Z-phase signal Z2, which shows the frequency-divided Z-phase pulse width setters ZW1 to ZW4 in Table 3 in Tables 2 and 6. It is a value. The period during which the frequency-divided Z-phase signal Z2 becomes 1 is four times the period during which the frequency-divided Z-phase signal Z2 is 1 corresponding to the division ratio of 1/4, and one cycle of the frequency-divided A-phase signal A2 Is the same as.
(Table 3)

As described above, the ABZ phase frequency divider 2 according to the present invention mutually exchanges the A phase signal A1, the B phase signal B1, and the Z phase signal Z1 output by the incremental encoder 1 as described with reference to FIG. The frequency division A phase signal A2, the frequency division B phase signal B2, and the frequency division Z phase signal Z2 are generated by dividing the frequency division at a predetermined frequency division ratio of 1 / K while maintaining the phase relationship of.

Next, the Z-phase signal Z1 output by the incremental encoder 1 is a signal of one pulse per rotation, and the pulse width is usually narrow. Therefore, the waveform of the Z-phase signal Z1 is often deformed by noise, and reception may fail in another device having a slow response. However, in the ABZ phase frequency dividing device 2 according to the present invention, by changing the value of the frequency dividing Z phase pulse width setting device shown in FIGS. 6 and 2, the frequency dividing device having an arbitrary wide pulse width can be used. The Z-phase signal Z2 is generated to eliminate the influence of noise, and it is possible to surely use it in combination with another device having a slow response.

By using the ABZ phase frequency divider of the present invention, a high-resolution incremental encoder can be used in combination with a recent control device having excellent performance, and at the same time, a conventional or third-party display device or monitor device, or another device. It can be used with the control device of.

1 Incremental encoder 2 ABZ phase divider 11 Pulse converter 12 Counter 13 Selector 14 NXOR gate 15, 17, 19, 22 Divider Z phase pulse width setter 16, 18, 20, 23 Comparator 21 AND gate 24 OR gate 13a, 13b multiplexer

Claims (2)

It is composed of an incremental encoder and a frequency divider that inputs A-phase signal, B-phase signal, and Z-phase signal output by the incremental encoder.
The incremental encoder outputs the A-phase signal and the B-phase signal, which are pulse trains having a phase difference of 90 degrees according to rotation, and outputs the Z-phase signal for each rotation.
The frequency divider has a built-in pulse converter and counter,
The pulse converter inputs the A-phase signal and the B-phase signal, and has a multiplication signal having a frequency obtained by multiplying the frequencies of the A-phase signal and the B-phase signal by an integral integral, and a rotation direction signal indicating the rotation direction of the incremental encoder. Detected,
The counter is an up / down counter that receives the multiplication signal, the rotation direction signal, and the Z phase signal as inputs, and the counter counts the multiplication signal up or down according to the rotation direction signal. outputs a value, also the counter, the Z-phase signal is a one to clear the previous SL count value when it becomes active,
The frequency dividing device is provided with a selector, a frequency dividing AB phase generator, a plurality of frequency dividing Z phase pulse width setters, and a comparator.
The selector selects and outputs a continuous 2-bit signal from the count value output by the counter, and outputs the signal.
The frequency division AB phase generator divides the frequency from the 2-bit signal by a frequency division ratio of 1 / K (K is a positive integer) while maintaining the phase relationship between the A phase signal and the B phase signal. , It is characterized by generating a frequency-divided A-phase signal and a frequency-divided B-phase signal.
The plurality of divided Z-phase pulse width setters and the comparator constantly monitor the count value, and the frequency division ratio is 1 with respect to the signal width of the previous period Z-phase with the count value as the base point. The pulse width is K, which is the inverse of / K, and a frequency-divided Z-phase signal synchronized with the Z-phase signal is generated.
The A-phase signal, dividing the B-phase signal, and Z-phase signals the division A phase signal divided, dividing B-phase signal, and dividing the Z-phase signal ABZ phase to generate was feature a apparatus. The ABZ phase divider device according to claim 1 is characterized in that the pulse width of the frequency divider Z phase signal is made variable by changing the values of the plurality of frequency division Z phase pulse width setters. Phase divider.

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